// Copyright (c) 2012 Ben Reynwar

// Released under MIT License (see LIC!"#t$t)

/%
I&ple&ents a 'utter(y &odule )or a **T#

Ta+es co&ple$ nu&'ers ,- ./- .B and returns
0/ 1 ./ 2 ,%.B
0B 1 ./ 3 ,%.B

It can ta+e input no &ore )re4uently than once e5ery
two steps# This is so- hope)ully- less &ultiply
'loc+s can 'e used#
%/
module butterfy
#(
// The width o) &6in#
parameter M_WDTH = 0,
// The width o) the input- output and twiddle )actors#
parameter X_WDTH = 0
)
(
input wire clk,
input wire rst_n,
// &6in contains data that passes through this 'loc+ with no change#
// It is delayed )or 7 counts li+e $6nd38y6nd#
input wire [M_WDTH-1:0] m_in,
// The twiddle )actor#
input wire signed [2*X_WDTH-1:0] ,
// ./
input wire signed [2*X_WDTH-1:0] !",
// .B
input wire signed [2*X_WDTH-1:0] !b,
// "et to 1 when new data is present on inputs#
// Cannot 'e set to 1 )or two consecuti5e steps#
input wire !_n#,
// delayed 5ersion o) &6in#
output reg [M_WDTH-1:0] m_$ut,
// 0/ 1 ./ 2 ,%.B
// 0B 1 ./ 3 ,%.B
// ,hen y6nd11 y6re and y6i& are outputing 0/#
// The step a)ter they are outputting 0B#
output wire signed [2*X_WDTH-1:0] y,
output reg y_n#
)%
// "et wire to the real and i&ag parts )or con5enience#
wire signed [X_WDTH-1:0] _re%
wire signed [X_WDTH-1:0] _im%
assign _re = [2*X_WDTH-1:X_WDTH]%
assign _im = [X_WDTH-1:0]%
wire signed [X_WDTH-1:0] !"_re%
wire signed [X_WDTH-1:0] !"_im%
assign !"_re = !"[2*X_WDTH-1:X_WDTH]%
assign !"_im = !"[X_WDTH-1:0]%
wire signed [X_WDTH-1:0] !b_re%
wire signed [X_WDTH-1:0] !b_im%
assign !b_re = !b[2*X_WDTH-1:X_WDTH]%
assign !b_im = !b[X_WDTH-1:0]%
reg signed [X_WDTH-1: 0] y_re%
reg signed [X_WDTH-1: 0] y_im%
assign y = &y_re, y_im'%

// 9elayed &6in#
reg signed [M_WDTH-1:0] m[1:0]%
// 9elayed ./
reg signed [X_WDTH-1:0] ("_re[1:0]%
reg signed [X_WDTH-1:0] ("_im[1:0]%
// 9elayed .B
reg signed [X_WDTH-1:0] (b_re%
reg signed [X_WDTH-1:0] (b_im%
// 9elayed ,
reg signed [X_WDTH-1:0] _re%
reg signed [X_WDTH-1:0] _im%
// 9elayed $6nd
reg signed !_n#_$l#[2:0]%
// "torage )or output o) &ultipliers
reg signed [2*X_WDTH-1:0] (b_m1%
reg signed [2*X_WDTH-1:0] (b_m2%
// , % .B
reg signed [X_WDTH-1:0] (b_re%
wire signed [X_WDTH-1:0] (b_im%
assign (b_im = ((b_m1 >>> (X_WDTH-2)) + ((b_m2 >>> (X_WDTH-2))%
reg signed [X_WDTH-1:0] (b_im_$l#%
// ,ire o) longer length )or adding or su'stracting ,%.B to ./#
// I) we don:t create longer wires )or the& then we can lose the
// high 'it# The contents o) these wires are downshi)ted into a
// nor&al si;e )or use#
wire signed [X_WDTH)0] (1_re_bi*%
wire signed [X_WDTH)0] (1_im_bi*%
assign (1_re_bi* = ("_re[0] + (b_re%
assign (1_im_bi* = ("_im[0] + (b_im%
wire signed [X_WDTH)0] (2_re_bi*%
wire signed [X_WDTH)0] (2_im_bi*%
assign (2_re_bi* = ("_re[1] - (b_re%
assign (2_im_bi* = ("_im[1] - (b_im_$l#%

always + (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
y_n# <= 1,b0%
end
else
begin
// "et delay )or $6nd6old and &#
!_n#_$l#[0] <= !_n#%
!_n#_$l#[1] <= !_n#_$l#[0]%
!_n#_$l#[2] <= !_n#_$l#[1]%
m[0] <= m_in%
m[1] <= m[0]%
m_$ut <= m[1]%
// "T/< 1
if (!_n#)
begin
("_re[0] <= !"_re%
("_im[0] <= !"_im%
_re <= _re%
_im <= _im%
(b_re <= !b_re%
(b_im <= !b_im%
// ,e per)or& two &ultiplications )or calculate the real part
// o) ,%.B#
(b_m1 <= !b_re*_re%
(b_m2 <= !b_im*_im%
if (!_n#_$l#[0])
-#is.l"y(/01121) 34 *$t ne #"t" t$ ste.s in " r$5/)%
end
if (!_n#_$l#[0])
// "T/< 2
begin
// !ow start the &ultiplications )or the i&ag part o) ,%,B#
(b_m1 <= (b_re*_im%
(b_m2 <= (b_im*_re%
// 9ownshi)t the &ultiplied results into nor&al width and
// su'stract the&#
// =5er(ow is not possi'le upon su'straction since we
// +now that , and .B 'oth ha5e &agnitude less than 1
// so their &ultiple &ust also#
(b_re <= ((b_m1 >>> (X_WDTH-2)) - ((b_m2 >>> (X_WDTH-2))%
end
// "T/< 7
if (!_n#_$l#[1])
begin
// ,e only need to shi)t the re4uired delayed data
// with ./ e5ery two steps since new input cannot
// arri5e &ore )re4uently than that#
// ./ is needed 'y a wire calculating ;26re6'ig and ;e6i&6'ig
// ne$t step#
("_re[1] <= ("_re[0]%
("_im[1] <= ("_im[0]%
// =utput 0/#
y_n# <= 1,b1%
y_re <= (1_re_bi* >>> 1%
y_im <= (1_im_bi* >>> 1%
(b_im_$l# <= (b_im%
end
// "T/< >
if (!_n#_$l#[2])
begin
// =utput 0B#
y_n# <= 1,b0%
y_re <= (2_re_bi* >>> 1%
y_im <= (2_im_bi* >>> 1%
end
end
end
endmodule