1-(

B. Preliinar! "ork

). 1. *onsider the OR gate implemented using practical diodes "ith %
D(on)
+ ,.- % as
gien in .ig. 1.(.


.ig. 1.(. OR &ate /mplemented 0sing 1ractical Diodes "ith %
D(on)
+ ,.- %

*omplete the missing entries in the oltage and logic truth tables gien belo"..


Voltage Truth Table Logic Truth Table

). '. !he AND gate implemented using practical diodes "ith %
D(on)
+ ,.- % using diode
logic is gien belo" in .ig. 1.2.


.ig. 1.2. AND &ate /mplemented 0sing 1ractical Diodes "ith %
D(on)
+ ,.- %

*omplete the missing entries in the oltage and logic truth tables gien belo".


Voltage Truth Table Logic Truth Table

). (. *onsider the serially connected AND gates (implemented using diode logic "ith
practical diodes$ %
D(on)
+ ,.- %) as gien in .ig. 1.3. Determine and "rite do"n
the oltage alues at the outputs indicated.
A B Y
0 0
0 1
1 0 ..
1 1
V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0
0 5
5 0
5 5
V
Y

V
CC

D
A

V
B

V
A

D
B

R
A B Y
0 0
0 1
1 0 ..
1 1
V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0
0 5
5 0
5 5
V
Y

V
B

V
A

R
D
A

D
B


1-'


Fig. 1.2. AND Gate Diode Logic Implementation

Assuming the diodes are ideal$ the oltage truth table of the aboe AND gate is as
gien in !able 1.'.a. !he corresponding logic truth table is in !able 1.'.b

!able 1.1. %oltage !ruth !able and Logic !ruth !able of the AND &ate


(a) (b)




A B Y
0 0 0
0 1 0
1 0 0
1 1 1
V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0 0
0 5 0
5 0 0
5 5 5
V
Y

V
CC

D
A

V
B

V
A

D
B

R

1-2



.ig. 1.3. %oltage Degradation in the serially connected AND &ates using practical
diodes "ith %
D(on)
+ ,.- %

). 2. !he oltage degradation problem may be oercomed by adding a diode and a
resistor as sho"n in leel shifted AND gate as sho"n in .ig. 1.4. .or the choice of
R
1
+ 1, # and R
'
+ 1,, #, the lo" output oltage is , olt compared to the ,.-
olts output for the normal AND gate. 5o"eer the high output oltage is ery
close to 3 %.

.ig. 1.4. Leel 6hifted AND &ate

*omplete the missing entries in the oltage truth table gien belo".


Voltage Truth Table



V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0
0 5
5 0
5 5
V
Y

V
CC
=5V
D
A

V
B

V
A

D
B

R
1

1 k
D
Y

R
2
100 k
0 V
0 V
. V
5 V
. V
5 V
. V
5 V
. V

1-3

C. Experimental Work

*. 1. *onctruct the OR gate diode logic gien belo" in .ig. 1.-.



.ig. 1.-. OR &ate Diode Logic /mplementation

Apply the gien inputs and complete the missing entries in the oltage and logic
truth tables gien belo"..


Voltage Truth Table Logic Truth Table

*. '. *onctruct the AND gate diode logic gien belo" in .ig. 1.7.



.ig. 1.7. AND &ate Diode Logic /mplementation

Apply the gien inputs and complete the missing entries in the oltage and logic
truth tables gien belo"..


Voltage Truth Table Logic Truth Table


A B Y
0 0
0 1
1 0 ..
1 1
V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0
0 5
5 0
5 5
V
Y

V
CC

D
A

V
B

V
A

D
B

R = 10 k
A B Y
0 0
0 1
1 0 ..
1 1
V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0
0 5
5 0
5 5
V
Y

V
B

V
A

R=10 k
D
A

D
B


1-4

*. (. *ontruct the Leel 6hifted AND &ate gien in .ig. 1.8.


.ig. 1.8. Leel 6hifted AND &ate

Apply the gien inputs and complete the missing entries in the oltage and logic
truth tables gien belo"..


Voltage Truth Table Logic Truth Table


A B Y
0 0
0 1
1 0 ..
1 1
V
A

(volt)
V
B
(volt)
V
Y
(volt)
0 0
0 5
5 0
5 5
V
Y

V
CC
=5V
D
A

V
B

V
A

D
B

R
1

1 k
D
Y

R
2
100 k