Modeling and Simulation study of advanced

MOSFETs for ultra low power analog/RF

applications

Thesis Submitted for the Degree of

Doctor of Philosophy (Engineering)

Electronics and Telecommunication Engineering

Jadavpur University
2009

By

N.Mohankumar
Department of Electronics and Telecommunication Engineering
Jadavpur University
 Kolkata-700032

DEDICATED TO MY BELOVED PARENTS

 Ind
ex No. 52/08/E
1. Title of the thesis :

“Modeling and Simulation study of advanced MOSFETs for

ultra low
power analog/RF applications”

2. Name, Designation & Institution of Supervisor/s :

Prof. C.K.Sarkar
Professor,
Department of Electronics & Telecommunication
Engineering,
Jadavpur University,
Kolkata-700032.

3. List of Journal Publications :

[1] N.Mohankumar, Binit Syamal and C.K.Sarkar,

“Performance and
Optimization of Dual Material Gate (DMG) Short Channel
BULK
MOSFETs for Analog/Mixed Signal Applications”,
International
Journal of Electronics, Vol. 96, No. 6, pp. 603-611, 2009.

[2] N.Mohankumar, Binit Syamal and C.K.Sarkar,

“Investigation of Novel
Attributes of Single Halo Dual-Material Double Gate
MOSFETs for
Analog / RF Applications”, accepted and to be published in
Micro
Electronics Reliability.
[3] N.Mohankumar, Binit Syamal and C.K.Sarkar, “Influence
of Channel
and Gate Engineering on the Analog and RF Performance
of DG
MOSFETs”, under review in IEEE Transactions on Electron
Devices.

[4] N.Mohankumar, Binit Syamal and C.K.Sarkar,

“Performance of gate-
Engineered Symmetric Double Gate MOS devices and
circuits for
ultra low power analog and RF applications”, communicated
and
under review in Micro Electronics Reliability.

[5] N.Mohankumar, Binit Syamal, Manas Saha and C.K.Sarkar,

“A new
Threshold Voltage Model for Asymmetric Double gate
MOSFETs in the
Nano scale regime”, communicated and under review in
International
Journal of Electronics.

4. List of Patents :

Nil

5. List of Conference Presentations in National/

International :

[1] N.Mohankumar, Binit Syamal, Manas Saha and C.K.Sarkar,

“An
Analytical Drain current Model for Undoped 4T asymmetric
Double
Gate MOSFETs”, as Invited Talk in IEDST 2009, IEEE
Sponsored
 International Conference conducted by IIT, Mumbai and
available
online at IEEE Explore.

[2] N.Mohankumar, Binit Syamal, C.K.Sarkar and S.Ravi

“Influence of gate
Engineering on the analog performance of DG MOSFETs”, at
ICCNU
2008, IEEE sponsored International Conference conducted by
Chettinad
college of Engineering & Technology, Tamilnadu, India and
available
online at IEEE Explore.

[3] N.Mohankumar, Swapnadip De, Angsuman Sarkar and

C.K.Sarkar
“Effect of fringing fields in modeling of subthreshold surface
potential
in DMG MOSFETs “, as Invited Talk at ICECE 2008, IEEE
sponsored
International conference conducted at Dhaka, Bangladesh,
pp 148-151
and available online at IEEE Explore.

CERTIFICATE FROM THE SUPERVISOR/S

This is to certify that the thesis entitled “Modeling and Simulation study of
advanced MOSFETs for ultra low power analog/RF applications” submitted by
N.Mohankumar, who got his name registered on 03.08.2008 for the award of Ph.D.
(Engineering) degree of Jadavpur University is absolutely based upon his own work
under the supervision of Prof. (Dr.) C. K. Sarkar and that neither his thesis nor any
part of the thesis has been submitted for any degree/diploma or any other academic
award anywhere before.

Signature of the Supervisor

and date with Office Seal

Acknowledgement
CONTENT
Chapter 1 Introduction 1

1.1 CMOS Scaling and VLSI 1

1.2 ITRS and TCAD 3
1.3 Justification of the work 5
1.4 Status of the existing work 8
1.5 Scope of the work
1.6 Organization of the thesis
References
Chapter 2 Challenges and Scaling issues of CMOS devices in 11
the nano regime : A Review

2.1 Physics of Scaling 11

2.2 Device parameters for superior performance 12
2.2.1 Definition of threshold voltage 12
2.2.2 Maximum Transconductance definition 13
2.2.3 Constant drain current definition
2.3 Historical trends 14
2.3.1 International Technology roadmap for semi
conductors 28
2.4 Gate Oxide Scaling 29
2.4.1 Ultra thin gate oxides-feasibility and limitations
2.4.2 Limitations 31
2.5 Gate Length Scaling
2.5.1 Ballistic Transistors 35
2.6 Effects of device Scaling-Short Channel Effects
2.7 Interconnects 40
2.8 Device Engineering to control Short Channel Effects 42
2.8.1 Source/Drain Engineering 43
2.8.2 Channel Engineering
2.8.2.1 Vertical substrate Engineering-Retrograde
2.8.2.2 Lateral channel Engineering- Halo
2.8.2.3 Hot carrier effects - Engineered MOSFETs
2.9 Silicon On Insulator Technology
2.9.1 Overview
2.9.2 Device Physics
2.9.2.1 PD-SOI
2.9.2.2 FD-SOI
2.9.3 Advantages of SOI CMOS over conventional
 Bulk Technology
2.9.4 Fabrication of SOI MOSFET
2.9.5 Challenges of SOI Technology
2.9.5.1 Kink effect
2.9.5.2 Single transistor Latch up
2.9.5.3 Reduced drain breakdown voltage
2.10 Metal Gate Technology – Gate Engineering
2.11 High-K dielectric Technology
2.11.1 Issues with High-K materials
2.12 Double Gate MOSFETS
2.12.1 Device Physics
2.12.2 Types of DG MOSFETs
2.12.3 Implementation of DG MOSFETs
2.13 FINFETs and Surrounding Gate MOSFETs
Summary
References

Chapter 3 A New Threshold voltage model for Asymmetric

Double Gate MOSFETs
3.1 Introduction
3.2 Electrostatic Potential Modeling
3.3 Results and Discussion
3.4 Summary
References
Chapter 4 Performance and Optimization of Dual Material 89
Gate (DMG) short channel bulk MOSFETs
4.1 Introduction
4.2 Device structure and simulations 89
4.3 Performance and Optimization 91
4.3.1 Improvement of carrier transport efficiency 92
4.3.2 Short channel effects suppression and output 92
resistance 94
4.3.3 Performance comparison in superthreshold and 97
subthreshold region of operation 99
4.3.4 AC analysis of DMG devices 101
4.3.5 Circuit Performance 102
4.4 Summary 109
References 110

Chapter 5 Performance of Gate Engineered symmetric Double 113

Gate MOS devices
5.1 Introduction
5.2 Device structure and simulation parameters 113
5.3 Simulation results and Discussion 114
5.4 Analog and RF Performance 115
5.5 Circuit Performance 116
5.6 Summary
References

Chapter 6 Influence of the Channel and the Gate engineering 131

on the analog and RF performance of DG
MOSFETs
6.1 Introduction 131
6.2 Graded channel in SOI/DG MOSFET 134
6.3 Fabrication of GC DG MOSFET 135
6.4 Optimization of the length and the doping
concentration in DG halo MOSFETs 137
6.5 Single Metal Double Gate MOSFET 147
6.6 Dual Metal Double Gate MOSFET 148
6.7 Performance analysis of channel and gate engineered
Double Gate MOSFETs 151
6.7.1 Digital Performance
6.7.2 Analog Performance
 6.7.3 RF analysis
6.7.4 Effects on channel Mobility
Summary
References

Chapter 7 Investigation of novel attributes of Single Halo Dual

Material DG MOSFETs for analog/RF applications
Introduction
7.1 Device structures and parameters
7.2 Simulation Results and Discussion
7.3 7.3.1 Analog Performance
7.3.2 RF Performance
7.3.3 Circuit Applications
Summary
7.4 References

Chapter 8 Overview of TCAD tools 165

8.1 Technology CAD
8.2 Sentaurus Process
8.3 Sentaurus Structure Editor 165
8.4 Sentaurus Device 166
8.4.1 Physical approach of the tool
8.4.1.1 Transport equations
8.4.1.2 Poisson and continuity equations
8.4.1.3 Drift Diffusion Model
8.4.1.4 Quantization Models
8.4.1.5 Density Gradient Model
8.4.1.6 Mobility Models
8.4.1.6.1 Doping dependent mobility
Degradation
8.4.1.6.2 Mobility degradation at interfaces
8.4.1.6.3 High field saturation
8.4.2 Mathematical approach of the tool
8.5 Inspect
8.6 Tecplot
8.6.1 Loading data files
8.6.2 Creating plots
8.7 Sentaurus Work bench
 8.7.1 Starting Sentaurus Work bench
8.7.2 Loading Sentaurus Work bench projects
8.7.3 Calibration
Summary
References

Chapter 9 Conclusion and Scope of future work

Synopsis
 CMOS ICs have conquered the electronic market with
devices for computing, communication, entertainment,
automotive, and other applications simultaneously with
improvements in cost, speed, and power consumption. It is
believed that this trend of rapid improvements will continue in the
near future. Since the 1960’s the price of one bit of semiconductor
memory has dropped to 100 million times and the trend continues
as we go for more and more advanced devices with relatively less
cost and better performance. CMOS technology went through a lot
of advancement following Moore’s Law to achieve higher packing
density and improved performance. Also, miniaturization of CMOS
devices has improved its cut-off frequency in the gigahertz range
that made it also attractive for analog and mixed-signal
applications.

As the end of Semiconductor Industry Association (SIA)

roadmap is being approached, the double gate (DG) devices are
considered to be one of the most promising technologies for the
future microelectronics industry due to its excellent immunity to
short channel effects and higher drive on current. Bulk CMOS
devices scaled beyond 100nm regime gives rise to short-channel
effects, a major concern. The double gate or multi gate devices
provide a better scalability option due to its excellent immunity to
short-channel effects. Among the other advantages of DG MOSFETs
are the near 60mV/dec subthreshold slope, the low Drain-Induced-
Barrier-Lowering (DIBL) and the possibility of using lightly doped or
undoped body. The use of undoped body also results in an
enhanced mobility of the charge carriers and the elimination of
statistical fluctuation of dopant concentration. Undoped DG
MOSFETS provide the flexibility of using the metal gates with near
mid-gap work-function to control the threshold voltage Vt .

Volume inversion is another important phenomenon that is

observed in case of multi gate MOS devices where the inversion
charges instead of being confined near the Si-SiO2 interface spread
near the center of the channel and this is more evident in the
subthreshold regime. The charge carriers thus experience less
interface scattering than that of a regular bulk MOSFET. This results
in increased mobility and transconductance in double-gate devices
than the bulk CMOS transistors. Most of the researches on the
double gate devices carried out in the last few years mainly
focused on the digital applications rather than the analog/RF
applications. But the recent advancement of IC industry evinced lot
of interest on the System on Chip (SOC) applications where the
analog and the digital circuits are realized on the same chip. This
results in an increased functionality and the reduction of the size
and the cost.

Along with the applications in logic designs, CMOS

technology has also started dominating the RF market also which
was previously dominated by BICMOS, BJT and the MESFET
technologies. Due to rigorous scaling advantages, CMOS has
become a viable option for analog and RF applications and RF
system-on-chip. To improve the analog performance of DG
MOSFETs and also to provide better immunity to short channel
effects, various approaches such as the channel engineering using
halo implantation and the gate work-function engineering have
been proposed. The dual-material gate (DMG) devices show a great
promise in this regard. Dual-material gate technology was
proposed by Long et. al. way back in 1999. This so called gate work
function engineering allows the use of lightly doped or nearly
undoped body resulting in reduced mobility degradation effects in
the channel and improved performance.

We have derived a concise analytical threshold voltage model

for the deep submicron asymmetric DG MOSFETs by considering
the distribution of the minority carriers in the silicon channel. The
2-D Poisson equation is solved by considering both the depletion
and the mobile charges in the thin silicon body which proves the
accuracy of the model for both the subthreshold and super
threshold operations. It has also been noticed that the threshold
voltage adjustability is more for the thin silicon channels, thus
providing more flexibility in device designs.

In this work, we have systematically investigated the

subthreshold and the superthreshold analog performances as well
as the RF parameters for high frequency applications of n-channel
advanced CMOS devices with 100nm gate length. Lateral
asymmetric channel (LAC) and the Dual Metal Gate realized on the
double gate architecture have been investigated. Integrated
Systems Engineering (ISE) - Technology Computer-Aided Design
(TCAD) has been used for the realization and the analysis of all the
devices used in this study. All the device parameters are set as per
ITRS road map for the 100nm gate length.

In the case of the graded channel DG MOSFETs, the

optimization of halo doped length and the doping concentration is
also shown. In the case of the DG MOSFET with the dual metal gate
technology, the optimization of the length of the metals gates is
illustrated with the detailed simulation results. Analog parameters
like the transconductance ( g m ), the transconductance generation
factor ( g m / I D ), the early voltage ( VA ), the output resistance and the
intrinsic gain of all the devices have been investigated and
compared with that of the conventional DG MOSFETs. For RF
applications, the cut-off frequency and the gain bandwidth product
have been explored.

It reveals that as there is a transition from bulk CMOS

technology to SOI and multigate architectures of thin silicon
channel, the potential of channel engineering technique decreases
considerably due to increasing field dependent mobility
degradation along the channel. On the other hand, the double gate
MOS transistor with the dual metal gate technology that adopts the
same undoped channel with increased carrier transport efficiency
shows improved analog/RF performance parameters compared to
that of the conventional architecture and thus may be suitable for
SoC applications in the nano regime.
 ________________
CHAPTER

1
________________

INTRODUCTION

1.1 CMOS SCALING & VLSI

Since the invention of the first electronic calculation
machines, miniaturization has been a constant challenge to
increase the speed and to improve the package density by the
microelectronics industry. Electronic devices have brought, and will
bring in the future, a far increasing number of new functions to the
basic computing systems such as fast data computing,
telecommunication, and several kinds of actuations which are
collectively fabricated on the same physical object named as the
solid state circuit, the integrated circuit or the “chip”. Electronic
devices are so small, that billions of basic functions are accessible
in a hand held system. Moreover, their unit cost has been divided
by more than a factor of 100 millions over the past 30 years! The
collective fabrication of electronic devices coupled with the
increase of their speed has given a tremendous success, which is
unique in the history of mankind, to Micro and Nano electronics by
continuously introducing innovations in the fabrication process (Fig.
1). Linear scaling of the device dimensions to a quasi-nanometer
level allows building a complex system integrated on a chip which
reduces drastically their volume and power consumption per
function, whilst tremendously increasing their speed [1]-[4].
Fig. 1.1: Evolution of microelectronics devices since the invention
of integrated circuits in 1958. On the double Y-axis, the number
of transistors per chip (on the left hand side) and their critical
dimension (gate length) (right hand side) are reported.
Fabrication technology (arrows) and System (bubble) innovations
are indicated.

At present, in high-performance processor technology, the physical

gate length of a transistor is reaching into the sub-100 nm regime
with a gate oxide thinner than 20 Å. In research laboratories,
transistors are being fabricated which might be the prototypes of
the last generation of CMOS devices based on the conventional
structures and the materials. Conventional scaling based on the
reduction of feature sizes obviously cannot continue forever.
The aggressive scaling of the CMOS technology in the deep
submicrometer regime gives rise to the short channel effects
(SCEs). The various undesirable SCEs are the threshold voltage
roll-off, the channel length modulation, the drain induced barrier
lowering (DIBL), the punch through, the velocity saturation, the
increased subthreshold leakage, the transconductance
degradation, the increased parasitic capacitances etc. Analog
performance parameters like the intrinsic gain, transconductance
generating factor, the early voltage, the output resistance etc. are
greatly affected by the SCEs. The undesirable mobility degradation
and increased parasitic capacitances drastically reduce the device
transconductance, the voltage gain and the noise performance.
Another major concern with scaling is the increased off-state
leakage current which in turn increases the power dissipation.

1.2 ITRS & TCAD

The international Technology Roadmap for Semiconductor
(ITRS), which was established by a group of experts, serves several
purposes within the semiconductors ground field. Its main objective
is to specify the device design parameters values as predicted for
the future device technology. In addition to that, it highlights the
challenges that might face the device scaling in the coming
generations. The (ITRS) main projection in the MOSFET and front-
end process areas is high performance while keeping the low power
logic. A major element of semiconductor device production is
devoted to the digital logic ICs as well as to the memory ICs. Key
considerations are the performance, the power, and the density
requirements.
The main focus is the high speed and the low power, which
drives the technology forward. The approaches for reaching these
goals are different. For high performance logic such as
microprocessors, the main objective is maximum chip speed, with a
tradeoff relative to the leakage current. For low power logic
approaches such as for mobile systems, the objective is to obtain
long operating time by minimizing the chip power dissipation,
particularly the static power dissipation, with a tradeoff of reducing
the MOSFET speed. Moreover, the aim of the Roadmap is to identify
key technical requirements and challenges critical to sustaining the
historical scaling of CMOS technology (i.e., according to Moore’s
Law [1]), and to encourage the needed research and development
to meet the challenges.
Technology Computer Aided Design (TCAD) can be a powerful
tool for reducing the design costs, improving the device design
productivity and obtaining the better device and the technology
designs. While the cost of building a state-of-the-art fabrication
plant continues to go up, computing the power has become a
relatively cheap product, due to Moore’s law and the resulting
improvements in the performance. Instead of going through an
expensive and time-consuming fabrication process, the computer
simulations can be used to predict the electrical characteristics of a
device design quickly and cheaply. Process modeling and
simulation of the fabrication process, can be predicted so that
physical characteristics such as the oxide thickness and the doping
distribution can be produced with high precision. Device modeling
and simulation can then be used to predict the electrical
characteristics of the given device structure.
An important benefit of using TCAD is that it can help in
understanding how semiconductor devices work. Assessment of
detailed device operation, such as how the energy levels and the
carrier (electrons and holes) distribution inside the device varies
with the biasing conditions, can provide valuable insights into the
relationship between a change in process conditions or device
design and the resulting impact on the device performance. These
quantities are often difficult to obtain experimentally. In contrast,
they are readily available through computer simulations, which
directly provide the feedback and the guidance for device design.

1.3 JUSTIFICATION OF THE WORK

According to the conventional scaling theory, if all the

dimensions and voltages of a MOSFET are scaled by a scaling factor
α, the circuit speed increases in proportion to the factor α and the
circuit density increases by α2 [5]. However, this scaling trend has
hit roadblocks due to various second order effects and the
fundamental physical limitations. These effects arise due to the
velocity saturation, the non-scaling of the subthreshold slope and
the built-in potential of the source/drain to body junctions, the
quantum effects, the poly depletion effects, and the high-field
effects etc. [6]-[9]. For CMOS digital applications, the transistor
efficiency is mainly determined by the on-current ( I on ) and the off-
current ( I off ) requirements of the device. By scaling the
technologies into sub 100 nm regimes, the drain induced barrier
lowering (DIBL), the channel length modulation (CLM), the charge
sharing, the gate tunneling and the band-to-band tunneling cause
I off to increase drastically, while I on is not increasing significantly
due to the reduced carrier mobility, and the source/drain parasitics.
Hence, maximizing the I on / I off is the primary objective for the
device design in logic circuits.
On the other hand, the above 2D effects also degrade the
transistor saturation current ( I DSAT ), the transconductance ( g m ), the
transconductance generation factor ( g m / I D ), and the output
resistance ( Ro ), which seriously limit the analog circuit performance
in the scaled technologies. Apart from these, degradation in the
cut-off frequency or unity current gain frequency ( fT ), the unity
power gain frequency ( f max ) and the maximum available power gain
(MAG) is an additional concern while scaling the technology for RF
applications. With fast growth in the radio-frequency (RF) wireless
communications market, the demand for high-performance but the
low-cost RF solutions is rising. This advanced performance of
MOSFETs is attractive for the High Frequency (HF) circuit design in
view of a system-on-a-chip realization, where the digital, the
mixed-signal base band, and the RF transceiver blocks would be
integrated on a single chip [10]–[14]. Thus the current research is
very much devoted in studying the performance of the scaled MOS
devices in case of analog and RF applications.
In a particular technology, the analog/ RF circuit performance
is affected by many other performance tradeoffs such as the signal
to noise ratio (SNR), the signal gain-bandwidths, the voltage
swings, the non-linearity, the power dissipation, the speed, and the
device layouts, with each parameter in turn related to other. All the
above requirements make the device design strategy for the
analog/RF circuit quite complex when compared to its logic
counterpart due to conflicting device performance requirements for
the analog and digital circuits. For example, a higher channel
doping is preferred for an analog device in order to reduce the
drain induced barrier lowering (DIBL) and the channel length
modulation (CLM) so as to achieve good drain conductance, where
as it results in a higher subthreshold slope in the logic devices[15]-
[20]. Similarly, although scaling down the power supply voltage is
always beneficial to the digital circuits if I on can be maintained
appropriately, it reduces the voltage swing, the dynamic range and
the voltage headroom in the analog circuits. Power supply scaling
also increases the power dissipation in the analog circuits. Hence,
any suggested device design approach for logic circuits must be
thoroughly evaluated for its analog/RF performance requirements
to meet the performance of mixed signal circuits, which is our
primary look out in this work.

1.4 STATUS OF THE EXISTING WORK

For the last few years, the integration issues of the analog
functions in the standard digital CMOS have been the topics of
research for several microelectronics researchers [13], [38], and
[39]. Quite a few researchers have suggested novel device
technologies to improve the performance of the MOS devices for
the System-on-Chip (SOC) applications. Within the conventional
CMOS process flow, many of these approaches need the gate work
function engineering, channel doping optimization and the
source/drain engineering for improving the mixed signal
performance.
The concept of a Dual-Material Gate technology is similar to
what was achieved by applying different gate-bias in split-gate [57]
structure first proposed by M. Shur. The challenge to satisfactorily
realize the split-gate FET is the inherent fringing capacitance
between the two metal gates which increases as the separation
between them is reduced. In 1999, Long et. al. [58] proposed a
new gate structure called the dual material gate (DMG)-MOSFET.
Unlike the asymmetric structures employing the doping
engineering in which the channel field distribution is continuous,
the gate-material engineering with the different work functions
introduces a field discontinuity along the channel, resulting in
simultaneous transport enhancement and suppressed the Short
Channel Effects (SCEs). Zhou [59] suggested a way in which the
Hetero-Material Gate (HMG) MOSFET can be fabricated by inserting
one additional mask in the bulk CMOS processing technology and
demonstrated the novel characteristics of this new type of MOSFET
by the simulation studies.
In the recent past, use of the halo doping in the channel has
been widely reported for controlling the short channel effects in the
sub 100 nm regimes. This doping scheme is well known to decrease
the DIBL and I off . On the other hand, the halo doping is also briefly
reported for its poor drain conductance under the long channel
conditions. Quite a few researchers also suggested the super steep
retrograde (SSR) devices for improved mixed signal performance
[21]-[51]. These devices show the higher carrier mobility, the
better short channel performance and the lower flicker noise levels
compared to the uniformly doped channel devices. However, due to
their higher substrate doping, the SSR devices show the reduced
drive currents below 0.1 μm technology nodes. In particular, during
the late nineties, the Single Pocket (SP), also known as the Single
Halo (SH) or the Lateral Asymmetric Channel (LAC), the doping
scheme has been reported for the excellent short channel
performance in the deep sub-micron technologies [38]-[39]. The
process for these devices is similar to the conventional halo doped
device, except for the absence of halo at the drain side. These
devices are primarily reported to exhibit the improved drive
currents in digital circuits. These devices are also briefly
characterized for improved the analog performance and the hot
carrier reliability in the deeply scaled technologies.
Once the scaling of a conventional MOS transistor with
an SiO2 gate insulator slows down due to physical limits, then
either a new materials system such as the high-k gate dielectrics,
the metal gate technology or an alternative device structure
such as a double-gate MOSFET may be needed to continue to
the improve performance. According to the device scaling physics,
increasing the channel doping concentration (NA) can effectively
suppress the SCEs. Frank et al. published their work quantifying
the dependence of the scale length on N A [15]. To a first order
approximation, their theory gives the following equation,
Λ = Wdm + (ε Si / ε I )TI , (1.1)
where Λ is the scale length, Wdm is the maximum channel depletion
depth, TI is the insulator thickness, and ε Si / ε I is the ratio of
dielectric constants of the silicon and the insulator. Depending on
the complexity of the channel doping profile, this theory predicts
that the minimum design length LG lies between Λ to 2Λ. It is quite
clear in Eqn. 1.1 that high N A results in reduced Wdm , therefore a
shorter scale length Λ. Also a thinner TI or higher ε I also results in
the better device scalability.
All recent studies indicate that the ultra-thin body double
gate (DG) SOI MOSFET is the ideal device structure for the ultimate
scaling [52]-[56]. In an ultra-thin body DG MOSFET, the second gate
electrode can significantly suppress the SCEs. Referring to Eqn. 1.1,
and noting that Wdm can be approximated by t si /2 ( t si is the silicon
body thickness), when t si is scaled to nanometer thicknesses (close
to Ti), clearly the scale length will downsize into the nanometer
regime. It should be also noticed that the high body doping is not
needed here, so the band-to-band tunneling junction leakage is no
longer a big concern. Moreover, the use of ultra-thin bodies will
result in the reduced metallurgical junction perimeter, therefore the
low junction capacitance. The bodies are typically lightly doped,
giving other advantages: 1) there is barely room for the floating
body effect (FBE) to come into play 2) the threshold voltage Vt
variation due to the dopant fluctuations can be eliminated 3) close-
to-the ideal subthreshold swing (60 mV/dec) can be achieved 4) the
severe mobility degradation due to the ion scattering might be
avoided. The different architectures of multigate SOI devices
proposed in the recent past are shown in the Fig. 1.2.
 Fig. 1.2:Different gate configurations for SOI devices: 1) single
gate; 2) double gate; 3) triple gate; 4) quadruple gate; 5) new
proposed Pi-gate MOSFET.

1.5 SCOPE OF THE WORK

In this work, we have systematically investigated the

subthreshold and the superthreshold analog performances as well
as the RF parameters for high frequency applications of n-channel
advanced CMOS devices with 100nm gate length. Lateral
asymmetric channel (LAC) [24] and the Dual Metal Gate [39]
realized on the double gate architecture have been investigated.
Integrated Systems Engineering (ISE) - Technology Computer-Aided
Design (TCAD) has been used for the realization and the analysis of
all the devices used in this study. All the device parameters are set
as per ITRS road map for the 100nm gate length.
In the case of the graded channel DG MOSFETs, the
optimization of halo doped length and the doping concentration is
also shown. In the case of the DG MOSFET with the dual metal gate
technology, the optimization of the length of the metals gates is
illustrated with the detailed simulation results. Analog parameters
like the transconductance ( g m ), the transconductance generation
factor ( g m / I D ), the early voltage ( VA ), the output resistance and the
intrinsic gain of all the devices have been investigated and
compared with that of the conventional DG MOSFETs. For RF
applications, the cut-off frequency and the gain bandwidth product
have been explored.
1.6 ORGANIZATION OF THE THESIS
This work focuses on the performance analysis of double gate
MOSFETs implemented with the channel engineering, the lateral
asymmetric channel as well as the gate engineering, the dual metal
gate technology. The primary goal of the work is to study the
analog and RF performance parameters in the 100nm gate length
regime.
Chapter 2 investigates the general issues related to the
CMOS scaling. The different aspects of the gate oxide thickness and
the gate length scaling in terms of the fabrication limits and the
leakage current issues are discussed. The different technology
aspects and the engineering techniques for the future MOSFETs are
presented in details.
Chapter 3 introduces a new analytical threshold voltage
model for the deep submicron asymmetric DG MOSFETs by
considering the distribution of the minority carriers in the silicon
channel. The 2-D Poisson equation is solved by considering both
the depletion and the mobile charges in the thin silicon body which
proves the accuracy of the model for the both subthreshold and
super threshold operations. It has also been noticed that the
threshold voltage adjustability is more for the thin silicon channels,
thus providing more flexibility in the device designs.
Chapter 4 illustrates a systematic investigation of the gate
work-function engineering such as the dual metal gate technology
on the analog and the RF performance of the bulk MOSFETs. An
optimization of the metal gate lengths is also shown with the
detailed simulation results. The different device parameters for the
analog applications are explored in the both the subthreshold and
superthreshold region of operation. Improvements in the drain-
current, the transconductance, the output resistance and the
voltage gain for various proportions of metals has been observed
for the both n-channel and p-channel devices.
Chapter 5 illustrates a systematic investigation of the gate
workfunction engineering such as the dual metal gate technology
on the analog and RF performance of the undoped symmetric
double gate MOSFETs with the gate underlap. The advantage of
using such a structure will improve the total gate capacitance since
the fringing fields are reduced and thus make it suitable for the RF
applications. An increased electron velocity at the source end
explains the higher carrier transport efficiency of the DMG
transistors. Various analog parameters like the drain current, the
transconductance, the transconductance generation factor, the
early voltage, the output resistance and the intrinsic gain of the
DMG devices are studied and compared with the SMG counterpart.
Chapter 6 will be devoted to the systematic investigation of
the channel engineering such as the lateral asymmetric channel on
the analog and RF performance of the double gate MOSFETs. The
optimization of the halo length and the doping concentration is
shown. In the next section, a comparative analysis is carried out
between the gate engineering (Dual Metal Gate) technology and
the channel engineering (Lateral Asymmetric Channel)
implemented on an undoped symmetric DG MOSFET for logic,
analog & RF applications.
In Chapter 7, we have clearly analyzed the effect of the
lateral asymmetric halo doping along with the dual metal
technology (SHDM) in respect of the digital, analog and the RF
performance and compared it with that of a single halo doped DG-
MOSFET (SH). The use of the dual metal gate technology enhances
the performances of the single halo doped DG MOSFET in respect of
the transconductance, the g m / I D ratio, the output impedance and
the intrinsic gain. The improvement is more prominent in the weak
inversion regime thus making it more applicable for the low power
subthreshold analog performance. The different RF-FOMs also show
improvement in the SHDM devices than the SH devices.
Chapter 8 provides a detailed overview of the two
dimensional device simulator Sentaurus TCAD used in the work.
The different aspects of the physics used in the simulation along
with the mobility models are explained with possible mathematical
equations. The details of the numerical simulation techniques
carried out to calculate the different electrical characteristics of any
electronic device are also explained.
Finally in Chapter 9 we draw the conclusions and make the
suggestions for the future work to be explored.
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 ______________
CHAPTER

2
_______________

CHALLENGES AND SCALING ISSUES OF CMOS

DEVICES IN THE NANO REGIME – A REVIEW

CMOS ICs have conquered the electronic market with

devices for computing, communication, entertainment,
automotive, and other applications simultaneously with
improvements in cost, speed, and power consumption. It is
believed that this trend of rapid improvements will continue in the
near future. Since the 1960’s the price of one bit of semiconductor
memory has dropped to 100 million times and the trend continues
as we go for more and more advanced devices with relatively less
cost and better performance. CMOS technology went through a lot
of advancement following Moore’s Law to achieve higher packing
density and improved performance. Also, miniaturization of CMOS
devices has improved its cut-off frequency in the gigahertz range
that made it also attractive for analog and mixed-signal
applications.
The primary engine that powered the ascent of electronics
is “miniaturization” [1]-[9]. By making the transistors and the
interconnects smaller, more circuits can be fabricated on each
silicon wafer and therefore each circuit becomes cheaper.
Miniaturization has also been instrumental in the improvements in
speed and power consumption.
This chapter begins with a description of several key device
design parameters and how they are influenced by device scaling
as predicted by first order theory. Several of the most important
second order effects are then discussed. Importantly the short
channel effects, Doping concepts including halo, different
technologies like bulk, SOI and various engineering concepts are
discussed in detail.

2.1 PHYSICS OF SCALING

Moore’s law [10], which states that the number of transistors

on a given chip can be doubled every two years, has been the
roadmap of the continuous reduction of CMOS device dimensions
since Gordon Moore, co-founder of Intel, first predicted it in 1965 (
Fig. 2.1). Over a period of a few decades, CMOS devices have been
scaled down to the sub-100nm regime. Although the basic device
geometry has remained relatively unchanged, the gate length has
been reduced from 10 mm in the 1970s to less than 0.1 µ m in
2001, and the gate oxide thickness from 1000 Å to less than 20 Å
[4]. The “Moore’s Law” is a succinct description of the persistent
periodic increase in the level of miniaturization.

Fig 2.1: Graph depicting Moore’s Law

 There are a number of different scenarios to scale CMOS
transistors to improve circuit performance and packing density.
One of the most widely used approaches is the constant electric
field scaling scenario proposed by Dennard et al. [7]- [9] (Fig. 2.2),
in which all linear dimensions of the transistor (e.g., the gate
length LG , the gate oxide thickness tox , etc.) and the operating
voltage VDD are reduced by the same factor α (>1).

Fig. 2.2: Dennard’s original figures illustrating the principles of

constant electric
field scaling

Essentially, this approach conserves the shape and the

magnitude of the electric field in the device region and thus the
device reliability is not degraded in this ideal scaling scenario.

2.2 DEVICE PARAMETERS FOR SUPERIOR

PERFORMANCE

The objective of device design is to obtain the devices with

high performance, low power consumption, high mobility, low cost
and high reliability in the field [11]. To make the design process
simpler, it is useful to refine these requirements in designer’s
perspective. Device parameters of particular interest include the
intrinsic capacitance ( Cox ), the parasitic capacitances ( C gsd ), the on-
current ( I on ), which determine the performance of digital circuits;
the worst-case off-current ( I off ), which is related to the static power
consumption of digital circuits; the transconductance ( g m ),
intrinsic output resistance ( Ro ) , unit-current-gain frequency ( fT )
and maximum frequency of oscillation ( f max ) which are important for
high performance analog and RF circuits. Table 2.I shows first
order relations for some of these design parameters.

S.N Performance trends for Digital/Analog applications

o
1.
Cox = εox /t ox
2.
I on = I ds (Vds = Vdd ,V gs = V dd )
3.
I off = I ds( Vds = Vdd, Vgs =Voff )
4.
Poff =I off Vdd
.
Pdynamic =
f Cload
. Vdd. 2

Table 2.I: Equations representing basic electrical quantities of a

MOS transistor.

The threshold voltage ( Vt ) is an especially important device

parameter that imposes a lower limit for the supply voltage ( Vdd ),
since for adequate current levels, we must have sufficient over-
drive Vg − Vt (= Vdd − Vt ) which in turn affects the power
consumption of the device. Vt is also related to I on and I off which
influences the device performance and the power consumption of
digital applications. For the proper operation of many analog
circuits, the matching of threshold voltages for the different MOS
devices is important.

2.2.1 Definition of Threshold Voltage

Conceptually, to turn on a MOS device, threshold voltage is

simply the applied gate-to- source voltage. Fig. 2.3a shows the
electrical characteristics of an ideal switch. As shown in the Figure,
the threshold voltage for such a hypothetical device is easy to
define. However, a MOS device is not an ideal switch. As a result,
arriving at a self consistent definition of the threshold voltage for
real devices is non-trivial.

Fig. 2.3: (a) Threshold voltage of an ideal switch (b) Maximum

gm definition of
threshold voltage.

2.2.2 Maximum gm Definition

The threshold voltage can be defined as the horizontal intercept of
the tangent to the I D - Vgs curve at the point of maximum g m (Fig.
2.3b) as follows:

Vgs ,maxg m
= maximize
Vgs

dI d
dV gs Vds
(2.1)
 I max g m = I d Vds
Vgs =Vgs ,max g m

(2.2)
I max g m
Vt = Vgs ,max gm −
dI d (2.3)
Vgs = Vgs ,max g
dVgs m

This definition does not depend on any arbitrarily chosen

parameters, and can therefore be used consistently across the
different technologies. However, it can be applied only for the
linear region (for low Vds ) and not the saturation region.

2.2.3 Constant Id Definition

Another commonly used definition of the threshold voltage is

based on an “appropriately” chosen reference drain current ( I ref ).
The threshold voltage at a given drain voltage is defined as the
gate voltage required to produce the reference current for the
device concerned.

VtVd =Vds = VgsI d = I ref |Vd =Vds

(2.4)
Simplicity is the advantage of the constant current definition.
Unlike the maximum g m definition which tends to be sensitive to
noise measurements, there is no need for the derivative
calculations. Furthermore, it can be applied for the both linear and
saturated operation, allowing the comparisons of threshold voltage
at the various bias conditions. However, the appropriate reference
current I ref is technology dependent, that makes it difficult to use
this definition to compare devices from the different manufacturers
or even over multiple technology generations.
The important thing to be noted is that the threshold voltage
is strongly dependent on doping concentration. As we increase the
doping level, the threshold voltage becomes more positive
(negative) for an n-channel (p-channel) devices.
Gate oxide capacitance ( Cox ) : The gate oxide capacitance
per unit area is increased to α Cox due to scaling . The increased
capacitance, and thus the increased inversion charge, allows a
high drive current at reduced operating voltages. The gate
oxide capacitance of each device is reduced by the factor α ,
because the area of each device is reduced by α 2 .
Inversion charge ( Qinv ) : The inversion charge per unit area
remains the same, since the reduced operating voltage and the
increased oxide capacitance cancel each other.
Carrier velocity ( V ) : The carrier velocity is not affected by
the scaling, regardless of whether velocity saturation is
considered or not, since the electric field is constant in this case
and the saturation velocity ( Vsat ) does not change.
Mobility ( µ ): The mobility, to the first order, is not changed
in constant electric field scaling. In practice, however, the
surface mobility will be degraded since the electric field
perpendicular to the Si/SiO2 interface increases, as will be
discussed later.
On-current( I on ): The drive current of a transistor is given by Qinv .
W . V (W is the width of the transistor), and thus I on is reduced by
the factor α , since Qinv and V do not change.
Off-current ( I off ): The off-state leakage current of a transistor,
which is defined as the drain current with the condition Vgs = 0 and
Vds = Vdd , is proportional to the diffusion current W . (dn/dx). Since
the gate length is reduced by the factor α , the charge gradient
along the channel length direction is increased, and thus the
I off per unit width (dn/dx) is increased by the factor α with
scaling. This is a major drawback due to scaling as the leakage
current has to be minimum for improved performance of the
device.
Overlap capacitance ( Coverlap ): Historically, the lithographic
alignment tolerances limit is at about one third of the minimum
feature size. Therefore, the parasitic overlap capacitances of each
device are reduced by the factor α .
Intrinsic delay ( τ ): The intrinsic delay defined as ( C.Vdd )/ I on ,
where C is the intrinsic capacitance resulting from the gate
capacitance and the overlap capacitance, is reduced by the
factor α . However, if the majority of the capacitive load comes
from the interconnects, as in many modern VLSI circuits,
improvements in the intrinsic delay may not directly translate to
faster circuit operation.
Power dissipation (P): The power dissipation per transistor,
which is given by V .I , is reduced by the factor α 2 (assuming I off is
insignificant). Since the power dissipation per transistor is reduced
by the factor α , even with a significantly increased number of
transistors ( α 2 times more transistors) on the same chip area with
scaling, the total power consumption of the chip is not increased.
This allows us to put millions of transistors together in a small
chip area without any additional sink to dissipate the power. Also,
this power consumption issue has been one of the major
differences between bipolar transistor-based circuits and CMOS-
based circuits. Although bipolar devices are faster at an individual
device level, basic physics tells us that faster switching inevitably
entails higher power dissipation. The higher integration density and
the resulting higher functionality of CMOS circuitry allow it to
outperform bipolar circuits, and this trend will continue for the
predictable future.
Finally, since most of the fabrication processes are done at
the wafer level (thin film deposition, oxidation, etch, etc.), the
processing costs of individual chips are lowered with scaling. This
cost factor has been crucial for driving continued scaling.
For RF applications, the following performance metrics that
are affected by scaling are discussed below. They include
Cut-off frequency( fT ): Cut-off frequency is the frequency when
the current gain is unity. It improves with scaling (1/L for short
channel devices)
Maximum frequency of operation ( f max ): For a matched load,
fmax is the frequency at which the power gain is unity and can be
extracted by the Mason’s gain formula. It also improves with
scaling but is limited by strong dependence of gate resistance and
other parasitics.

2.3 Historical Trends

Over the last 30 years of scaling, the basic physical

structure of the MOS transistor has not dramatically changed,
except for a few additions such as the spacers, the Lightly
Doped Drain (LDD) structure, the source/drain extensions (SDEs),
etc., as shown in Fig. 2.4. Although the basic device geometry had
remained relatively unchanged, the gate length LG has been
reduced from 10 µm in the 1970s to less than 0.1 µm in 2001, and
the gate oxide thickness tox from 1000 Å to less than 20 Å. As a
result, performance and the packing density have improved
tremendously, as shown in the example in Figs. 2.5 and 2.6,
confirming the predictions of scaling theory for more than 30 years.

Fig. 2.4: (a) 0.25 µm technology in the early 1990s (b) 0.13 µm
technology node in
2001(c) 70 nm technology node (30 nm physical gate
length) in research [32]
Fig. 2.5: Past trends of transistor scaling: LG and tOX trends. [32]

Fig. 2.6: Past trends in the performance and power of Intel’s

microprocessors [32].

2.3.1 International Technology Roadmap for

Semiconductors

Due to the significant resources and investments

required to develop the next generation of CMOS technologies,
it has been necessary to identify clear goals and put collective
efforts towards developing new equipment and technologies.
The semiconductor roadmap represents a consensus among
industry leaders and gives projected needs based on past
trends. The International Technology Roadmap for
Semiconductors (ITRS) [12] is the standard accepted roadmap.
Fig. 2.7 shows a projection for the thickness of gate
insulators. As shown, the gate insulator needs to be aggressively
scaled down to improve the drive current and to suppress short-
channel effects. Currently, in the 130 nm technology node with a
70 nm physical gate length, the physical thickness of the gate
oxide is only 15 Å, which is approximately 6 atomic layers thick. To
continue the past trends in CMOS scaling, a sub-10 Å effective
oxide thickness will soon be required, which is about 4 atomic
layers thick. Beyond that point, SiO2 may lose its properties as an
insulator and we may need a different materials system, as will be
discussed later. Figure 2.8 shows the supply voltage scaling
scenario. Lower supply voltages are required due to power
dissipation and reliability reasons.
The roadmap distinguishes two different applications: high-
performance and low-power circuits. High-performance applications
include mainstream microprocessors, and low-power applications
include the mobile chips, where the duration of the battery power is
more important than the performance. Figure 2.9 shows the
roadmap specifications for drive current and off-state leakage
current for high performance circuits, along with the associated
supply voltages and the technology nodes. The drive currents of
the nMOSFET/pMOSFET are fixed at constant values of 750/350
µA/µm, while the off-stage leakage current continually
increases with scaling.
Fig. 2.7: 1999 ITRS roadmap for gate insulator thickness [12] As
of the year 2001,
a transistor with a 70 nm physical gate length is
ready for
manufacturing, featuring a 15 Å physical oxide
thickness.

Fig. 2.8: 1999 ITRS roadmap for the supply voltage [25]
Fig. 2.9: 1999 ITRS roadmap for high-performance technologies.
The target IOFF is
plotted versus VDD [12].
In summary, scaling improves cost, speed, and power per
function with every new technology generation. All of these
attributes have been improved by 10 to 100 million times in four
decades --- an engineering achievement unmatched in human
history ! Table 2.2 shows that scaling is expected to continue. Table
2.2: Excerpt of 2003 ITRS technology scaling from 90nm to 22nm.
(HP: High Performance technology, LSTP: Low Standby Power
technology for portable Applications, EOT: Equivalent Oxide
Thickness,)

Table 2.2: Excerpt of 2003 ITRS technology scaling from 90nm to

22nm.
2.4 GATE OXIDE SCALING
Although the principle of the MOSFET was recognized in
the late 1920s, it was not until the 1960s that the device was
successfully realized by Kahng and Atalla [13]. That realization was
critically dependent on the development of a passivation technique
to stabilize the silicon surface using silicon dioxide. The properly
processed Si/SiO2 interface exhibits a degree of perfection that is
not the same with other materials. This system has sustained the
microelectronics industry since 1960. The existence of an ideal
insulator SiO2, in addition to other factors such as silicon’s
mechanical strength and abundance, has given silicon a dominant
status in the IC industry. Ever since the invention of the
transistor and integrated circuits, the gate oxide has been
continually scaled down. A thinner gate oxide gives a higher gate
capacitance so more inversion charge is induced at the same
operating voltage. More inversion charge, in turn, results in a
higher drive current. At the same time, a thinner gate oxide allows
the gate to have better control of the potential in the channel
region via stronger capacitive coupling, suppressing short-channel
effects (SCEs). As devices are shrinking, getting faster and using
less power, the SiO2 gate oxide has been successfully reduced to
15 Å thick, or about 6 atomic layers.
Figure 2.10 shows the scaling scenario of future generation
MOSFETs. Figure 2.11 shows the past trend of the gate oxide
scaling as a function of the gate length in microprocessor
technology. In the DRAM industry, more conservative gate oxides
have been used, since reducing the gate leakage current is of
crucial importance. As shown in Fig. 2.11, the ratio of the gate
length to the gate oxide thickness has not changed very much with
scaling over the last three decades, confirming that gate oxide
scaling has been a main driver of CMOS scaling.
Figure 2.12 shows some of the past roadmap projections
and the actual trend in gate oxide scaling based on Intel’s
microprocessor technologies [14]-[16]. These projections have
become less and less conservative over time due to the
technological advances in the industry. Now, the projection
based on the 1999 ITRS roadmap predicts sub-10 Å equivalent
thickness of the gate insulator in the not too distant future. In the
following sections, we will see how challenging it will be to achieve
such goals and discuss what may be possible solutions.

Fig. 2.10: Scaling scenario of future generation MOSFETs

Fig. 2.11: The past trend of the gate oxide scaling based
on Intel’s
microprocessor technology. A nearly constant
ratio between the Leff
and the tOX has been sustained to improve the
drive current and
maintain control of short-channel effects [24].
Fig. 2.12: Roadmaps for gate oxide scaling and the actual trend
obtained from
Intel’s microprocessor technology [12].

2.4.1 Ultra-thin gate oxides-feasibility and

limitations

Gate oxide scaling is not limited by manufacturing control. It

is feasible to manufacture sub-15Å SiO2 layers on 8-inch wafers
with current technology. Historical concerns that such thin
oxides would exhibit pinholes or other defects somewhere in a
chip have proven unfounded. Instead, the real challenge comes
from gate leakage current through the thin oxide. Figure 2.13
shows the band-diagram of the Si/SiO2 system. The conduction
band offset between Si and SiO2 is 3.2 eV and the valence band
offset is 3.7 eV, and holes have a much lower tunneling probability
in oxide than electrons. As a result, the leakage current limit will be
reached first for n-type MOSFETs [14]-[17].
Reduction of gate oxide thickness results in an increase in
the field across the oxide. The high electric field coupled with the
low oxide thickness results in tunneling of electrons from the
substrate to the gate and also from the gate to the substrate
through the gate oxide, resulting in the gate oxide tunneling
current. To understand the phenomenon of tunneling, let us
consider an MOS capacitor with a heavily doped n+-type polysilicon
gate and a p-type substrate. Also, for simplicity, let us now focus
only on the electron tunneling. When a positive bias is applied to
the gate, the energy band diagram is shown in fig. 2.14(a).

Fig. 2.13: Band diagram to explain gate tunneling current. The

barrier height seen by the conduction electrons is 3.2 eV while it
is 3.7 eV for the holes.

(a) (b)

Fig. 2.14: Tunneling of electrons through an MOS capacitor.

(a) Energy-band
diagram with positive gate bias showing tunneling
of electron from
substrate to gate. (b) Energy-band diagram at
negative gate bias
showing tunneling of electron from gate to
substrate

Due to the small oxide thickness, which results in a small

width of the potential barrier, the electrons at the strongly inverted
surface can tunnel into or through the SiO2 layer and hence give
rise to the gate current. On the other hand, if a negative gate bias
is applied, electrons from the n+ polysilicon can tunnel into or
through the oxide layer and give rise to the gate current [see Fig.
2.14(b)].
The mechanism of tunneling between substrate and gate
polysilicon can be primarily divided into two parts, namely: (1)
Fowler–Nordheim (F-N) tunneling; and (2) Direct tunneling. In
the case of F-N tunneling, electrons tunnel through a triangular
potential barrier, whereas in the case of direct tunneling, electrons
tunnel through a trapezoidal potential barrier. The tunneling
probability of an electron depends on the thickness of the barrier,
the barrier height, and the structure of the barrier. Therefore, the
tunneling probabilities of a single electron in F-N tunneling and
direct tunneling are different, resulting in different tunneling
currents.
1) Fowler–Nordheim Tunneling: In F-N tunneling, electrons
tunnel into the conduction band of the oxide layer. Fig. 2.15 shows
the F-N tunneling of electrons from the inverted surface to the
gate. Ignoring the effect of finite temperature and image-force-
induced barrier lowering, the current density in the FN tunneling is
given by [15]
q 3E ox
2
4 2m* φ 3/ 2
J FN = −
exp( ox
) (2.5)
16π 2 hφ ox 3 h Eox
where Eox is the field is across the oxide, φox is the barrier height for
electrons in the conduction band and m* is the effective mass of an
electron in the conduction band of silicon. The F-N current equation
represents the tunneling through the triangular potential barrier
and is valid for Vox > φox , where Vox is the voltage drop across the
oxide. The measured value of F-N tunneling current is very small;
for example, at an oxide field of 8 MV/cm, the F-N tunneling current
density is about 5*10-7A/cm. Since φox =3.1eV, short-channel
devices mostly operate at Vox < φox . Thus, for normal device
operation, the F-N tunneling current is negligible.
 Fig. 2.15: Fowler–Nordheim Tunneling Phenomena

2) Direct Tunneling : In very thin oxide layers (less than 3–4 nm),
electrons from the inverted silicon surface, instead of tunneling into
the conduction band of SiO2 , directly tunnel to the gate through
the forbidden energy gap of the SiO2 layer. The direct tunneling
phenomenon is explained in Fig. 2.16. In the case of direct
tunneling, electrons tunnel through a trapezoidal potential barrier
instead of a triangular potential barrier. Hence, the direct tunneling
occurs at Vox < φox [15]. The equation governing the current density
of the direct tunneling is given by [18]
Vox 3/ 2
B[1 − (1 − ) ]
φox (2.6)
J DT = AEox2 exp{− }
Eox
where A =q 3/16 π hφ
2
and B = 4 2m *φox3/ 2 / 3 hq . Direct tunneling
ox

current is significant for low oxide thicknesses.

 Fig. 2.16: Direct Tunneling Phenomena

 GIDL : Gate Induced Drain Leakage

Another type of current leakage that should be considered as

the gate oxide thickness is decreased is GIDL (Gate Induced Drain
Leakage). When the gate is in the off state and the drain voltage is
positive for an n-channel MOSFET, the electric field from the drain
to the gate can cause the overlap region to form a depletion region
(see Fig. 2.17).
If the electric field is high enough, the depletion region near
the surface may invert to p-type. When the minority carriers are
drawn to create the inversion layer, they are swept into the p-well
[26]. Electrons from the valence band can tunnel into the drain
region under the overlap. The holes left in the valence band drift to
the p-well. GIDL does not increase because of scaling the gate
length, but does increase when the oxide thickness is reduced,
since the electric field increases. One way to decrease GIDL is to by
decreasing Vds. GIDL is independent of temperature. To detect
GIDL, the lack of temperature dependence is a solution, since the
electrical measurements of leakage can be performed at different
temperatures.
 Fig. 2.17: Schematic diagram illustrating GIDL.

2.4.2 Limitations
Although it is becoming progressively more difficult to scale
down the gate oxide thickness, the performance of the device
detoriates[14]. The first reason is the finite distance of the
inversion layer from the Si/SiO 2 interface due to quantum
mechanical confinement. The inversion charge centroid is ~1 nm
away from the Si/SiO2 interface, and this increases the electrical
thickness of the gate oxide. Usually, the quantum mechanical
effect adds 4-8 Å to the physical oxide thickness. As a result, to
reduce the electrical thickness of a 20 Å physical gate oxide (24-28
Å electrical) by half, we need a 12-14 Å electrical thickness or 6-8 Å
equivalent physical thickness of SiO2, which will be extremely
challenging.
Another problem comes from the subsequent increasing of
the electric field in the transistor. Although ideal scaling theory
was based on a constant electric field, in practice, the electric
field continually increases. The main reason for this discrepancy
lies in the non-scaling nature of the threshold voltage. The
subthreshold slope of the MOSFET at room temperature cannot be
made better than 60 mV/decade due to Boltzmann’s statistics. As
a result, if the threshold voltage is reduced, the off-state
leakage current will exponentially increase. On the other hand,
the circuit delay is mainly determined by the gate overdrive ( VDD -
Vt ), and thus scaling down VDD while keeping the same Vt
will severely degrade the switching speed. Since Vt cannot be
easily scaled due to fundamental physical limits (Boltzmann
statistics), we cannot simply scale down VDD . As a result, the
supply voltage has not scaled down as fast as geometries of
the device and thus the perpendicular electric field has
steadily increased. Fig 2.18 shows the trends in the voltage
scaling along with the trend in gate oxide scaling.
The gate oxide thickness has been scaled down faster than
the supply voltage, giving rise to the increased electric field. An
increased surface electric field can severely degrade the carrier
mobility and consequently reduce the drive current. Fig. 2.19 (a)
shows the universal mobility curve, which plots the surface mobility
as a function of the effective electric field [32]. The x-axis
represents the effective vertical electric field and the y-axis
represents the surface mobility. In the low field regime as in Fig.
2.19 (b), Coulomb scattering is the dominant scattering
mechanism. However, if the surface vertical electric field
approaches about 1 MV/cm, the mobility rapidly drops due to
increased surface scattering. Note that this effect also applies to
high-k gate dielectrics to be discussed later. Perhaps the roughness
scattering will be even more devastating in that case, since the
interface quality of the high-k material systems may not match that
of the Si/SiO2 interface.
Fig. 2.18: Scaling trends for the supply voltage and the gate
oxide thickness.
Due to the non-scaling nature of the threshold voltage,
the electric field
across the gate oxide has steadily increased ([24])

(a)
(b)
Fig. 2.19: The universal mobility curve and the explanation of
different regime (After
Takagi et al. [32])

2.5 GATE LENGTH SCALING

The gate length has been one of the most important
parameters directly related to CMOS scaling. Smaller gate
lengths, driven by an advanced lithographic capability, allow
higher drive current and, consequently, faster circuits, assuming
that the parasitic capacitances are scaled down simultaneously
allowing operation at lower voltages. At the same time, higher
packing density is also achieved, due to the ability to pattern finer
structures. Traditionally, more demands for gate length scaling
have come from the DRAM industry, where the cost (reduced
by the packing density) has been crucial. Logic circuits have
benefited from these advances in lithography. Figure 2.20 shows
the historical trends in the gate length scaling and the future
projections [12].
 Fig. 2.20: Transistor Gate Length Trend ([25])

2.5.1 Ballistic Transistors

As the gate length approaches 10 nm, one interesting
phenomena that occurs is ballistic transport. The mean free path
of electrons in silicon is about 10 nm. If the gate length of a
transistor becomes shorter than the mean free path, the
majority of the electrons will not be scattered in the channel. Such
a device is called a ballistic transistor.
The current in a ballistic transistor is determined by
transmission and reflection coefficients. These coefficients are
influenced by factors such as surface roughness and channel
potential. An interesting observation is that in the ballistic
regime, reducing the gate length may no longer improve I on since
the drive current is fixed by the thermal velocity of the electrons
in the source region. Such an example illustrates the difficulty
of continually improving the transistor performance based on
conventional scaling of the feature sizes.

2.6 EFFECTS OF DEVICE SCALING-SHORT

CHANNEL EFFECTS
Device design in the deep sub-micron regime is a challenging task.
The basic, first-order theories do not fully describe the device
behavior. Second-order effects, such as threshold variations with
 channel length due to the charge sharing and the doping effects,
extrinsic resistances, and quantum mechanical effects, must be
taken into account. These second order effects combine to make it
difficult for the device designers to have an intuitive grasp of all the
trade-offs inherent in the device design, complicating the design
process..
A MOSFET device is considered to be short when the channel
length is the same order of magnitude as the depletion-layer
widths ( X dd , X ds ) of the source and drain junction. As the channel
length LG is reduced to increase both the operation speed and the
number of components per chip, the so-called short-channel effects
arise.
The short-channel effects are attributed to two physical
phenomena:
1. The limitation imposed on electron drift characteristics in the
channel.
2. The modification of the threshold voltage due to the shortening
of channel length.
In particular five major short-channel effects can be distinguished:

• THRESHOLD VOLTAGE ROLL-OFF

A clear indicator of short channel effects is the decrease in
the threshold voltage Vt with decreasing channel length. [18], [19].
Plotting Leff on the x-axis and threshold voltage on the y-axis
makes a Vt roll-off chart. The minimum Leff that will be acceptable
is indicated in the chart. Vt roll-off is one of the most serious
consequences of short channel effects. Fig. 2.21 below
demonstrates Vt roll-off for n- and p-channel MOSFETs.
The threshold voltage ( Vt ) of MOSFETs cannot continue to be
scaled down as the gate length is decreased. The subthreshold
current I off increases as Vt is decreased. An increase in I off is a
serious threat to the continued performance enhancements of the
MOSFET transistor. For transistors less than 0.25 μm designers
must consider the trade off between the speed and the power
consumption.
 Fig. 2.21: Vt versus Leff demonstrating (Vt roll-off) [15].

As the gate length is reduced below 2 μm, the long channel

approximation for the threshold voltage is not as accurate. The Vt
generally decreases as gate length is decreased. Also, the Vt
decreases as the drain-source voltage ( Vds ) is increased. In order to
predict the Vt of a short channel device, the shift in the threshold
voltage, Δ Vt , must be approximated [17]. The short channel effect
(SCE) Vt is given by the following formula where Vto is the long
channel Vt [20]:

( Vto )SCE = Vto − (Δ Vt ) (2.7)

 Fig. 2.22: Charge sharing model for explaining short channel
effects (Yau [18])

Through a charge sharing argument (Fig. 2.22), this

phenomenon can be explained. Unlike the long channel device, in a
short channel device, a significant portion of the field lines
emanating from the bulk charge terminate in the source and drain
regions instead of at the gate. As a result, it is easier for the gate to
deplete the lower amount of channel charge, lowering the
threshold voltage of the device. Using the model given by Yau [21],
for NMOS device the analytical formula mentioned below to
calculate Δ Vt can be used for uniformly doped channels
2d max
qN SUB d. r. ( {1 +
max j } −1)
rj (2.8)
∆Vt=
Cox .L
where d max is the maximum width of the depletion region under the
gate, and rj is the length of the depletion region of the source/drain.
The above mentioned model shows that decreasing the gate oxide
thickness ( Cox = εox t ox
/ ) and decreasing the depletion regions of
the source/drain will decrease Δ Vt . The model works well and helps
to understand the concept of decreasing Δ Vt , but does not predict
the change in the Vt accurately against experiment data, especially
for narrow gate lengths and high Vds . The above model does
provide a first order approximation [20].
• DRAIN INDUCED BARRIER LOWERING (DIBL)

The threshold voltage is a measure of the strength of the

barrier against carrier injection from source to channel. In the
short-channel regime, this barrier may be significantly modified by
the application of a drain bias, as was schematically depicted in
Fig. 2.23 and Fig. 2.24. In any n-channel FETs, this drain-induced
barrier lowering (DIBL) translates into a lowering of the threshold
voltage (n-channel MOSFET) and a concomitant rise in the
subthreshold current with increasing Vds . The combined scaling and
DIBL effect on the threshold voltage may be expressed as follows:
Vt ( LG ) = Vto ( LG ) − σ ( LG ) Vds (2.9)
where Vto ( LG ) describes the scaling of Vt at zero drain bias
resulting from charge sharing and σ( LG ) is the channel-length-
dependent DIBL parameter. In the long-channel case, where LG
>Lmin, Vt should become independent of LG and Vds . This behavior
can be modeled by letting both Vto ( LG ) and σ ( LG ) scale
approximately as exp (− LG /Lmin). In BSIM, detailed scaling
functions alongwith dependence on substrate bias are used. In
Figure 2.21, we show experimental data of Vt versus VDD for two n-
channel MOSFETs with short gate lengths. A good agreement with
the linear relationship of (2.5) is indicated. As stated above, DIBL
vanishes well above threshold. For modeling purposes, we
therefore adopt the following empirical expression for σ
σ0
σ=
V −V (2.10)
1 + exp( gt 0 σ t )
Vσ
where Vgto is the gate voltage overdrive at zero drain-source bias
and the parameters Vot and Vo determine the voltage and the width
of the DIBL fade-out, respectively. We note that σ → σ o for Vgto < Vot
and σ → 0 for Vgto > Vot . As per the concept, the lowering of the drain
barrier is caused by the lowering of the potential barrier at the
source of a MOSFET due to applied drain bias (Fig. 2.22). The
important point is that, like threshold voltage roll-off, DIBL effects
increase with increasing the junction depth of the source/drain
region. A measure of the severity of DIBL can be defined as follows
Vt ,lin −Vt ,sat
DIBL = (2.11)
VDD −Vdlin
where VDD is the supply voltage, Vdlin is the linear drain voltage, and
Vt ,lin and Vt , sat are the threshold voltages in the linear and the
saturated operations respectively.

Figure 2.23: DIBL effect: (a) experimental threshold voltage shift

versus drain-
source voltage for two n-MOSFETs with different
gate lengths
(Reproduced from Fjeldly T. A. and Shur M. (1993))
 Fig. 2.24: The energy band diagram at the source end of a half
NMOS device with
and without an applied drain bias.

• PUNCH THROUGH

Punch through occurs when the depletion regions of the

source and drain merge with each other. When the depletion
regions intersect, as shown in Fig. 2.25, the space-charge limited
current flows between the drain and source. By the gate bias, this
current cannot be controlled [18]. It depends on the drain bias and
also the substrate doping. Decreasing the drain bias will decrease
the depletion region. For channel lengths below 0.1 μm, the
substrate requires a doping level of 1×1018 − 5 ×1018 cm −3 to prevent the
punch through. An increase in the tunneling current between the
source and the drain p-n junctions with the substrate [23] is caused
by this high doping.

Fig. 2.25: Schematic diagram for punch through.

• HOT CARRIER DEGRADATION

The “Lucky Electron” model [24] describes the mechanism of

hot carrier degradation in an n-channel MOSFET (Fig. 2.26).
Electrons are injected into the drain-substrate depletion region,
when a device is operated in saturation mode. Some electrons
acquire enough energy to cause impact ionization (i.e., electron-
hole pair generation), as the electric field is quite high in this region
and are referred to as hot electrons [25]. The maximum electric
field is located between the pitch-off point and the drain-substrate
metallurgical junction. Electrons generated in the drain-substrate
depletion region may be redirected (i.e., momentum changed)
toward the gate oxide. At the same time, holes generated in the
drain-substrate depletion region will give rise to a substrate
current, I sx , as illustrated in Fig. 2.26. (The monitoring of I sx has
proved invaluable as a means of modeling hot carrier effects. A
higher value of I sx corresponds to a higher impact ionization rate.)
If hot electrons with energy > 3.2 eV overcome the potential
barrier between Si and SiO2, they may be trapped in the oxide and
give rise to a gate current. It is also possible for hot electrons with
energy > 3.7 eV to generate interface traps, or surface states, at
the Si-SiO2 interface [24].

Fig. 2.26: The mechanism of hot carrier degradation in an n-

channel MOSFET.

Interface state generation and fixed charge formation results

in hot carrier degradation in n-channel MOSFETS. This damage
produces shifts in 1) threshold voltage, 2) mobility, 3) subthreshold
current swing, and 4) transconductance [18]. In the case of 1), the
threshold voltage increases with time while the device is operated
in saturation mode, which results in a lower on current ( I on ). The
mobility decreases with time in the case of 2), which also results in
a lower I on . Based on the model proposed by Hu, et al. [32], the
threshold voltage increases because the generation of interface
traps reduces carrier density and mobility at the drain side of the
channel. When I sx is a maximum, the worst case device
degradation is observed. Both the threshold voltage and the
transconductance shifts are proportional to the average trap
density, which in turn is inversely proportional to Leff . Therefore,
reducing the channel length will produce a lower hot carrier
lifetime. (The hot carrier lifetime is defined as the time required
causing a certain threshold voltage shift or a corresponding
decrease in I on .) A lower lifetime is produced by increasing the
drain source voltage, since the electric field in the drain-substrate
depletion region is higher.

Fig. 2.27: The mechanism of hot carrier degradation in a p-

channel MOSFET.

Since the energy barrier between the Si and SiO2 is lower for
electron injection (3.2 eV) than for hole injection (4.7 eV), hot
carrier degradation is more severe for n-channel MOSFETs than for
p-channel MOSFETs [26]. Nevertheless, hot carrier degradation in
submicron p-channel MOSFETs can be a serious concern [27]. When
the device is operated in saturation mode, holes are injected into
the drain-substrate depletion region (see Fig. 2.27). Enough energy
is acquired by some holes to cause impact ionization and they are
referred to as hot holes. Electrons generated in the drain-substrate
depletion region may be redirected toward and trapped in the
oxide. If the density of trapped electrons is sufficiently high, the
excess negative oxide charge will attract holes to the Si-SiO2
interface and cause an extension of the drain into the n-well region
which results in a reduction in Leff and a decrease in the absolute
value of the threshold voltage, | Vt |. This can be a serious problem
for short channel devices, especially those that are sensitive to
subtle changes in Leff due to DIBL. When the gate current, I g , is
maximum, the worst case device degradation occurs. For | Vg |<| Vds |,
the electron trapping mechanism is dominant, while a hole injection
mechanism is dominant for | Vg |>| Vds |. Hole injection has the
opposite effect, as the electron trapping by producing an increase
in | Vt |.
It is possible for one channel electron to collide with another
channel electron of the same energy, in the case of electron–
electron interactions. One of the electrons may lose its energy to
the other electron, giving this electron two times the energy of the
drain-source supply energy [28]. It has been predicted by
simulation techniques that the high energy tail of the electron
energy distribution will be dominated by electron-electron
scattering for drain voltages < 3 V [29]. In one study [28], the
electron energy distribution was determined by solving the one-
dimensional spatially dependent Boltzmann transport equation that
includes electron-electron interactions. It was found that for a long
(0.25 μm) channel length device and a drain voltage of 1.5 V, the
high energy tail (i.e., low probability tail) of the electron energy
distribution was only slightly increased when electron-electron
interactions were included. Contrary to this, for a short (0.07μm)
channel length device and a drain voltage of 1.5 V, the high energy
tail of the electron energy distribution was greatly increased when
electron-electron interactions were considered. This implies that
the hot electron population is expected to increase significantly for
very short channel devices due to electron-electron interactions.
Recently, Rauch, et al. [29], have shown experimentally that
electron-electron scattering must be considered in order to
accurately model hot carrier degradation for effective channel
lengths in the range 0.07-0.10 μm.

Fig. 2.28: Impact ionization feedback process in an n-channel

MOSFET

In the case of secondary impact ionization, a feedback

process occurs in which secondary electrons (holes) contribute to a
gate current [28]. Fig. 2.28 illustrates the impact ionization
feedback process for an n-channel MOSFET. Channel electrons, e1,
create electron-hole pairs, e2 and h2, through impact ionization in
the drain-substrate depletion region. The secondary electrons, e2,
are swept into drain while the secondary holes, h2, are swept into
the substrate [30]. Through impact ionization these secondary
holes create more electron-hole pairs, e3 and h3. The h3 holes
contribute to the substrate current, while the e3 electrons are swept
back into the drain-substrate depletion region.
Large vertical fields in this region can give the e3 electrons
enough energy to surmount the Si-SiO2 barrier (3.2 eV) and thereby
contribute to a gate current [30]. The e3 electrons also lead to
additional impact ionization. For relatively long channel-length
devices operated at high Vds , the electron energy distribution is not
affected by secondary impact ionization because of weaker vertical
fields in the drain-substrate depletion region. Thus, for long
devices, the gate current will be controlled by the e1 channel
electrons. But for relatively short channel-length devices operated
at low Vds , the high energy tail of the electron energy distribution is
 significantly affected by secondary impact ionization because of
stronger vertical fields in the drain-substrate depletion region.
Therefore, the gate current is controlled by the e3 electrons, for
short devices.

• VELOCITY SATURATION
The linear velocity-field relationship (constant mobility) works
reasonably well for the long-channel devices. However, the implicit
notion of a diverging carrier velocity as we approach pinch-off is, of
course, unphysical. Instead, current saturation is better described
in terms of a saturation of the carrier drift velocity when the
electric field near the drain becomes sufficiently high. The following
two-piece model is a simple, first approximation to a realistic
velocity-field relationship:

v( F ) = µn F for F < Fs

= vs for F ≥ Fs (2.12)
where F =|dV(x)/dx| is the magnitude of lateral electrical field in
the channel, vs is the saturation velocity, and Fs = vs /µn is the
saturation field. In this description, current saturation in FETs
occurs when the field at the drain side of the gate reaches the
saturation field. A somewhat more precise expression, which is
particularly useful for n-channel MOSFETs, is the so-called Sodini
model (Sodini et al. 1984),
µn F
v( F ) = for F < Fs
1 + F / 2 Fs
= vs for F ≥ Fs (2.13)
 Fig. 2.29: Velocity-field relationships for charge carriers in
silicon MOSFETs. The electric field and the velocity are
normalized to Fs and vs, respectively.
Even more realistic velocity-field relationships for MOSFETs are
obtained from
µF
v( F ) = (2.14)
(1 + ( F / Fs ) m )1/ m
where m = 2 and m = 1 are reasonable choices for n-channel and
p-channel MOSFETs, respectively. The two-piece model in (2.8)
corresponds to m =∞ in (2.10). Figure 2.29 shows different velocity
field models for electrons and holes in silicon MOSFETs.
Reverse Short Channel Effects-Width scaling

We have focused on how the threshold voltage decreased as

the gate length decreased, in the previous section. It also discussed
how width scaling could sometimes have a reverse effect on the
threshold voltage. When the threshold voltage increases with
scaling this is referred as Vt rollup. The two effects, Vt roll-up and Vt
roll-off, compete with one another until Vt roll-off becomes the
dominate effect as scaling increases.
One explanation for reverse short channel behavior is
presented by Rafferty, et al [5]. The source/drain implants
introduce a retrograde profile of point defects at the edge of the
channel. In turn it leads to pile up of boron impurity atoms at the
surface, increasing the channel doping close to the source/drain
region (Fig. 2.30). While the impact of this increase in doping is
small for long channel devices, for short channel devices the region
with the increased doping is a significant part of the channel. The
resultant increase in the effective channel doping with shortening
channel length causes the threshold voltage to increase with
scaling, until eventually short channel effects take over. This
explains the roll-up in the threshold voltage.

Fig. 2.30: Schematic diagram showing a non-uniform lateral

doping distribution
that can be used to explain the reverse short channel
effects (a) Schematic
of the device (b) Doping profile along the line AA’

A physical model of the lateral doping distribution responsible

for reverse short channel effects can be found in Hanafi, et al [20].

Mobility Degradation

Mobility is a measure of the ease with which an electron or

hole can move in a semiconductor. Mobility is determined by
impurity and lattice scattering in the Si [32] for long channel
devices. For the short channel devices, the mobility in the channel
will be less. One reason for the decrease in mobility is because of
the effect discussed in section 2.3.2 velocity saturation, which
occurs as a result of the electric field perpendicular to the gate, E y .
The other electric field to be considered is the one perpendicular to
the channel, Ex . This electric field component causes scattering of
the electrons near the Si surface. The electrons slow down by the
increase in scattering, thereby decreasing the mobility with respect
to the bulk [32]. Ex attracts the electrons to the interface between
the Si and SiO2, and since the interface is not smooth, it will cause
more electron scattering [31]. For an increase in substrate doping,
the mobility will also decrease.

2.7 Interconnects

Interconnects can be scaled using the constant electric field

scaling. By the constant K, the width, the length, the insulator
thickness, and the spacing between the lines can all be scaled. The
material properties are assumed to remain constant, such as the
resistivity of the metal and the dielectric constant for the insulator.
If these assumptions are correct, the capacitance of the wire per
unit length will remain the same. On the other hand, the wire
resistance does not decrease, but increases by K. The resistance
per unit length ( Rw ) increases by K2. Therefore the RC time
constant increases by K2. The RC time delay ( τ ω ) formula is given
by
1 l
τω = Rw ( K 2 )Cw ( ) 2 (2.15)
2 K
The RC delay remains constant since the K terms cancel. For
aluminum (Al) this does not pose a problem since the RC delay
becomes [24]
−18 l2
τω ≈ 3*10 (2.16)
A
which equals 1ps of delay or less. This number is much smaller
than the intrinsic delay for 0.1 μm CMOS technology, which is
approximately 20 ps [12, 31]. Also worth mentioning is that the
current density increases by K ((see Table 2.II)), forcing the long
term reliability issues such as electro-migration.
The above discussion is for local wires. The delay time for
global wires will cause problems, while the RC delay time for local
wires will not. Global wires are on the order of the chip size. They
are not scaled down by K. The chip size usually does not decrease,
but will more likely increase slightly as more and more transistors
are added with each iteration of more powerful chips. The RC delay
time will increase by K2 for global wires, since the chip size is
basically the same. If the global wires decrease by K for each
shrink, then it leads to a problem .Using constant scaling for the
local wires and not to scale or scale-up the global wires is a solution
for this problem. Eventually the scale-up approach will have
problems as it approaches the limits when the inductive effect
outweighs the resistive effect. When this happens, the signal rise
time is shorter than the time it takes the signal to travel to the end
point [32]. To replace Al with a lower resistivity material, such as
copper (Cu) is an alternative solution.
Trade-off between the Performance and the Reliability
The main objectives of MOSFET scaling are to
 provide a roadmap for the design
 require the actual design to focus on optimization of the
short channel effects
For digital applications, it is critical that the device threshold
voltage is large enough (>0.4 V) in order to reduce I off and the
noise sensitivity. While scaling certainly improves the performance
by producing a larger I on and increasing the switching speed,
scaling also introduces the short channel effects in the submicron
devices that adversely effect the device performance and the long
term reliability.
Device designs that improve circuit performance may be
detrimental to the MOSFET reliability, and vice versa. For instance,
reducing the depth of the source and the drain regions leads to less
threshold voltage reduction due to DIBL and less junction
capacitance. But at the same time, shallower junctions are more
abrupt and result in larger electric fields in the drain-substrate
depletion region. These larger fields may cause more oxide
damage than expected due to new hot carrier effects, such as the
secondary impact ionization [27]. Likewise, although reducing the
oxide thickness improves the performance since I on α Cox , thinner
oxides are more susceptible to the catastrophic breakdown, direct
tunneling currents and the Stress-Induced Leakage Currents (SILCs)
[30, 33, and 34]. Conversely, while the LDD structure described
above reduces the hot carrier effects and allows shorter devices to
be operated at higher voltages, the n- regions increase the series
resistance and thus lead to a lower I on [27, 32].

2.8Device Engineering to Control Short

Channel Effects

As Silicon MOSFET technologies approach the 0.1µm regime, the

short channel effects such as the DIBL, shifts in Vt , the punch
through and the mobility degradation are more likely to hinder the
device performance [35]. Punch through; for example, is controlled
in conventional MOSFETs by using a higher substrate (channel)
doping as the channel length is reduced. But this approach has
limitations since higher substrate (channel) doping decreases the
channel mobility and results in lower Vt control [35]. In order to
reduce the channel length and at the same time maintain an
acceptable threshold voltage, the channel mobility and the
punchthrough control, state-of-the-art MOSFET technologies
implement source/drain-engineered, the channel-engineered and
the gate-engineered devices (see Fig.2.31). In this section, we
discuss the device characteristics and hot carrier reliability of these
engineered structures.

Fig. 2.31: Schematic diagram illustrating various aspects of

Device Engineering
2.8.1 Source/Drain Engineering

By using the source drain extensions (SDE), we can reduce short

channel effects. An example of source drain extensions is the LDD
structure mentioned in section 2.4.1. SDE can be formed by first
etching the gate followed by ion implantation forming the SDE. A
spacer will be attached to the gate after the SDE implant. The
spacer’s purpose is to block the higher dose source/drain (S/D)
implants. The SDE should be relatively shallow compared to the S/D
implants. The deeper the SDE, the more will be short channel
effects. But on the other hand, the shallower the SDE, the higher
will be the external resistance. The external resistance can be
divided into five resistors in series.
The current in the channel flows first through the channel
(accumulation region) next to SDE (spreading resistance) then
through the deep source implant (shunt resistance) and finally
through contact resistance. The main components of the external
resistance are the RACCUMULATION and the RSPREADING resistance which are
shown in Fig.2.32.
The channel length becomes smaller and the SDE depth
becomes narrower when the transistors are scaled. The channel
resistance decreases but the SDE resistance increases. Scaling of
the depth is limited. It is proposed by Intel that SDE depths below
30-40 nm will have little to no benefit for devices with gate lengths
less than 0.1 um. The reason for this is that any gain in short
channel effect because of reduced charge sharing will be balanced
out because of the increase in external resistance. Also if the SDE
depth is very narrow it will not extend far enough under the gate.
The SDE must extend under the gate to increase drive current. If
the SDE does not extend enough under the gate the current will
spread out more in the lower doped part of the SDE. This will cause
an increase in the RACCUMULATION and RSPREADING resistance. The increase
in the overall external resistance will decrease the maximum drive
current [36].
 Fig. 2.32: Components of external resistance [46]

The SDE is created using an ion implantation as described

earlier. Ion implantation can cause implant channeling and also
cause transient enhanced diffusion. Both of these effects can cause
the SDE to be deeper than intended, which will increase the short
channel effects. The effect can be controlled decreasing the
implant energy, but is unlikely for p-channel MOSFETs using boron
as the implant.

2.8.2 Channel Engineering

Fig. 2.33: Graphical representation of different aspects of Well

Engineering [42].
Besides the gate oxide thickness and junction scaling,
another technique to improve short-channel characteristics is the
well engineering. The distribution of the electric field and potential
contours can be changed by changing the doping profile in the
channel region. The goal is to optimize the channel profile to
minimize the OFF-state leakage while maximizing the linear and
saturated drive currents. Super steep retrograde wells and halo
implants have been used as a means to scale the channel length
and increase the transistor drive current without causing an
increase in the OFF-state leakage current [39]–[42].
Fig. 2.33 is a schematic representation of the transistor
regions that are affected by the different types of well engineering
[30]. Retrograde well engineering changes the 1-D characteristics
of the well profile by creating a retrograde profile toward the Si–
SiO2 surface. The halo profile creates a localized 2-D dopant
distribution near the S/D extension regions. These two techniques
are used to increase the device performance, while keeping
leakage to a tolerable limit.

2.8.2.1. Vertical Substrate Engineering - Retrograde

Channel Profiles

Conventional channels formed by implanting dopants into the

substrate and diffusing them (at high temperature) to a certain
depth, can be quite susceptible to short channel effects such as
punch through, mobility degradation and latch-up. To maintain
acceptable SCE with continually decreasing channel lengths, both
the oxide thickness and the gate-controlled depletion width in
silicon

4εsiΨB
Wdm =
qN a
(2.17)
must be reduced in proportion to the channel length (L) to offset
the degradation in SCEs for extremely small devices. This requires
an increase in the channel-doping concentration (Na). This leads to
a higher threshold voltage for a uniformly doped channel,
according to the following:

4εsi qNΨ
a B
Vth =V fb+ Ψ
2 B+
Cox
(2.18)
However, if the threshold voltage is not scaled, the device
performance for low supply voltages will degrade due to the large
reduction in gate drive. Retrograde doping can be used to reduce
the gate-controlled depletion width while fulfilling the Vth reduction
trend. This design is achieved by using high energy ion
implantation to place dopants at a desired substrate depth and
then annealing at a low temperature to activate the implants. An
important feature of retrograde structures is the use of slow
diffusing dopants such as arsenic or antimony for p-channel
devices and indium for n-channel devices [36].

Fig. 2.34: Comparison of conventional and retrograde p-well

profiles.

Fig. 2.34 illustrates the doping profiles (simulated) in the

conventional and the retrograde implanted p-well structures. As
shown in the figure, the doping concentration for the conventional
well is highest at the silicon surface and decreases as one moves
further into the p-well. On the other hand, the peak of the
retrograde doping profile is highest at a certain depth within the
silicon substrate and decreases as one approach its surface. The
slope of the doping profile between the location of peak
concentration and the silicon surface can be quite high, as is the
case for super steep retrograde (SSR) channel profiles. Some
advantages of the retrograde over the conventional channel
engineering are noted as follows:
 1. Increased packing density since high energy ion implantation
results in less lateral diffusion of the implanted dopants [32].
2. Higher surface mobility (i.e., less impurity scattering in the
channel region near the Si/SiO2 interface) due to a lower
surface concentration of dopants [43].
3. Better control of Vt due to lower surface doping [43].
4. Reduction in DIBL because the drain depletion width extends
less into the retrograde well, resulting in shorter minimum
channel lengths for the same Ioff leakage current.
5. Better control of punch through since the doping
concentration at the bottom of the well is higher [32].
6. Increased protection against the latch up because the
conductivity in the bottom of the well is increased [32].
7. For a given tox, reduction in Wdm improves SCE, but increases
substrate sensitivity and the Subthreshold Slope [44].
8. Due to peculiar doping profile, these devices also have shown
higher body bias sensitivity, source/drain-to-body
capacitances and lower flicker noise levels compared to a
uniformly doped channel device.

2.8.2.2. Lateral Channel Engineering - Halo Implants

Halo doping or non-uniform channel profile in a lateral direction

was introduced below 0.25-µm technology node to provide another
way to control the dependence of the threshold voltage on the
channel length. Halo implants increase the doping near the source
and the drain implant. For n-channel MOSFETs, more highly p-type
doped regions are introduced near the two ends of the channel as
shown in Fig. 2.35. The implants near the source or drain can be
symmetrical or asymmetrical. The halo implants can be vertical or
can have a tilt. They are usually added after the gate pattern is
completed. The implants add more of a barrier between the source
drain junctions with the channel.
 (a) (b)
Fig. 2.35: A Schematic view of halo doped MOSFETs (a) Left:
Symmetric Halo (b)
Right: Asymmetric Halo i.e. heavy doping only on the source
side

During sidewall oxidation, point defects are injected under the

edges of the gate, in the vicinity of what will eventually become the
end of the channel. Doping impurities from the substrate are
gathered by this point defects, thereby increasing the doping
concentration near the source and drain end of the channel. More
highly doped p-type substrate near the edges of the channel
reduces the charge-sharing effects from the source and drain
fields, thus reducing the width of the depletion region in the drain-
substrate and source-substrate regions. These highly doped regions
consume a larger fraction of the total channel as the channel
length is reduced. Reduction of charge-sharing effects reduces the
threshold voltage degradation due to channel length reduction.
Thus, threshold voltage dependence on channel length becomes
more flat as shown in Fig. 2.36. Hence, the off-current becomes
less sensitive to channel length variation. The barrier lowering in
the channel is also reduced by the reduction in drain and source
junction depletion region width, thus reducing DIBL. Since the
channel edges are more heavily doped and junction depletion
widths are smaller, the distance between source and drain
depletion regions is larger. This reduces the punch through
possibility. The higher doping near the channel edges causes larger
Band To Band Tunneling (BTBT) and higher GIDL. The halo doping
level [45] is ultimately limited by the BTBT currents in the high-field
region near the drain.

Fig.
2.36:
Short-

channel threshold-voltage rolloff for retrograde and

superhalo (vertical and lateral non-uniform doping).
Halo implants only add small increases of Vt for long devices, but
much larger increases can be seen with short channels. For
conventional MOSFETs the threshold voltage should not roll off
more than 100 mV. Transistors could not be fabricated below 0.3 µ
m without the use of halo implants, as per this requirement.
Its compatible process flow with the conventional CMOS made halo
devices to receive much attention from the semiconductor industry
even down to 50 nm technologies [48]. Using a tilted implantation
after the gate electrode formation, these halos are obtained. This
introduces another process parameter, tilt angle, which needs to be
optimized along with the other halo implant parameters. Schmitz et
al. have optimized halo implant parameters for 0.18 μm low-power
CMOS technology and reported that, for the same energy and dose,
a boron halo implanted with lower tilt angle results in poor short
channel behavior, while a larger tilt angle gives a higher sub-
threshold swing, leading to an optimized medium tilt angle for
higher Ion/Io f f [46].
It was also shown, in the same work that hot carrier effects do
not show dependency on tilt angle. Also, Wen-Kuan Yeh et al. have
reported that a steep Indium halo causes reduced reverse short
channel behavior, hot carrier effects, and increased punch through
compared to Boron-halo for N-MOSFETs [49]. Recently, the effect of
halo implantation on the 1/ f noise performance of MOSFETs was
also looked into [53]
Other important aspect of the channel engineering, which has
been extensively reported for enhanced performance of scaled
technologies, uses the concept of device asymmetry. The early
work on these devices was started by Chen et al. proposing sub-
micron large angle tilt implanted drain technology (LATID) for
mixed signal applications [55]. These devices have shown
improved analog performance parameters and immunity to hot
carrier effects. Also, Miyamoto et al. reported an asymmetrically
doped buried layer (ADB) structure, for low-voltage mixed signal
applications [54].
The output resistance of these devices is improved by the
absence of the pocket implant at the drain side. Later, Odanaka et
al. reported the concept of using asymmetrically tailored channel
doping (having higher channel doping at the source compared to
drain side) to enhance the carrier velocities resulting in a higher
transconductance compared to conventional devices [56].
In the late nineties, lateral asymmetric channel MOSFETs,
whose structure is similar to the device proposed by Odanaka et
al., as shown in Fig. 2.27, have been proposed for high
performance digital CMOS due to their excellent short channel
effects [57–59]. These devices have reduced channel doping at the
drain, and decreasing peak lateral electric fields in the channel
resulting in reduced DIBL. Further, built-in electric fields at the
source side due to higher channel doping enhance the carrier
velocities resulting in good Ion/ Io f f in sub 100 nm regimes. Lack of
�

the pocket at drain also reduces the leakage currents due to band-
to-band tunneling in these devices. Most of the reports in LAC
devices deal with low angle of implantation of halo only. Shin et al.
reported the concept of 0.1µm MOSFET’s with Asymmetric Halo by
Large Angle Tilt Implant (AHLATI) which aids considerably in
suppressing short-channel and hot carrier effects while enhancing
the current driving capability [60].
2.8.3. Hot Carrier Effects in Engineered MOSFET

As explained earlier, sub-micron CMOS technologies

commonly implement channel and source/drain engineered
MOSFETs in order to control short channel effects. Even if these
structures are expected to reduce the change in Vt due to DIBL and
improve punch through control, the impact of device engineering
on long term reliability must also be considered. Specifically, the
effect of device engineering on hot carrier degradation needs to be
factored into the equation for determining the optimum device
design.
Since halo implants increase the doping concentrations near
the drain-substrate junction (or drain extension-substrate junction
in the case of LDD structures), the junction becomes more abrupt
and the electric field in this region increases [61]. In addition, the
location of the peak electric field moves toward the Si/SiO2
interface when halo implants are used. Hence, it is widely believed
that devices with halo implants are more susceptible to hot carrier
degradation. Also, structures with the halo implant performed after
the sidewall spacer process and source/drain implantation
exhibited increased hot carrier degradation compared to structures
with the halo implant preceding the sidewall spacer and
source/drain implantation [62]. In a recent study, the tilt angle (see
Fig. 2.37) as well as the energy of the halo implant was found to
play a significant role in hot carrier behavior [61].

Fig. 2.37: Halo implants with different tilt angles for an LDD n-
channel MOSFET.
 Modern MOSFET technologies as mentioned in section 2.4.1,
commonly implement LDD structures in order to shift the position
of the peak electric field toward the drain and reduce the
magnitude of the peak field [13, 17]. Source/Drain engineered
structures such as these are much less susceptible to hot carrier
induced degradation. The peak electric field along the channel
exhibits a minimum value as a function of the n- dose [20, 62].An
increase in the n- dose above this point will cause the peak field to
increase because Leff is reduced [62]. Hot carrier degradation in
LDD devices therefore can be optimized by controlling the n- dose.
2.9 SILICON ON INSULATOR TECHNOLOGY
2.9.1 Overview
Silicon-On-Insulator (SOI) technology, which was originally
developed for military applications, is emerging as a mainstream
technology after long history of struggle. CMOS technology on SOI
substrate was developed roughly 25 years ago. A cross-section of
an SOI MOSFET is shown in Fig. 2.38. In this structure, the silicon
film lies on top of a buried oxide layer. The process flow and device
characteristics of SOI MOSFETs closely resemble those of bulk
MOSFETs in many respects. Due to the presence of the buried
oxide, however, parasitic capacitances are reduced, and this allows
switching characteristics faster than those of bulk MOSFETs [63]-
[70].

(a) (b)
Fig 2.38 : (a) A schematic representation of the SOI MOSFET.
The thin silicon film
lies on top of the buried oxide layer. In a fully
depleted SOI, tSi is so thin
(~10 nm) that the depletion region extends to the
buried oxide interface.
(b) TEM image of a partially depleted SOI MOSFET
with a 45 nm gate
length. from [24]

At earlier times, research activity was mainly focused on

wafer fabrication techniques, and the quality of the SOI substrate
was poorer than the bulk wafer. With the emergence of new
fabrication techniques such as SIMOX (Separation by IMplanted
OXygen) and BESOI (Bond-and-Etch back SOI) in the mid 1980s,
high quality SOI wafers became available.
Since then SOI technology has improved dramatically, and
has been applied in IC design for high temperature ( 400°C ), rad-
hard (300 Mrad), high density (16 Mb DRAM), high speed (several
GHz) and high performance, low voltage circuits (0.5V). SOI CMOS
technology is likely to be an alternative for deep sub-micron CMOS.
It appears to be the best option for low-power electronics. SOI
MOSFETs provide reduced capacitance, low body effect, sharp
subthreshold slope and high current driving capability. Therefore,
they offer excellent low-power low-voltage performance. SOI
technology has attracted many major IC companies. Engineers
from IBM have manufactured SOI chips that improved the
performance by upto 35 percent. They are already producing SOI-
based chips in a pilot production and will introduce the technology
on its manufacturing lines in first half of 1999.

IBM began to use SOI in the high-end RS64-IV "Istar"

PowerPC-AS microprocessor in 2000. Other examples of
microprocessors built on SOI technology include AMD's 130 nm, 90
nm and 65 nm single, dual and quad core processors since 2001.
Freescale adopted SOI in their PowerPC 7455 CPU in late 2001;
currently Freescale is shipping SOI products in 180nm, 130nm,
90nm and 65nm lines. The 90 nm Power Architecture based
processors used in the Xbox 360, PlayStation 3 and Wii use SOI
technology as well. Competitive offerings from Intel, however, such
as the 65 nm Core 2 and Core 2 Duo microprocessors, are built
using conventional bulk CMOS technology. Intel's new 45 nm
process will continue to use conventional technology.

2.9.2 Device Physics

Depending on the silicon film thickness t si and the channel
doping concentration, the SOI-MOSFET can be operated in two
different regimes: partially-depleted (PD) and fully-depleted (FD)
[66]. The device characteristics and the requirements for
fabrication are different for each regime.

2.9.2.1 PD-SOI

If the thickness of silicon film t si is larger than the strong

inversion depletion width, then the channel region is partially
depleted during device operation. In many respects, the device
characteristics of PD-SOI are similar to those of conventional bulk
devices. The absence of substrate contacts in PD-SOI results in a
floating-body (kink) effect, which is not present in bulk planar
MOSFETs. In PD-SOI, when n/p type carriers are generated in the
n/p type substrate during device operation, they accumulate in the
channel region, since there is no exit path. These accumulated
carriers will positively/negatively bias the p/n type substrate
affecting many electrical characteristics of the device. The
subthreshold slope and drive current are improved by the presence
of the floating-body effect, which can benefit circuit performance.
However, the floating body effect also causes a transient effect on
circuit delay, which makes circuit design more complicated. On
balance, the floating-body effect may be undesirable and should be
controlled by a method such as lifetime adjustment. With device
scaling, the importance of junction capacitances in bulk MOSFETs
has been reduced, but not significantly, because the channel
doping has also been increased to suppress short-channel effects.
Thus, the advantages of SOI, i.e., reduced capacitances and the
kink effect, will continue to give improved performance as long as
the floating body effect can be well controlled.

2.9.2.2 FD-SOI

In terms of suppressing short-channel effects (SCEs), PD-SOI

does not offer any noticeable advantage as compared to the
conventional bulk MOSFET because PD-SOI devices use a very
similar channel doping profile and device geometry. Thus, the
scaling scenario for PD-SOI may not go beyond the 70-nm
technology node where the gate length is about 30 nm. One
possible solution to the problem of how to scale devices beyond
this limit is a FD-SOI. If the SOI layer is very thin so that the
depletion region extends to the bottom Si/SiO2 interface, the device
channel is fully depleted. Both the silicon channel thickness and
channel doping determine whether the device operates in a PD or
FD regime. FD-SOI provides better control of SCEs as compared to
PD-SOI. However, to take full advantage of FD operation, a very
thin silicon channel (~10 nm) is required to reduce the effective
junction depth, which may not be easily manufactured. Also, the
series resistance of the thin channel and shallow source/drain
regions in thin SOI films will degrade device performance. Overall,
the performance gain by using a FD-SOI MOSFET may not be
significant.

Figure 2.39 shows the VT roll-off trends of SOI MOSFETs with

the silicon channel thickness as a parameter. As shown, the worst-
case short-channel effect is seen near the transition between PD
and FD operation for a given channel doping. In the SOI MOSFET,
due to the presence of the thick buried oxide in which the electric
field has vanishing magnitude, the field from S/D has no other
choice but to terminate in the device channel by coupling through
the buried oxide. In the FD-operation, such an undesirable
coupling directly affects the potential in the channel region,
which in turn degrades the short-channel behavior of the
transistor. If the silicon channel becomes thinner in the FD
regime, the corresponding junction depth becomes shallower,
which reduces the influence of SDEs in the channel region.

As a result, to take advantage of the good short-

channel characteristics of FD-SOI, an extremely thin silicon
channel is required to reduce the influence of electric fields
from S/D. However, there are problems with making SOI MOSFETs
with extremely thin channels. First, the series resistance in the thin
SDE region degrades I on . We may solve this issue by using raised
source drain extensions. Second, as we saw in the previous section,
with current SOI fabrication methods, it is very difficult to control
the silicon channel thickness with the accuracy required for fully-
depleted SOI. Overall, FD-SOI may not be a more attractive choice
than PD-SOI.

Fig. 2.39 : Short-channel effects (VT roll-off) in SOI as a function

of a silicon channel thickness for a given doping concentration.
[32]

2.9.3 Advantage of SOI CMOS over conventional

Bulk CMOS technology
SOI CMOS technology possesses many unique properties for
low power low voltage applications as discussed in the following
paragraphs.
• High integration density and simplified process

SOI CMOS offer a higher integration density than bulk CMOS.

This high density results mainly from the absence of wells in SOI
technology. SOI CMOS devices can be isolated by reach through
oxidation, while bulk devices normally use junction isolation.

• Latch up free

In conventional bulk CMOS technology, special care must be

taken to prevent latch up that occurs because of the parasitic P-N-
P-N structure inherent in the CMOS structure. The latch up path in
bulk CMOS can be symbolized by two bipolar transistors formed by
the substrate, the well, the source and drain junctions. Latch up
can be triggered by different mechanisms such as node voltage
overshoot, junction avalanching and photocurrents. A necessary
condition for latch up occurrence is that the current gain of the loop
formed by the two bipolar transistors is larger than unity. In an SOI
CMOS inverter, the silicon film containing the active devices is thin
enough for the junctions to reach through to the buried insulator. A
latch up path is ruled out because there is no current path to the
substrate.

• Reduced parasitic capacitances

SOI CMOS devices are isolated from each other dielectrically.

Such isolation reduces the parasitic junction capacitance. In a bulk
CMOS device shown in figure 2.40 (a), the parasitic junction
capacitance consists of two components: the capacitance between
the drain and the substrate, and the capacitance between the drain
and the channel stop implant under the field oxide. As the device is
scaled down to small dimensions, the high substrate doping must
be used to minimize the short channel effects. This increases the
parasitic junction capacitance. In SOI CMOS devices shown in
Figure 2.40 (b), there is only one component of parasitic
capacitance between junction and the substrate. As the thick BOX
layer (> 300nm) is used in SOI, this capacitance is much smaller
than its corresponding counterpart in a bulk device. This reduction
 of parasitic junction capacitance contributes to the excellent speed
performance observed in SOI CMOS circuits. The presence of the
buried oxide not only reduces the junction capacitance, it reduces
other parasitic capacitances as well (i.e. all the parasitic
capacitances between the silicon substrate and the various
terminals).

(a) (b)

Fig. 2.40: Parasitic junction capacitances in bulk and SOI

MOSFET.

• Subthreshold performance

Subthreshold slope is a function of the ratio of depletion

capacitance Cd to oxide capacitance Cox . In a bulk Silicon CMOS
technology, the scaling down the channel length results in a roll-off
of the threshold voltage, which is called short channel effect. It is
due to the loss of control by the gate to part of the depletion zone
below it. In order to minimize the short channel effect, one should
increase the doping level in the channel region. This increases Cd
and results in an increase in inverse subthreshold slope. In a
partially depleted SOI structure, the short channel effects are not
as serious as in bulk Silicon CMOS. Therefore, it is possible to
optimize the channel doping profile to achieve better inverse
subthreshold slope with minimum short channel effects. In a thin
film SOI device, the channel region is fully depleted. This results in
an inverse subthreshold slope in FD SOI MOSFET close to the ideal
value of 60 mV/decade. The lower inverse subthreshold slope is
highly desirable for low-power low-voltage applications because it
allows the use of devices with a smaller value of threshold voltage
without an increase in leakage current. This reduces the static
power consumption significantly.

2.9.4 Fabrication of SOI MOSFET

Many different methods exist to fabricate SOI wafers. In a
broad sense, various SOI fabrication methods can be divided into
two different categories: Separation by IMplanted OXygen (SIMOX)
and Bond-and-Etch-back SOI (BESOI). In this section, we will review
the current status of various fabrication methods.
SIMOX is currently a leading process to manufacture SOI
wafers [31]. Fig. 2.41 outlines the SIMOX process. Basically, oxygen
ions are implanted into a silicon wafer and annealed to form a
continuous buried oxide layer. In the Internal Thermal Oxidation
(ITOX) method, which is a variation of the SIMOX method, an
additional oxidation step as in Fig. 2.41 (c) is added to thicken the
buried oxide layer and form a better Si/SiO2 interface. High defect
density in the silicon caused by the oxygen implantation is one of
the problematic issues that arise with this method.

(a) Oxygen implantation (b) Anneal

(c) ITOX

Fig.2.41 : SIMOX-ITOX method: (a) Oxygen implantation into

silicon wafer (b)
wafers are annealed and a continuous buried oxide
layer is formed (c) In
the case of ITOX, thermal oxidation step is added [32].

In the BESOI method, the buried oxide layer is grown on one

wafer and the SOI layer is transferred from the second wafer and
then selectively separated by a few different methods. One such
technique is called the SMART-CUT method [32] and is shown in
Fig. 2.42.
After the buried oxide layer is grown on wafer A, hydrogen
ions are implanted underneath the silicon surface and annealed.
This forms micro cavities in the silicon region at a depth
determined by the ion implantation energy. Then, the top oxide
interface is bonded to wafer-B using OH-bonding mechanism. After
an annealing process to remove defects and strengthen the bonds,
the second wafer can be selectively separated, since the region
with micro cavities is mechanically very weak.

Fig.2.42 : Smart-cut process: (1) Buried oxide is grown on wafer-

A (2) Hydrogen
ions are implanted to generate micro cavities at a
predetermined depth
(3) Wafer-A and B are bonded (4) Wafer-A is separated
via the weak
region formed by H+ implantation (5)-(6) Top surface is
polished [24].

Another category of BESOI is the ELTRAN method developed by

Canon [3.6]. In this method, the combination of porous silicon
formation and epitaxy is used in conjunction with wafer bonding. A
schematic illustration of the ELTRAN process is shown in Fig. 2.43.
Although this is a promising new technology with a good control of
SOI thickness, this method still needs to be improved, e.g., defect
density due to the growing epi layer on porous silicon should be
reduced. Note that regardless of the method chosen, with current
SOI fabrication methods, it is very difficult to achieve the level of
accuracy and uniformity required to make thin (tSi=10 nm) FD-SOI.
Fig.2.43 : ELTRAN process: (1) Wafer surface is made porous by
anodization in
(HF+C2H5OH). Epi silicon is grown on the porous-Si
layer. Top silicon
surface is oxidized to form a buried oxide layer. (2)
Wafer is bonded to the
“buried” oxide (3) Wafers are separated and H2
annealing smoothens the
surface [24].

Fig.2.44 : (a) TEM image of bonding interface (b) SEM images

illustrate the
formation of porous silicon with anodization (c)
Smoothened surface
after H2 annealing [24]

2.9.5 Challenges of SOI Technology

It is generally acknowledged that SOI CMOS provides better device
performance than its bulk counterpart. However, the presence of
the BOX layer also results in self heating and floating body effects.
Self heating is due to the thermal isolation of transistors from
the substrate by the buried insulator. As a result, removal of
excess heat generated within the SOI devices is less efficient than
in bulk devices, which may result in a substantial increase in device
operating temperature. Self heating effects are, however, less
serious in low power applications since the power consumption is
minimized in the design. In an SOI MOSFET the silicon film under
channel region is electrically floating. A neutral region exists in
partially depleted SOI NMOS devices, as shown in Figure 2.45, and
introduces a potential barrier between the source and drain. Figure
2.45 illustrates the operation of the partially-depleted SOI NMOS
device biased in saturation region ( Vds > Vgs - Vt ). The floating body
results in several parasitic effects which are discussed in details in
the following sections.

Fig.2.45 : Cross section of partially depleted SOI NMOS biased at

Vds >Vgs - Vth

2.9.5.1 KINK EFFECT

The first of these parasitic effects is the appearance of
a kink in the output characteristics of an SOI MOSFET, as
illustrated in Figure 2.46. The kink effect can be explained as
follows. As VDS increases, electron-hole pairs are generated due to
impact ionization. Electrons can easily move into the drain
region while holes migrate to the floating body, where the
potential is low. Holes cannot be extracted through the substrate
because of the existence of the buried oxide layer and are trapped
in the neutral region. The accumulation of holes increases the
potential in the bulk and results in a decrease in the threshold
voltage. In turn, a kink is observed in saturation region.
Although floating body effects are difficult to control,
they can be utilized to boost circuit performance. Methods
such as germanium implantation can be used to control the
kink effect [66]. Another important phenomenon specific to
the SOI MOSFET is the history-dependence of the circuit delay
[66]. Due to the floating body effect and the resulting biasing of
the substrate, there is some circuit delay dependence on the
previous history of the circuit operation, which can be as
much as 10%. Unfortunately, this effect becomes more serious as
the operating voltage is scaled down.

Fig.2.46 : Variation of Drain current with the gate voltage in PD

SOI MOSFET showing the KINK effects.
2.9.5.2 SINGLE TRANSISTOR LATCH-UP
A parasitic bipolar transistor exists in the MOSFET structure
illustrated in Fig. 2.47. Due to the presence of a floating body, the
lateral bipolar action becomes more pronounced in SOI MOSFET.
The base current in the parasitic bipolar is formed due to the
impact ionization near the channel-drain junction. The parasitic
BJT effects are more serious in NMOSFET than that in
PMOSFET, because the impact ionization is more pronounced in
NMOSFET than in PMOSFET. In any bulk NMOSFET, the holes
generated by the impact ionization flow to the substrate as the
substrate current. However, in the SOI structure, holes generated
by the impact ionization are trapped in the neutral region. If the
minority carrier lifetime in the silicon film is high enough, the
parasitic NPN BJT presented in the NMOSFET device can amplify
the base current(i.e. the hole current generated by impact
ionization near the drain). It results in an increase in drain current.
As a consequence, when the current is higher than certain level,
the parasitic BJT will be dominant. NMOSFET device behaves as an
open base BJT. The gate may even lose the control to source drain
current. This phenomenon is known as the “single -transistor latch
up” as illustrated in Figure 2.47. It may cause malfunction of the
circuit. Notice that such effect only happens when Vds is larger than
Vgs − Vt , since the impact ionization only occurs when the device
operates in the saturation region.

Fig.2.47 : Parasitic NPN bipolar junction transistors in SOI

NMOSFET structure.

2.9.5.3 REDUCED DRAIN BREAKDOWN VOLTAGE

Because of the existence of parasitic NPN BJT structure
in SOI NMOSFET, the current generated by the impact
ionization is amplified. This results in the reduced breakdown
voltage of SOI NMOSFET. Generally, the larger is the beta of
parasitic BJT, the smaller is the breakdown voltage. This reduction
of breakdown voltage is more significant in short channel devices
and when the good lifetime SOI materials are used, since the beta
in such kind of devices is much larger than unity. In summary, the
presence of the floating body gives rise to a series of problems
during device operation and degrades the device performance.
These effects have their origin in the charging/discharging of the
floating body by currents coming from the source or the drain
and in the capacitive coupling between the gate and the floating
body.
It is likely that scaling of the conventional planar MOSFET
may hit the physical barriers within this decade. If the bulk planar
MOSFET cannot improve the circuit performance, different
materials systems or alternative device architectures may be
required to continue the CMOS scaling.
In this chapter, we present the current status of research or
more precisely a literature review on the prospects of promising
material systems and alternative device architectures. Among the
different material systems, metal gate technology as the gate
material and the physics of High-K dielectric as the gate insulator
will be discussed. In the midst of many interesting structures
proposed so far, we choose to analyze the the double-gate (DG)
MOSFET, the FinFETs and the surrounding-gate MOSFETs. We will
analyze the device physics associated with each device structure
and the proposed methods of fabrication.

2.10 METAL GATE TECHNOLOGY-GATE ENGINEERING

For traditional CMOS fabrication, n+ poly silicon is used as
the electrode for NMOSFETs, and p+ poly silicon is used for P-
MOSFETs. With the scaling of poly silicon gate length to sub-0.1-µm
and the gate oxide thickness to below 3 nm, further performance
such as the high gate resistance, the boron penetration, poly silicon
gate depletion, and increasing of gate tunnel leakage occur. A
proposed solution for all these problems is the use of metal gates
instead of poly silicon gates. A metal gate structure using
refractory metals such as tungsten [33], [34] and titanium nitride
[34], [35], therefore, seems to be promising because of the
elimination of the depletion effects.
Several material systems and process integration approaches
for achieving multiple gate work functions have been investigated
to date: dual metal (Ti/Mo), metal(Ti/Ni) inter diffusion, metal
alloying (Ru/Ta), fully silicided doped poly-Silicon, and the tunable-
work-function metal (Molybdenum) gate [33]-[53]. The metal gates
must have suitable work function and required thermal and
chemical stability with underlying thin gate dielectrics for gate-first
CMOS processing, especially for High-K dielectrics such as HfO2,
ZrO2 and their silicates. However, mid-gap work function metal
gates are subjected to a serious problem that the threshold voltage
for the metal gate MOSFET is larger than that for the poly silicon
gate transistor. A buried channel, however, should become
indispensable for the metal gate structure to obtain an optimal
threshold voltage for not only PMOSFET but also for the NMOSFET
since the work function of the metal is located near silicon mid-gap
[36].
To replace n+ and p+ poly-Silicon and maintain scaled
performance, it is necessary to identify pairs of metals with work
functions that are respectively within 0.2eV of the conduction and
valence edges of Silicon, i.e., the work function, Φ m , for NMOS and
PMOS gates must be near 4eV and 5eV, respectively. Mid-gap work
function metals (e.g., TiN and W) are inadequate for advanced
bulk-Silicon CMOS devices due to high threshold voltages and
severely degraded short channel characteristics. Abe et. al [36] had
reported a simulation study on the poly depletion effects of the
metal gate and the poly silicon gate MOSFETs with a long channel
of 100 µ m. In Fig. 2.48(a), at the inversion region of Vgs > 0 V, the
C gate / Cox ratio for the metal gate structure monotonically increases
with an increase of Vgs , while the ratio decreases over Vgs ~ 0.8 V
for the poly silicon gate structures, which should be attributed to
the gate depletion effect. As a result a high value of 96% was
obtained for metal gate at Vgs =1.5 V, which scarcely depended on
the channel doping profile unlike poly silicon gates.
In Fig. 2.48(b), the g m value for the metal gate structure is
much larger than those of the three poly silicon gate structures
because of no depletion effect. The metal gate structure, however,
shows the larger subthreshold slope increasing with an increase of
I off , which is due to strong buried channel effect to keep the
appropriate threshold voltage.
 In summary, the depletion free effect for the metal gate
configuration suffers remarkably from undesired influences of the
buried channel structure which is indispensable to obtain an
optimal threshold voltage. Consequently, the drivability for the
metal gate is comparable to that for the poly silicon gate under the
commonly used conditions. Moreover, the metal gate would be less
effective with scaling down in the MOSFET because of the stronger
buried channel effects.
The refractory metals have become superior candidates for
the gate electrode to solve the problems associated with the poly
silicon gates. Sputtering deposition of the metal gate electrode is
more favorable than the chemical vapor deposition (CVD) for the
conventional CMOS process, because the impurity contained in the
CVD metal degrades the dielectric reliability at high-temperature
annealing process. The surface damage of the gate dielectric
during the sputtering deposition, however, is one of the remaining
major problems. Therefore, mode of reducing the surface state
density becomes the key in improving the performance of metal
gate MOSFETs. Although there are many choices for replacement of
poly silicon as gate material, the most popular of them are W/TiN
and Molybdenum layers. Here we would see the various issues
related to fabrication and control of device operation.

(a)
(b)
Fig.2.48 : Normalized gate capacitance (Cgate=Cox) as a
function of the gate
voltage for the metal and polysilicon gate structures.
(b) Transconductance (gm) and subthreshold swing
(S) as a function of
the subthreshold leakage current (Ioff)

Fig. 2.49 shows the main process steps of damascene W/TiN

stacked gate MOSFETs [37]. The original wafer was P (100).
Considering TiN as a kind of midgap material, the doping
concentration of the well is approximately lowered. To further
nullify the effect of increased threshold voltage due to midgap
work-function, Super Steep Retrograde (SSR) channel doping may
also be adopted. Si3N4 dummy gate electrode was patterned by
electron-beam lithography and line-width reducing etching. Ultra
shallow source/drain (S/D) extension regions were formed by Low
Energy Implantation (LEI) after the thin TEOS sidewall formation.
Before S/D implantation, the second TEOS sidewall was made to
form a double sidewall structure to improve the short channel
effect, which is caused by the diffusion of S/D extension region.
Then the S/D implantation was performed with dummy Si3N4 gate
electrode on a dummy gate oxide. To obtain a plane wafer surface,
a method is suggested in [37].

Fig. 2.49: Main process steps of damascene W/TiN stacked gate

MOSFETs [47].
Molybdenum (Mo) has very low resistivity ( 5X10-6 Ω-cm) and
high melting point(>2600o C), and thin films of Mo with (110)
crystallographic texture have been shown to exhibit work functions
close to 5eV on several candidate dielectrics. Molybdenum has an
excellent compatibility with CMOS processing and a matching
coefficient of thermal expansion with the Silicon lattice. These
observations suggested that Molybdenum can be a potential
candidate for a single metal dual-work function technology
provided that a sufficient and stable work function shift can be
obtained.
CMOS fabrication with Molybdenum as gate material was
reported in [39]-[41]. CMOS devices were fabricated using
Molybdenum as the single gate electrode material. Mo (110)
exhibits a high work function that is suitable for bulk p-FETs, and this
value can be lowered for n-FETs with nitrogen (N) implantation.
With further optimization, this technology can potentially be used
to achieve dual gate work functions for CMOS devices. In multiple
VT technologies optimized for the performance and the power, this
gate work function adjustment technique provides another flexible
approach to implementing threshold voltage CMOS circuits. It is
known that that metal work functions depend upon on the bulk and
the surface material properties, crystalline orientation, and the
permittivity of the dielectric interfacing with the metal.
It will however be necessary to control the microstructure of
deposited Molybdenum film and any post-gate thermal processing
that could alter the interface and the microstructure of the
Molybdenum film. Implantation of N+ ions to modify the work-
function of thin films of Molybdenum should be carried out at very
low implantation energies in order to minimize ion penetration into
gate dielectric while allowing for high atomic Nitrogen content
within the Molybdenum films. The variation of gate capacitance
with the gate voltage for implanted and un-implanted nitrogen is
shown in fig. 2.50.

Fig. 2.50: Typical high-frequency C-V curves of p-FET (left),

with unimplanted Mo
gate electrode, and n-FET (right), with nitrogen
implanted Mo gate
electrode. [46]
The evolution of Molybdenum gate work function with
annealing temperature is shown in Fig. 2.51 below. It can be seen
that the Molybdenum gate work function (~4.95eV) decreases with
increasing anneal temperature (Tanneal), and saturates at ~4.5eV for
Tanneal > 900oC. The cause for this change can be traced to an
evolution of the Molybdenum film chemistry with annealing.
 Fig. 2.51: Variation of Mo work function with thermal annealing
[46]

2.11 HIGH-K DIELECTRIC TECHNOLOGY

With the apparent physical limit of the SiO2 gate insulator on
the horizon, active research is being conducted in many
laboratories to find its successor. In this section, we will review the
requirements for high-k gate dielectrics, the current status of this
research, and the future outlook. Materials with a high dielectric
constant or “high-k”, to first order, give the same electric behavior
although they are physically thicker than SiO2. Materials such as
hafnium oxide (HfO2), aluminum oxide (Al2O3), and many
others are being studied as possible candidates to continue
gate dielectric scaling [54],[56,57]. However, there are significant
challenges for all of them to succeed the Si/SiO2 material
system, which has been dominant in manufacturing over the last
three decades.
Since it is possible to manufacture sub-15 Å gate oxides with
SiO2, to be useful at all, a high-k material should provide a sub-10 Å
equivalent oxide thickness. Not only that, it must improve the drive
current while significantly reducing the gate leakage current as
compared to SiO2. As shown in Fig. 2.52, materials with a higher
dielectric constant show a tendency to be associated with a
lower band-gap, which reduces the effectiveness of these
materials in suppressing gate leakage current. On balance,
 though, high-k gate dielectrics can still reduce the gate leakage
current while maintaining the same electrical thickness as
compared to SiO2.

2.11.1 Issues with High-K materials

 Material/process compatibility:
So far, most high-k materials come with an interfacial layer. The
existence of this interfacial layer significantly reduces the
effectiveness of the high-k gate dielectric. It is also very difficult to
control deposition processes (crystallization, oxidation, etc.).

 Short-channel effects:
Many of the high-k materials require the use of a metal gate for
processing reasons, since poly silicon tends to form an
interfacial oxide layer. Mid-gap metal gate with a work function
equal to intrinsic silicon (e.g., tungsten) would have to be used.
However, the channel needs to be undoped in that case to tune the
threshold voltage correctly, and the lack of channel charge in
the bulk MOSFET may result in severely increase the short-
channel effects.

 Mobility degradation:
The effective vertical electric field at the interface has been
increasing and is often in the surface roughness scattering
regime where the mobility degrades with strong field dependence.
It is not realistic to expect the interfacial quality between silicon
and any high-k material to be as good as that of the Si/SiO2
interface. Any degradation of the surface roughness as
compared to the Si/SiO2 interface will amplify the mobility
degradation due to surface scattering and will significantly
reduce the drive current. Because of this, the drive to use a high-k
gate dielectric may first come from applications that target low-
power operations combined with reasonable performance. In the
high-performance arena, it may be possible to deal with high gate
leakage, but in the low-power regime, it is crucial to drop the
standby current by cutting this leakage and the active current by
dropping the supply voltage. In conclusion, we still do not have a
promising candidate material to replace the Si/SiO2 system and the
diminishing returns from the gate oxide scaling make it uncertain
how much we will gain by using the high-k gate dielectrics.

Fig. 2.52: Variation of bandgap of different materials with

dielectric constant

2.12 DOUBLE GATE MOSFETS

In this section, we will describe a different approach to
transistor scaling: non-planar device structures. One of the most
promising candidates in this category is a double-gate (DG)
MOSFET (Fig. 2.53), which was originally conceived by Sekigawa
et al. [71]. This device structure is a focus of current
research due to the superior control of short-channel effects
and higher drive current per unit silicon area provided by the
structure
 Fig 2.53: Structure of a Double gate MOSFET (top): Three
dimensional view,
(bottom): Front view structure used for major 2D
simulation study

The double-gate MOSFET originally proposed in 1984 as

"XMOS" by the Electro technical Laboratory (ETL) under the Agency
for Industrial Science and Technology has been expected to be the
most advanced transistor giving a breakthrough to the scaling limit
due to increasing leakage current and short channel effects in the
ordinary single- gate MOSFET.
The double-gate FET (DG FET) shown was proposed in the
early 1980s. The concept has been gradually explored both
experimentally and theoretically by many groups. The Monte Carlo
and drift-diffusion modeling clearly showed that a DG FET can be
scaled to a very short channel length (25 to 30 nm) while achieving
the expected performance derived from scaling.
2.12.1 Device Physics
In conventional bulk MOSFET and PD-SOI devices,
immunity from the short-channel effects such as the V T-roll off
and the drain-induced barrier lowering (DIBL) requires
increasing channel doping to reduce the depletion depth in
the substrate. Even when retrograde channel profiles are used
to reduce mobility degradation and the threshold mismatch,
this approach intrinsically trades the improved short-channel
immunity for an increased substrate-bias sensitivity and
degraded subthreshold swing. However, by replacing the
substrate with another gate to form a double-gate (DG) MOSFET as
shown in Fig. 2.53, the short-channel immunity can be achieved
with an ideal subthreshold swing of 60mV/decade.
The current-voltage characteristics of DG MOSFETs were
reported by [32]. Fig. 2.54 shows the simulations of the
subthreshold characteristics for a 30 nm n-type DG-MOSFET and
a 30 nm conventional bulk MOSFET (dotted curves) with tox =
10 Å. The subthreshold swing of the DG-MOSFET is near the ideal
value of 60 mV/decade while the planar MOSFET suffers from a
degraded swing due to a high channel doping concentration, N A
= 1.2 × 1019 cm −3 .
For the planar MOSFET, this high channel doping was
required to obtain the right threshold voltage and to control
short-channel effects. The threshold voltage Vt was 0.35V for both
devices. For a DG-MOSFET, a nearly intrinsic silicon channel was
used and Vt was adjusted by using gate electrodes with a mid-gap
work-function. Although both the planar and DG-MOSFETs have
the same Vt , the I off of the planar MOSFET is more than one
order of magnitude higher than that of the DG-MOSFET due to a
degraded subthreshold swing from the high channel doping. Also,
the DG-MOSFET shows much higher drive current, since it does not
suffer from a severely degraded mobility caused by high
channel doping and the resultant high vertical electric field.
In the sub-50 nm gate length regime, the validity of
using a drift-diffusion simulator may not provide accurate results.
Especially, when examining the “on” characteristics, e.g., the drive
current, we may be required to use a Monte Carlo method or a
hydrodynamic model to correctly predict the behavior. However, in
the subthreshold regime, where the free carriers are irrelevant
to the electrostatics, drift-diffusion simulators are more
accurate than Monte Carlo methods. Even for the “on”
characteristics, if we are only interested in the steady-state
solutions such as the I-V characteristics, drift-diffusion simulation
can give reasonable results for devices as small as 30 nm
gate length. The fact that the conventional velocity saturation
model can work remarkably well in a ballistic transport regime is
explained by a fortuitous similarity between the thermal velocity Vt
and the saturation velocity Vsat in silicon. Hydrodynamic models
implemented in the conventional drift-diffusion simulators are
supposed to give a better prediction of “on” characteristics such as
velocity overshoot in the ballistic regime. However, even in that
case, extensive calibration of the coefficients is required if we
are interested in quantitatively accurate results. Considering all
these issues and the significant amount of time and resources
required for Monte Carlo simulations, the use of conventional drift-
diffusion models can be justified as long as we do not
emphasize the quantitative details too much. For the purpose of
describing the subthreshold characteristics and qualitatively
comparing different novel device structures, this approach can
provide satisfactory results.
The threshold voltage Vt of a fully-depleted DG-MOSFET can
be controlled either by adjusting the channel doping
concentration, similar to the conventional bulk MOSFET case, or
by changing the work-function of the gate electrodes. However, in
the small gate lengths regime a DG-MOSFET is aimed at, an
undoped silicon channel will be needed to avoid Vt fluctuations due
to discrete, random dopant placements [78].
 If we choose to use an intrinsic silicon channel, then the
threshold voltage is adjusted by using gate electrodes with mid-gap
work-function (e.g., tungsten). Fig. 2.54(a) compares the
subthreshold characteristics of a DG-MOSFET with n+ polysilicon
gate electrodes and a high channel doping of NA = 1.4E19/cm3
and a DG-MOSFET with a near intrinsic silicon channel and
mid-gap gate electrodes with the work-function of tungsten
(4.63 eV).
For these MEDICI simulations, the abrupt and the metal-like
source/drain extensions were used. For planar MOSFET operation,
in the partially depleted regime, a charge sharing analysis tells us
that higher channel doping provides a better suppression of the
short-channel effects. However, as we can see in Fig 2.54 (b),
increasing the channel doping does not improve the short-
channel effects in a fully-depleted DGMOSFET.
 (a)
(b)
Fig. 2.54: (a) Numerical simulation of subthreshold
characteristics for a 30 nm
conventional bulk MOSFET (dotted lines) and a 30 nm
DG-MOSFET.
(b) MEDICI simulation to compare ID-VGS characteristics
between a DG-
MOSFET with n+ poly-Si gates and a DG-MOSFET with a
near intrinsic
silicon channel and mid-gap gates. [32]
Both devices have the same subthreshold swing of near
60 mV/dec since they are in the fully-depleted regime and the
off-state leakage currents of the two devices are very close,
indicating that they have equally good suppression of the SCEs
regardless of channel doping concentration.
For a planar MOSFET or other devices in the partially-
depleted regime (e.g., PD-SOI), the gate length is a major
source of variation in electrical characteristics. For a fully-
depleted DG-MOSFET, however, the silicon channel thickness t si
also becomes a critical dimension, the variation of which
severely affects the electrical performance, such as Vt and I off .
Typically, t si needs to be about 1/4 to 1/3 of the gate length
in a fully-depleted device to control SCEs. Since a fully-depleted
DG-MOSFET is aimed at sub-30 nm gate lengths, the silicon channel
thickness will be on the order of 10 nm. Even if we can fabricate
such a thin silicon channel, the manufacturing variation will
translate into a fluctuation of device characteristics. Fig. 2.55
shows MEDICI simulations for a DG-MOSFET to analyze the
sensitivity of I off to silicon channel thickness variation in the fully-
depleted regime of operation [32].

Fig. 2.55: Sensitivity analysis for a fully-depleted DG-MOSFET

with a thin silicon
channel. The change in IOFF due to tSi variation is
plotted for
LG = 25 nm and 30 nm. An undoped silicon channel
with the mid-gap
 workfunction gate electrodes were used in the
simulations ( [32])

2.12.1 Types of DG MOSFET

A classification of DG devices and their implications on circuit
design is illustrated in Fig. 2.56. There are two main device
processes possible for DG devices, namely (a) symmetric device
with the same gate material (e.g. near mid gap metals) and the
oxide thickness for the front and the back gate [77] and (b)
asymmetric device with different strengths for the front and the
back gates. Different strengths can be obtained by using either
different oxide thickness (asymmetric oxide) or materials of
different work-function (e.g. n+ poly and p+ poly) for the front and
the back gate (asymmetric work-function).

Fig. 2.56: Different types of DG MOSFETs

Regardless of the underlying device process, DG devices can
also be classified in terms of their terminal structure. Typically the
front and the back gates of DG devices are connected together
resulting in a 3-Terminal (3-T) device. 3-T devices can be used for
direct replacement of the conventional single gate bulk CMOS
devices. Recently, double gate devices with independent gate
control option (separate contacts for the back and the front gates)
have been developed. Such DG devices are referred to as
Independent or Isolated Gate (IG) devices. The Ground Plane (GP)
SOI process can also be considered as a class of IG devices with the
exception that the second gate is shared among all the devices. GP
SOI is attractive for dynamic Vt design with dynamic control of the
common back gate bias. IG devices with a second gate for each
device are referred to as 4-Terminal (4-T) devices. In such
technologies, one can choose to connect the back and front gates
together or to control them separately while designing a circuit
resulting in new circuit. Connected back and front gates (3-T
configuration) provides a simple way of mapping circuits designed
in single gate technologies to the double gates technologies.
3-T configuration provides more ON current for transistors as
well. On the other hand, independent gate control (4-T
configuration) can be used for designing new circuit styles. For
example, back gate bias can be used to dynamically adjust the
threshold voltage of the front gate to tune the power and the
performance requirement of a circuit. It can also be used for
merging the parallel transistors or driving non-critical transistors in
single gate driven mode to reduce power dissipation.
Depending on the gate materials and the body doping, three
types of DG device structures have been proposed namely: 1) A
doped body symmetric device with poly gates (n+ poly for NMOS,
SymDG); 2) An intrinsic body symmetric device with (near mid-gap)
metal gates (MGDG); and 3) An intrinsic body asymmetric device
with different front and back gate work functions (e.g., n+ poly/p+
poly, AsymDG); In the SymDG device, the threshold voltage is
controlled using the body doping. In the MGDG device, the metal
work function is used for threshold voltage control, while in
AsymDG devices threshold voltage is controlled by the work
function difference between the front and the back gates. A
comparative study of the three types of DG-FET is shown in Table
2.3.
One of the major advantages of using double gate transistors
is the lower leakage current. The major leakage components in
double gate devices are: (a) subthreshold leakage and (b) gate
leakage (Fig. 2.57). In the double gate structures presence of two
gates and ultra-thin body helps to reduce the Short-Channel Effect
(SCE), which significantly reduces the subthreshold leakage
current.

Table 2.3: Different aspects of Metal Gate, Symmetric and

Asymmetric DG MOSFETs

Body Threshold Advantage Disadvantage

Gate Material Doping Voltage
Control

Metal Gate
eliminates
Poly Complex
Depletion Process due
MGDG Metal Intrinsic Metal Intrinsic Body to use of
Body Work eliminates metal gates
Function random
dopant
fluctuation

Use of Self Random

SymDG n+ Poly Halo Body Aligned Gate Dopant
Doping Doping Technology fluctuation
and Poly
Depletion

Front n+ Poly Work Intrinsic Body Poly

Intrinsic Function eliminates Depletion
Body difference random and difficult
AsymD of Front dopant to realize low
G and Back fluctuation threshold
Back p+ Poly Gate voltage

Moreover, lower SCE allows the use of lower body doping (body can
even be intrinsic) in DG devices compared to the bulk-CMOS
structure. Hence, to induce equal inversion charge, DG devices
require lower electric field compared to the bulk-CMOS structure,
 which also helps to reduce the gate leakage current in the DG
devices. Although the leakage current is significantly reduced in DG
devices, it is important to analyze different leakage current
mechanisms in such devices.

Fig. 2.57:
DG device
structure
and
different
leakage

mechanisms

(a) Subthreshold Leakage:

Electrically coupled front and back gates and the ultra-thin body
reduce the short channel effects in double gate devices, resulting
in a reduction of the subthreshold leakage. Moreover, for an equal
“on” current MGDG device shows lower subthreshold leakage
compared to the SymDG and the AsymDG devices. This is due to
the fact that, the surface electric field is higher in the poly gate
devices (due to higher doping) and the asymmetric devices (at the
front gate due to the large work-function difference between the
front and the back gates) which reduces the mobility (due to higher
surface scattering). Hence, for an equal “on” current MGDG device
can be designed with a higher VT compared to the SymDG and the
AsymDG devices. This is further enhanced by the elimination of
poly depletion in MGDG devices (which is present in the SymDG
and the AsymDG devices thereby lowering the effective gate
 capacitance). Due to the higher VT, for an equal “on” current MGDG
device shows lower subthreshold leakage (Figure 2.58).

Fig. 2.58: Variation of subthreshold current in different types of

DG MOSFETs

(b) Gate Leakage:

Gate leakage in the DG devices is due to the gate to the
channel tunneling and the overlap tunneling current. In the double-
gate and the ultrathin body devices, the control of short channel
effects and the threshold voltage is ideally achieved without the
use of channel dopants. This eliminates the statistical dopant
fluctuation concerns and minimizes the impurity scattering. In
addition, the depletion charge cannot exist because there are no
impurities in the channel. The average vertical electric field in the
channel inversion layer is
ηQinv O
+
Eeff = depl
(2.19)
εSi
where Qinv and Qdepl are inversion and depletion charge densities, εSi
is the dielectric constant for silicon, and η is an experimentally
derived fitting parameter. Since Qdepl is negligible for the DG- FET,
carriers in the inversion layer thus encounter a smaller average
vertical electric field in the thin-body devices than in standard bulk
devices with heavy channel doping.
 This can be seen in Fig. 2.59, in which the slope of the
potential in the silicon channel is dramatically reduced, particularly
at points further away from the silicon/dielectric interface. This
reduction in the vertical field is expected to improve the carrier
mobility, especially as the gate dielectric thicknesses are scaled
and the surface scattering mechanisms become dominant.

Fig. 2.59: Band bending in different bulk, DG and SOI MOSFET

Hence, the DG devices show lower gate-to-channel
tunneling compared to bulk devices as shown in fig. 2.60. This
effect is more pronounced in the MGDG devices as the body is
intrinsic. Hence, midgap intrinsic body devices have lower gate-to-
channel leakage compared to the SymDG devices. In AsymDG
devices due to the work-function difference of the front and the
back gates, the front surface field is very high whereas the back
surface field is negligible. Hence, the tunneling occurs only through
the front gate (which is larger than the MGDG device but smaller
than the SymDG device).
The band bending in the three types of DG MOSFETs are
illustrated in fig. 2.61. In the “off” state ( Vgs =0, Vds = VDD ) overlap
tunneling occurs due to tunneling of electron from the gate to the
n+ drain. In MGDG devices (or in p+ poly back gate of AsymDG
devices) the overlap tunneling occurs due to the tunneling of the
electron below the metal Fermi level (or due to electron tunneling
from valance band of p+ poly). On the other hand, in SymDG
devices tunneling occurs from conduction band of the n+ poly.
Since, the barrier height for tunneling of the electron is higher in
case of tunneling from the metal gate (barrier height = Si-SiO 2
barrier height + Eg/2), MGDG devices show lower overlap tunneling
leakage compared to SymDG devices. In the case of AsymDG
MOSFET, due to the presence of the built-in field, the total field
across the front gate oxide at inversion is higher as
Eoxf = Ebuilt-in + Eband-bending (2.20)

This results in a higher tunneling current through the front gate.

Hence, the total gate current in the AsymDG device is less than
that of the SymDG device (as only one gate is tunneling) but more
than that of the MGDG devices (due to the built-in electric field).

Fig. 2.60: Gate Current Density variation in DG MOSFETs.

 Fig. 2.61: Qualitative analysis of gate tunneling in DG NMOS
devices: (a) SymDG,
(b) MGDG and (c) AsymDG.

2.12.2 IMPLEMENTATION OF DG MOSFET

 Planar DG MOSGET :
The first type of structure shown in Fig. 2.62(a) is close to the
planar MOSFET in geometry except that it has a bottom gate. An
advantage of this topology is the good control of the silicon channel
thickness, which is required for FD operation. However, fabrication
of the self-aligned bottom gate in this structure has been very
challenging. Another problem is that the gate length must be
controlled by lithography.
 Vertical DG MOSFET :
The second type of structure is a vertical MOSFET shown in
Fig. 2.62(b). In this device structure, the current flow is
perpendicular to the wafer and the gate length is defined by non-
lithographic methods such as a timed etch or a thin film
deposition [32]. Originally, Toshiba/Stanford devices were
demonstrated in this category.
One problematic issue with this structure is how to make a
fully-depleted DG MOSFET. Since the silicon channel thickness is
even smaller than the gate length (usually, 1/4 ~ 1/3 of LG) in
Fully Depleted (FD) regime, we may not simply rely on lithography
to define a sub-20 nm channel thickness. However, interesting
ideas have been suggested to control both the gate length and
the silicon channel thickness in a related device structure. In
addition to high-performance logic applications, this vertical
structure is also very promising for DRAM applications, since the
gate length is decoupled from the packing density.
2.13 FINFETS & SG MOSFETS
While the selection of new “backbone” device structure in the
era of post-planar CMOS is open to a few candidates, the FinFET
and its variants show great potential in the scalability and the
manufacturability for nanoscale CMOS. The basic diagram of a
FinFET is shown in fig. 2.63. The FinFET, a recently reported novel
double-gate structure, consists of a vertical Silicon fin controlled by
self-aligned double-gate. In spite of its double-gate structure, the
FinFET is close to its root, the conventional MOSFET in the layout
and the fabrication as shown in Fig. 2.64. The features of this
structure include (1) an ultra-thin Si fin with gate on improved gate
control for the suppression of short-channel effects; (2) two gates
which are self-aligned to each other and to the source/drain (S/D)
regions; (3) raised (poly-Si) S/D to reduce the parasitic resistance;
(4) a short (50 nm) Si fin for quasi-planar topography; and (5) gate-
last process compatible with low-T, high-k gate dielectrics.

(a)
 (b)
Fig. 2.62: Different architectures of DG MOSFET (a) Planer DG
MOSFET (b) Vertical DG MOSFET

Fig. 2.63: Cross section of a FinFET

Conventional bulk CMOS scaling beyond 45nm is severely

constrained by short channel effects and the vertical gate insulator
tunneling [15][20]. Double-gate FinFET technology [79]-[85] has
been proposed as a very promising candidate to circumvent the
bulk CMOS scaling constraint, by changing the device structure
 Fig. 2.64: Fabrication flow of FinFETs

in such a way that the MOSFET gate length can be scaled further
even with thicker oxide, so that we can continue scaling beyond
the limit of conventional bulk CMOS. The various advantages of
FinFETs are listed below.
• Short channel effects reduced
• Very low leakage current
• High On/Off Current ratio
• Low voltage operation
• Efficient gate design Efficient gate design –
• Less switching power
• Flexibility of using multiple fins for better performance
• Compatibility with current manufacturing processes
• Scalability to sub10 nm
The thickness ( t si ) of a single fin equals to silicon channel thickness.
The current flows from the source to drain along the wafer plane.
Each fin provides 2H of device width, where H is the height of the
each fin. For the FinFET devices, widths are quantized into units of
the fins. Large width of device is obtained by using multiple fins.
Figure 2.65 shows a multi-fin FinFET structure.
 Fig 2.65: Multiple-fin FinFET structure

RECENT ADVANCEMENT IN FINFET TECHNOLOGY

• IBM has demonstrated a near ideal behavior of 40nm N-type
FinFET
• Intel has come up with Trigate Transistors, which are very
similar to FinFETs with exception of Gate Fin contact on three sides,
instead of two.
• TSMC has come up with an OMEGA FET
• AMD demonstrated a 10 nm FinFET in 2002, with gate delays
~ 0.43ps (smallest yet)
• Infineon has produced Flash memory cells using FinFETs of
20 nm
• UC Berkeley has been the leading academic institution
involved in FinFETs Research.

SURROUNDING GATE (SG) MOSFET

The surrounding gate MOSFET is a type of the vertical DG

MOSFET in which the cross-section of the silicon channel has a
cylindrical shape and the gate electrode completely surrounds the
device channel region. A schematic cross-section diagram of a
cylindrical MOSFET is shown in Fig. 2.66. The current flows
vertically along the cylindrical Si/SiO2 interface and the gate length
of the transistor is defined by the height of the gate material. A
cylindrical, surrounding-gate MOSFET in the FD-regime has even
better control of short-channel effects than in the “ideal” DG-
MOSFET. This is because of the tight capacitive coupling of the
surrounding-gate to the device channel region from all directions.

Fig. 2.66: Cross section of a surrounding gate MOSFET

Although the surrounding-gate MOSFET offers superior control of

the short-channel effects and higher packing density, obtaining a
high drive current from a thin silicon pillar may be an issue,
especially when it has to drive a large interconnect-load. Using
multiple pillars to increase the drive current can be a possible
solution. Also, when the pillar diameter approaches the sub-10 nm
regime, quantum-mechanical (QM) confinement effects will
significantly increase VT. Compared to the DG-MOSFET, QM
confinement is stronger in a cylindrical structure, since the
confinement comes from all directions. Finally, crystalline
orientation effects around the cylindrical surface may cause issues
with a non-uniform thickness of the gate oxide.

2.14 SUMMARY
In this chapter, we have examined the showstoppers of
conventional CMOS scaling. Past trends based on aggressive gate
oxide scaling will be extremely difficult to sustain beyond another
decade or so due to increasing gate tunneling current. Also the
rigorous gate length scaling capability that has been the
distinguishing feature of the CMOS technology is facing severe
challenges due to the undesirable Short Channel Effects. A review
of existing and upcoming technology developments to provide
better immunity to short channel effects is discussed. Different
material systems like metal gate technology and high-K dielectrics
are illustrated with possible advantages and disadvantages. The
transition from bulk CMOS to SOI MOSFET is explained with further
details of multigate architectures specially the double gate
MOSFETs. In the end, the potential of SOI/DG MOSFETs for analog
and RF circuit applications are discussed with special importance to
low power subthreshold analog applications. Instead of going
through an expensive and time-consuming fabrication process,
computer simulations can be used to predict the electrical
characteristics of a device design quickly and cheaply. Process
modeling and simulation of the fabrication process, can be
predicted so that physical characteristics such as oxide thickness
and doping distribution can be produced with high precision.
Device modeling and simulation can then be used to predict the
electrical characteristics of the given device structure.

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________________
 CHAPTER

3
________________

A NEW THRESHOLD VOLTAGE MODEL FOR

ASYMMETRIC DOUBLE GATE MOSFETS

3.1 INTRODUCTION

In the past three decades, the CMOS technology has rapidly

embraced the market of digital and analog electronics. The CMOS
technologies have remarkably captured the digital market because
of the low power dissipation during the switching time and the high
packing density to implement large complex Boolean Functions.
Moreover the scaling down of the CMOS technology is an easy go
than BJT or MESFET counterparts. Analog circuit design itself has
evolved with this technology as well. High–voltage, high–power
analog circuits containing a few tens of transistors and processing
small, continuous time signals have been gradually replaced by
the low–voltage, low–power analog systems containing millions of
transistors and processing the large and discrete signals. Along
with these applications of the CMOS technology, it has percolated
in the RF market which was previously dominated by the BICMOS,
the BJT and the MESFET technologies [1]-[2].
Therefore an advanced MOSFET called DOUBLE-GATE (DG)
MOSFET takes over the bulk MOSFET in the microelectronics based
industry due to the improved scaling and the reduced SCEs for the
rugged control of the channel by the two gates [4]. Among the
other advantages of the DG MOSFETs are the near 60mV/dec
subthreshold slope, the low Drain-Induced-Barrier-Lowering (DIBL),
the high transconductance and the possibility of using lightly doped
or undoped body [5]. Undoped DG MOSFETS provide the flexibility
of using the metal gates with near mid-gap work function to control
the threshold voltage Vth [6]-[7]. Volume inversion is another
important phenomenon that is observed in the case of multi gate
MOS devices with ultra thin body where the inversion charges
instead of being confined near the Si-SiO2 interface spread near
the center of the channel and this is more evident in the
subthreshold regime [7].
There are different types of DG MOSFETs based upon the
work function of the gate materials used and the voltage applied to
the two gates. When two gates in DG MOSFETs are tied, an
identical voltage is applied to both gates. On the contrary, for the
separated gates in the DG MOSFETs different voltages can be
applied. The front gate may be used as the driving gate and the
back gate is used to tune the threshold voltage and vice-versa [8].
The Asymmetric DG MOSFETs present a greater degree of freedom
to adjust the threshold voltage either by the gate material
engineering or by applying desired voltage to any one of the
separated gates.
In this work, we report a new threshold voltage model for the
asymmetric double gate MOSFETs derived from the two
dimensional Poisson’s equation. Various models are reported
regarding the threshold voltage of DG MOSFETs. Analytical solution
of the 2-D Poisson’s equation by means of the Green’s function
technique [9] is a model to solve 2-D Poisson’s equation. Another
well-known approach to solve the 2-D Poisson’s equation is the
separation of the 2-D Poisson’s equation into a 1-D Poisson’s
equation and a 2-D Laplace equation [10]. Taur et al. [11] derived
a threshold voltage model based on the 1-D Poisson’s equation.
Chen et al. [3] derived a new threshold voltage model using the 2-D
Poisson’s equation.
In our proposed threshold voltage analytical model, a cubic
potential is used in the vertical direction as proposed by [8] so that
it is applicable for 4 terminal DG MOSFETs. Next we use a different
threshold voltage definition as proposed by S.S. Chen et al. [12]
which states that at threshold condition, the sum of electron
densities at the front and back surfaces will be equal to the doping
density of the silicon film.
3.2 ELECTROSTATIC POTENTIAL MODELING

Fig 3.1: The Cross-sectional view of an Asymmetric DG

MOSFET with two
different voltages Vgf and Vgb applied at the top and
bottom gates.

The cross-sectional view of an asymmetric DG MOSFET is

shown in Fig.3.1 where the origin is assumed to be at the top of the
channel oxide interface at the source end. The gate length and the
silicon film thickness are denoted by LG and t si respectively. The
two dimensional Poisson’s equation in the channel area with both
the depletion and the mobile charge term can be written as
qϕ(x ,y )
∂2ϕ( x, y)∂ ϕ2 ( x, y) qN qn i 2
+ = + a e KT
∂x 2 ∂ y2 εsi N
ε si a
(3.1)
where ϕ ( x, y) is the 2-D potential , x and y are the variables along
the length and thickness of the channel respectively, q is the
electronic charge, ε si is the permittivity of silicon, N a denotes the
channel doping concentration, ni is the intrinsic electron density , K
is the Boltzmann constant and T is the absolute temperature. In
 this model, we have used a cubic potential distribution along the
thickness of the channel as
ϕ( x, y) =
P( x0) +P( x1)+
y P( x2+
)y P( x3) 2y 3

(3.2)
The following boundary conditions are used to evaluate P0 ( x ) , P1 ( x) ,
P2 (x ) and P3 ( x ) .
ϕ( x,0ϕ) =( x)f
ϕ( x, t ϕ
)si =(bx)
dϕ ( x, y) ε ϕ f ( x ) − (V fg −V ffb )
y = 0 = ox
dy ε si t
ox

dϕ ( x, y) ε ϕ ( x ) − (V bg −V bfb ) (3.3)
y = tsi = − ox b
dy ε si t
ox

where ϕ f ( x) and ϕb ( x) are the front and back surface

potentials, V fg and Vbg are the front and back gate voltages and V ffb
and Vbfb are the front and back gate flat band voltages respectively.

Fig 3.2: Energy band diagram of an asymmetric DG n-channel

MOSFET biased
 in the Subthreshold regime. The relation between
the front surface and
the back surface potential is obtained from the
similarity of triangle
ABC and triangle DEF.

In Fig 3.2, a geometrical approach based on the similarity of

triangles (∆ ABC and ∆DEF) is applied to calculate the relationship
between the front and the back surface potentials. As proposed in
[8] and viewed from Fig 4.2, ϕ f ( x ) and ϕb ( x) are related as
is
εox tsi '
ϕ f ( x) ϕ
− b ( x)= (−
Vfg Vbg ) '

2εsi tox ε
+ ox tsi

(3.4)
where V fg = V fg − V ffb and Vbg = Vbg − Vbfb are used for simplicity. Using
/ '

the above relation, the 2-D electrostatic potential is given in terms

of the front surface potential ϕ f ( x) as
ε ox V fg − ϕ f( x) 2V fg' − Vbg' ϕ−
'
( x2)
ϕ ( x , y )= f ϕ ( x ) − +y f
y
ε si t ox 2s
ε ox (3 εsit ox+ εoxt si)(V' fg −V' bg)2
− y
tsiε si t ox(2 εsi t ox+ εoxt si)
(3.5)
ε si tox tsi
where s = is used for simplification.
2εox
Unfortunately, it does not provide any information about the
electrostatic potential at any arbitrary depth y = y . The 2-D
potential at any depth y is calculated in [8] as
 εox y ε ox y 2
1+ −
εsi tox ε si tox tsi
ϕ( x, y) = ϕ
× {2 ( x) y
εox y ε ox y
1+ −
εsi tox ε si tox tsi
2
ε y 'ε y ε' V fg' −Vbg' 2
+ ox V− ox
+V fg ox
y }
εsi tox fgε t t
si ox si tsiε ε(2
t
si ox t+
ox si )
ε y ε ox y 2 ε' ox (V fg −Vbg) ' '

− ox V+fg' −V fg y2
εsi tox ε si tox tsi tsiε siεtox o + x tsi )
(2
Replacing (3.5) into the 2-D Poisson’s equation
(3.6)
of (3.1) and setting y =0, we get the desired 1-D differential
equation for solving the front surface potential ϕ f ( x) as follows
∂ 2ϕ f ( x ) V fg' −fϕ( x ) qNa qn2i qϕ KT
( x, y)
(V fg' − Vbg' ε) si tox
+ = +e +
∂x2 s ε si εsi a N s(2ε si tox + εox tsi )
(3.7)
Using the power series approximation, we evaluate the mobile
charge term as
qϕx
( y
, )
%+ qϕx
( ,y )
e KT
1=
KT

(3.7a)
Substituting it into (7), the front gate surface potential is derived
from the second order differential equation as
F
ϕ f ( x ) = C1 e Ex
+ C2 e− Ex
− ,
E
(3.8)
where the constants F & E are
'
qNa V fg ( V fg' − Vbgε' ) t 2
qni
F= − + si ox
, + ,
ε si s s(2 sit +εox oxt )siε si a ε
N
(3.8a)
 1 q 2 ni 2
E= + , .
s ε si Na KT
(3.8b)
The constants C 1 and C2 are solved by the boundary conditions
ϕ f (0) =ϕ f ( LG ) = Vbi
,
(3.8c)
where Vbi is the built in voltage between the channel and the
source/drain. Our model assumes that the drain voltage is
practically 0V. And Vbi is evaluated as
KT N
Vbi = ln( )a
q n i

(3.9)
The constants C1 and C2 are calculated as

F
(1 −e − EL
)(G+
V bi )
C1 = E
− G
(e EL G
−
e EL
)
F
(e EL G
1−
)(V +bi )
C2 = E
− G
(e EL G
−
e EL
)

(3.10)

Before deriving the threshold voltage, it is important to

understand the principle of operation of an asymmetric DG
MOSFET. As the two gate voltages can be applied independently,
the effective threshold voltage actually depend on whether the
front surface or the back surface is the first to reach the “inversion”
condition. This actually depends on the applied voltages of the
front and the back gates as well as their flat band voltages. So a
new threshold voltage model was defined in [12] as the condition
when the sum of mobile charges at the front and the back surface
equals the doping density of the thin silicon channel.
Mathematically the condition is expressed as
qϕf m qϕbm

ne i+ =
ne Na
KT KT
i

(3.11)
where ϕ fm and ϕbm are the minimum surface potential at the front
and back gate respectively. The minimum potential at the front
surface is calculated from (3.8) as
F
ϕ f m = 2 C1 C2 −
E
(3.12)
The minimum potential at the back surface can be calculated from
(3.4). After some simple mathematical calculations, the equation
for finding the threshold voltage Vth (assuming that front gate is
used for achieving the desired threshold voltage) can be written as
Na
e( JVth +L) +e( PVth+ Q) − = 0 ,
ni
(3.13)
where
2 (e E LG
− 1)(1 − e− E LG
)
q( −
− 1) 1 ε sit ox
(e −e
E LG
) E LG
× ( 1)−
J= 2
KT q ni 2 s 2ε si tox + εox tsi
( + )
s ε si Na
(3.13a)
− ELG
2 (e ELG
−1)(1 − e )
q − ELG
V( bi + )qG
G −
(e ELG
−e )
L=
KT

(3.13b)

Where
 1 ε sit ox q n2 1 ε sit ox
−Vbg' ( ) + ( N a +i ) V ffb ( ( − 1))
s 2ε si tox + εox tsi εsi Na s 2ε si tox + εox tsi
G= − , (3.13c)
1 q 2 ni 2 1 q 2 ni2
( + ) ( + )
s ε si Na KT s ε si Na KT

qε si tox
P= J−
(2ε sit ox + εox t si )KT
qε si tox (Vffb − Vbg' )
Q= L+
(2ε sit ox + εox t si )KT

(3.13d,3.13e)

3.3 RESULTS & DISCUSSION

A direct comparison is made between our model and a 2-D

numerical simulation using DESSIS-ISE [13] and a good agreement
is observed. Fig. 4.3 shows the variation of the surface potential at
the front gate for 60nm and 100nm gate lengths. It can be seen
that the minimum surface potential value increases with
decreasing length which is obvious due to the threshold voltage
roll-off.
Fig. 3.4 shows the variation of the front surface potential with the
position along the channel for different back gate voltages. In both
Fig. 3.3 and Fig. 3.4, the oxide thickness is fixed at 3nm and the
doping at 1018/cm3. As the back gate voltage is decreased towards
the negative direction, the back surface potential is lowered so that
the effective threshold voltage of the channel increases toward the
positive direction. It can be seen that the surface potential graphs
are very closely matched with the DESSIS simulation results
Fig 3.3: Front surface potential for the gate length of 60nm
and 100nm at the front
and the back gate voltage at 0.2V.

Fig 3.4: Variation of the front surface potential with the

change in the position
 along the channel for the back gate voltages of 0.2V
and -0.2 V.
Fig. 3.5 shows the threshold voltage roll-off for the channel length
variation from 40nm to 200nm for the oxide thickness of 3nm and
4nm and a good agreement with DESSIS is observed. The effect of
the back gate voltage on the threshold voltage is shown in Fig. 3.6
where it is visible that as Vbg is increased towards the negative
direction, the threshold voltage is increased. This is due to the fact
that as Vbg is increased towards the negative direction, the back
surface moves towards the accumulation stage so that a greater
threshold voltage is needed to invert the thin silicon film. The back
gate effect is more prominent if the body thickness is small and so
it is an attractive idea to go for thin film so as to obtain better
threshold.

Fig 3.5: Threshold voltage roll-off for two different oxide

thicknesses and a back
gate voltage of 0.2V
Fig. 3.6: Variation of threshold voltage with the back gate
voltages for the
channel thickness of 20nm and 40nm

Fig 3.7: Variation of threshold voltage with doping density

for the symmetric
 and the asymmetric DG MOSFETs. For asymmetric
DG MOSFET, the
back gate voltage is set at Vbg =-0.2V
The variation of threshold voltage with the doping concentration is
shown in Fig. 3.7 for symmetric and asymmetric DG MOSFETs. For
the asymmetric case, the back gate voltage is kept at -0.2 V so that
the effective threshold voltage is increased compared to the
symmetric one.
It can be concluded that our derived threshold voltage model
predicts the short channel effects accurately. The effect of the back
gate voltage on the threshold voltage variations for a 4-T DG
MOSFET is also noticed. The simulated results from DESSIS
approximately match with our model thus proving the accuracy of
the calculations.

3.4 SUMMARY

We have derived a concise analytical threshold voltage model for

deep submicron asymmetric DG MOSFETs by considering the
distribution of the minority carriers in the silicon channel. The 2-D
Poisson equation is solved by considering both the depletion and
the mobile charges in the thin silicon body which proves the
accuracy of the model for the both subthreshold and super
threshold operations. It has also been noticed that the threshold
voltage adjustability is more for the thin silicon channels, thus
providing more flexibility in the device designs. The sub threshold
swing of the asymmetric DG MOSFET can also be derived from our
model. If we incorporate the concept of mobility degradation in our
model its accuracy would be increased to a great extent. The
model shows a good agreement with the simulated data from
DESSIS.

REFERENCES
[1] P. H. Woerlee, M.J. Knitel, R. van Langevelde, D.B.M. Klaassen, L. F.
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 ______________
CHAPTER

4
________________

PERFORMANCE AND OPTIMIZATION OF

DUAL MATERIAL GATE (DMG) SHORT
CHANNEL BULK MOSFETs
4.1 INTRODUCTION

CMOS technology is the most dominant and promising

technology over the past decade in terms of scaling, performance,
device properties, speed and dynamic power dissipation etc.
Aggressive scaling in the nano regime leads to short channel
effects (SCE), a major concern. Different approaches such as the
channel and the gate engineering, multi-gate devices have been
proposed for controlling short channel effects [1-3].
The Dual Material Gate (DMG) devices show great promise in this
regard as SCEs get reduced by varying the length and the work-
function of two gate material aligned side by side [1]. The novel
attributes of DMG devices show improved transconductance, early
voltage, carrier transport efficiency and reduced Drain-Induced
Barrier Lowering (DIBL).In 1999, Long et al. proposed a new type of
MOSFET structure, dual-material gate (DMG) FET which employs
the gate material engineering to improve the carrier transport
efficiency and reduce the SCEs [2]. In a DMG FET, two different
gate materials with different work-functions are merged together.
For an n-channel MOSFET, the work-function of the gate material
(M1) close to the source end is chosen greater than the gate
material (M2) close to the drain end. This introduces a step
potential at the interface of the two materials. The effective
threshold voltage of the device depends on both the work function
of M1 and M2. If the work function of Metal M1 is increased further,
the effective threshold voltage of the device will increase. On the
other hand, if the work function of M2 is decreased further, the
threshold voltage will again increase due to a higher difference in
work function. A higher threshold voltage may lead to reduced on
current of the MOSFET and degrade the performance.
The length and work-function ratio of the two gate materials can
be adjusted to suppress SCEs. The surface potential is mainly
controlled by the gate voltage. When it is below the threshold
voltage, there are only a limited number of electrons injected from
the source over the barrier and collected by the drain (subthreshold
current). In case of short channel MOSFETs, the source and drain
fields penetrate deeply into the middle of the channel, lowering the
potential barrier between the source and the drain [3]. This
substantially increases the subthreshold current thereby
decreasing the threshold voltage.
In DMG MOSFETs, short channel effects are suppressed by
screening effect, induced by a step rise of the potential along the
channel. Since the drain potential variations are screened by a
higher potential under M2, the drain conductance is reduced
because of the shorter depletion region and thus increasing the
output resistance. The use of polysilicon gate electrodes results in
the reduction of the capacitive equivalent thickness (CET) of the
gate dielectric. Hence polysilicon gates have to be doped highly to
reduce the depletion width associated with it. But for sub 100nm
CMOS applications since the gate dielectric is very thin, the
dopants out-diffuse from the poly silicon to the silicon through the
dielectric. Due to presence of depletion charges on the heavily
doped gate, poly-depletion effects occurs .Therefore it is always
advisable to use metal gates which eliminates gate depletion
effects and also reduces the CET.
The conventional approach of fabrication of DMG MOSFET
requires etching of the first deposited metals exposing a thin gate
oxide resulting in reliability issues [4]. Hence an alternate method
of DMG fabrication, metal inter-diffusion was introduced [5-11].
Here the two materials with different work-functions are deposited
one after the other and selectively removed from the device. The
remaining two metals are allowed to inter-diffuse so that they form
a material with intermediate work-function eliminating the etching
of metal immediately over the gate oxide.
In this chapter, we report a systematic investigation of
performance and optimization of DMG bulk MOSFETs for
Analog/Mixed-signal applications by varying the proportion of the
two metals. The performance of a CMOS inverting amplifiers with
the n-channel device as driver and the p-channel device as the load
for optimized DMG MOSFETS is studied.

4.2 DEVICE STRUCTURE AND SIMULATIONS

A schematic cross-sectional view of an n-channel DMG bulk
MOSFET is shown in Fig. 4.1 with gate metals M1 and M2 of lengths
L1 and L2 ,where the work function of metal gate 1 (Cobalt) is
chosen higher than that of metal gate 2 (Alumunium) for n-channel
devices. The technology parameters and the supply voltages used
for device simulations are taken from the analog roadmap of
International Technology Roadmap for Semiconductors (ITRS) for
100nm gate-length devices. The doping in the p type body and n+
source/drain regions are kept at 6 X 1016 cm-3 and 5 X 1019 cm-3
respectively. Typical values of gate oxide thickness and junction
depth are 2.5nm and 30nm respectively. The performance of the
DMG device is compared with that of a single metal gate (SMG)
device by keeping the threshold voltage ( Vt ) constant. In this work,
the threshold voltage for DMG and SMG devices are fixed at 0.3V
for the n-channel and -0.3V for the p-channel MOSFETs.
 Fig 4.1: Two dimensional structure of a DMG Bulk MOSFET

4.3 PERFORMANCE AND OPTIMIZATION

A device editor, Sentaurus structure editor and device simulator
S Sentaurus device of integrated systems engineering technology
computer aided design (ISE-TCAD) are used for the realization and
the analysis of all the devices in our study. An enhanced and
précised slicer is used to observe the doping profile, the electric
field and the carrier velocity along the channel. For all the devices
explored, we have Vt adjust implant so that it is maintained
constant. The simulated results are shown for different proportion
of metal M1 and metal M2. Metal M1 with any value of Z %
automatically implies that M2 proportion is (100-Z) %.

4.3.1 Improvement of Carrier Transport

Efficiency
The variation of electrostatic potential along the channel is given
in Fig. 2(a). Due to the difference in the work-function, there is a
step rise in the potential at the interface of the two metals. When
the metal proportions are equal, the rise is maximum as shown in
Fig. 4.2(a). The difference in the work-function values of the two
gate materials in the DMG devices gives rise to an additional peak
in the lateral electric field at the interface in addition to the peak
that normally exists in the drain side of the channel in the single
metal gate (SMG) devices as shown in Fig. 4.2(b). Due to an
additional peak at the interface, the peak value of the electric field
at the drain end is reduced than the SMG devices and hence short
channel effects are suppressed in DMG devices. Moreover, the hot
electron effects are better controlled since we use bulk technology.
Fig. 4.2(c) shows the carrier velocity distribution along the channel
which plays an important role in carrier transport efficiency. It also
reveals that for equal proportion of metals, the velocity rise is
maximum at the source end as compared to the SMG devices.
(a) (b)
 (c)

Fig. 4.2: Comparison of different parameters for different lengths

in DMG n-channel
devices.
(a) Electrostatic potential along the channel at V ds = 0.8v
and Vgs = 0.1v
(b) Lateral electric field along the channel at V ds = 0.8v
and Vgs = 0.1v.
(c) Electron velocity along the channel at V ds =0.8v and
Vgs = 0.1v.

4.3.2 Short Channel Effects Suppression and the

Output Resistance

In a DMG MOSFET, the electric field discontinuity at the interface

of the two gate metals causes overall channel field flattening which
results in a larger average velocity when the electrons enter into
the channel from the source. The work function of metal M1 close
to source end should be greater than metal M2 close to drain end
so that the region under M1 has a higher threshold voltage than
the region under M2. The relation between gate voltage and
electrostatic potential is given by (1)
Vg = V fb + Φ s − Qs / Cox …. (1)
Where Vg = Gate Voltage
V fb = Difference in work function between metal and
intrinsic silicon
Φ s = Electrostatic surface potential
Qs = Total charge per unit area induced in the silicon
Cox = Oxide capacitance per unit area
So the region under the metal M1 has a lower potential than that
under ther metal M2. This results in an increase of the electrostatic
potential at the interface of the two metals. Thus the electrons in
the subthreshold condition face a higher barrier while flowing from
the source to the drain end resulting in reduced leakage current
and improved immunity to short channel effects. Higher
electrostatic potential under region M2 helps in screening the major
portion of the channel from the drain field variations and thereby
suppressing Drain Induced Barrier Lowering (DIBL).
Fig. 4.3(a) shows the peak electric field (PEF) at the drain end and
the DIBL as a function of proportion of the metals. It can be seen
that the DIBL is found to be minimum when the length of both the
metal gates are equal. This justifies the digital performance of the
device. Fig. 4.3(b) shows the variation of output resistance Ro with
the metal proportion in both subthreshold and superthreshold
regions for the p-channel devices. In this case also Ro is increased
considerably improving the gain of the device. It is to be noted that
the area factor of the p-channel device is increased three times as
the n-channel device for achieving same gain since the hole
mobility is very less compared to the electron mobility.
 (a) (b)
Fig. 4.3: (a) Plot of DIBL and Peak Electric Field (PEF) at the
Drain side as a
function of metal proportion
(b) Plot of output resistance Ro as a function of metal
proportion for both
superthreshold and subthreshold condition

4.3.3 Performance comparison in

superthreshold and subthreshold region of
operation

The different analog performance parameters for the DMG

MOSFETs in both the subthreshold and superthreshold regions are
studied in detail. Fig. 4.4(a) and 4.4(b) shows the variation of the
transconductance ( g m ) and the intrinsic gain ( g m Ro ) as a function of
the metal 1 composition for the subthreshold and the
superthreshold region. Here it is evident that g m and consequently
g m Ro are maximum when the metals proportion is 50% -50% .The
increase in the transconductance is due to the step profile and the
accelerated electron velocity near the source region.
Fig. 4.4(c) and 4.4(d) shows the variation of g m / I D with the
metal1proportion for DMG bulk MOSFETS. Since g m / I D is viewed as
the available gain per unit value of power dissipation is maximum
when the total metal length is halved. The early voltage VA is
improved which in turn increases the output resistance Ro
suppressing the short channel effects. Due to this the intrinsic gain,
g m Ro of the DMG devices is improved significantly.

(a) (b)
 (c) (d)
Fig. 4.4: Comparison of the analog performances of DMG
devices as a function of
metal proportion for subthreshold and superthreshold
operation.
(a) & (b) Plot of g m and g m Ro with metal proportion
for subthreshold
Vgs = 0.1v and Vds = 0.8v and superthreshold Vgs = 0.6v
and Vds = 0.8v
(c) & (d) Plot of gm/Id with metal proportion for
subthreshold Vgs =0.1v
and V ds = 0.8v and superthreshold Vgs= 0.6v and Vds =
0.8v
4.3.4 AC analysis of DMG devices

Fig. 4.5(a) shows the electron density in DMG devices with varying
metal proportions. It is seen that the electron density is higher at
the source side and lower at the drain side. This is due to the fact
that the region under M1 has higher threshold voltage than that
under M2. Fig. 4.5(b) shows the device gate-gate capacitances ( C gg
) as a function of the metal proportion.

(a) (b)

Fig. 4.5: (a) Plot of Electron Density as a function of the position

along the channel.
(b) Plot of total gate capacitance as a function of Vgs
(0.1v)

All the capacitances are extracted from the small-signal ac

device simulations at a frequency of 1MHz. It is seen that the C gg
value is smaller at equal proportion of metal in the DMG devices.
This is due to the concentration variation of electrons in the source
and drain regions. Another figure-of-merit, the unity-gain cutoff
gm
frequency is given by f = where Cgg is the gate-gate
T
2π C gg
capacitance. DMG devices provide higher fT in the superthreshold
region while it is limited in subthreshold region of operation. This is
due to the fact that g m is comparably higher in the former region
than the latter. Owing to lower gate capacitance at equal
proportion of metals, fT is expected to improve for that case.

4.3.5 Circuit Performance

The circuit performance of DMG devices is analysed by

investigating the parameters of a simple push-pull CMOS inverting
amplifier (Fig. 4.6(a)). In a CMOS amplifier, with n- and p-channel
devices as the driver and load, the output resistance Ro which in
turn determines the early voltage VA of the p-channel devices plays
a significant role in determining the performance of the circuit. The
width of the p-channel device ( W p ) is chosen three times the width
of the n-channel device ( Wn ) to match the subthreshold current of
both the devices.

(a) (b)

Fig. 4.6: (a) A high-gain CMOS inverting amplifier.

(b) Plot of Voltage gain as a function of metal proportion

The voltage gain of this amplifier is plotted with the metals

proportion as shown in Fig. 4.6(b). The gain is computed by
calculating the slope of the voltage transfer characteristics. The
circuit shows higher voltage gain around 50-50% proportions. The
 Vout −( g m1 + gm 2 )
voltage gain can be calculated as = . Since both the
Vin g ds1 + gds 2
transistors are driven by same input and considering the transistors
to be ideal the voltage gain is maximum. Moreover in push-pull
amplifier the voltage swing is very much limited.

4.4 SUMMARY

The different device parameters for analog applications in both the

subthreshold and superthreshold region of operation for DMG
devices and their optimization have been systematically explored.
Improvements in the drain-current, transconductance, output
resistance and voltage gain for various proportions of metals has
been observed for both n-channel and p-channel devices. The
CMOS amplifiers made with these DMG devices subsequently have
larger voltage gain than conventional single metal gate (SMG)
devices. The gate capacitances for different proportion of metals
have been explored. It is seen that the different figure of merits
tend to improve for equal proportion of metals. This is due to the
fact that electric field and electron velocity show a maximum peak
at the interface when the lengths of both the metals are equal. Also
due to maximum step rise in potential, the major portion of the
channel is mostly screened from drain field variation for this case.
Therefore in conclusion we see that DMG CMOS devices can be
very attractive for future analog and mixed signal applications. It is
also been explored that the device works best when the proportion
of metals is equal.

REFERENCES:
1. Wei Long , Haijiang Ou, Jen-Min Kuo and Ken K.Chin “Dual-Material Gate Field
Effect Transistor,” IEEE Trans. Electron Devices, Vol. 46, No. 5, May 1999.
2. Anurag Chaudhry and M.Jagdish Kumar “ Investigation of novel Attributes of a
Fully Depleted Dual-Material Gate SOI MOSFET,” IEEE Trans. Electron Devices,
Vol. 51, No. 9, Sep. 2004.
3. M. J.Kumar and A.Chaudhry, “ Two-Dimensional analytical Modeling of fully
depleted Dual-Material Gate SOI MOSFET and evidence for diminished short-
channel effects,” IEEE Trans. Electron Devices, Vol. 15, pp. 569-574, Apr.
2004.
4. X. Zhou, “Exploring the novel characteristics of Hetero-Material Gate Field-
Effect transistors with gate-material engineering,” IEEE Trans. Electron
Devices, Vol. 47, pp. 113-120, Jan 2000.
5. I. Polihchuk, P.Ranade, T. J. King and C. Hu, “Dual work function metal gate
CMOS technology using metal inter-diffusion,” IEEE Electron Device Lett., Vol.
22, pp. 444 – 446, Sept. 2001.
6. G.W. Taylor, “ Subthreshold conduction in MOSFETs,” IEEE Trans. Electron
Devices, Vol. ED-25, pp. 337 -350,1978.
7. Manoj Saxena, Subhasis Haldar, Mridula Gupta and R.S. Gupta, “Physics-
Based Analytical Modeling of Potential and Electric Field Distribution in Dual-
Material Gate MOSFET for improved Hot Electron Effect and carrier transport
efficiency,” IEEE Trans. Electron Devices, Vol. 49, No. 11, Nov. 2002.
8. R. Kaur, R. Chaujar, M. Saxena and R. S. Gupta, “Performance investigation of
50-nm insulated-shallow-extension gate-stack MOSFET,” IEEE Trans. Electron
Devices, Vol. 54, No. 2, Feb. 2007.
9. E.Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak
inversion operation,” IEEE J. Solid-state circuits, Vol. 12, No. 6, June 1977.
10. M.G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J. DeMan, “Adaptive
biasing CMOS amplifiers,” IEEE J. Solid-state circuits, Vol. 17, No.6 June 1982.
11. S.Chakraborty, A. Mallik, and C.K. Sarkar, “Subthreshold performance of
Dual-Material gate CMOS devices and circuits for ultra low power
analog/mixed signal applications,” IEEE Trans. Electron Devices, Vol. 55, No.
3, Mar. 2008.
12. International Technology Roadmap for Semiconductors, 2001 ed.
13. Integrated Systems Engineering (ISE) TCAD Manuals, 2006, Release 10.0.
 ______________
CHAPTER

5
________________

PERFORMANCE OF THE GATE ENGINEERED

SYMMETRIC DOUBLE GATE MOS DEVICES

5.1 INTRODUCTION

As the end of Semiconductor Industry Association (SIA) roadmap is

being approached, the double gate (DG) devices are considered to
be one of the most promising technologies for the future
microelectronics industry due to its excellent immunity to short
channel effects and higher drive on current. Bulk CMOS devices
scaled beyond 100nm regime gives rise to short-channel effects, a
major concern [1]-[2]. The double gate or multi gate devices
provide a better scalability option due to its excellent immunity to
short-channel effects. Among the other advantages of DG MOSFETs
are the near 60mV/dec subthreshold slope, the low Drain-Induced-
Barrier-Lowering (DIBL) and the possibility of using lightly doped or
undoped body. The use of undoped body also results in an
enhanced mobility of the charge carriers and the elimination of
statistical fluctuation of dopant concentration. Undoped DG
MOSFETS provide the flexibility of using the metal gates with near
mid-gap work-function to control the threshold voltage Vt [3]-[8].
Volume inversion is another important phenomenon that is
observed in case of multi gate MOS devices where the inversion
charges instead of being confined near the Si-SiO2 interface spread
near the center of the channel and this is more evident in the
subthreshold regime [8]. The charge carriers thus experience less
interface scattering than that of a regular bulk MOSFET. This results
in increased mobility and transconductance in double-gate devices
than the bulk CMOS transistors. Most of the researches on the
double gate devices carried out in the last few years mainly
focused on the digital applications rather than the analog/RF
applications. But the recent advancement of IC industry evinced lot
of interest on the System on Chip (SOC) applications where the
analog and the digital circuits are realized on the same chip. This
results in an increased functionality and the reduction of the size
and the cost. Along with the applications in logic designs, CMOS
technology has also started dominating the RF market also which
was previously dominated by BICMOS, BJT and the MESFET
technologies [9]-[13]. Due to rigorous scaling advantages, CMOS
has become a viable option for analog and RF applications and RF
system-on-chip. To improve the analog performance of DG
MOSFETs and also to provide better immunity to short channel
effects, various approaches such as the channel engineering using
halo implantation [14]-[17] and the gate work-function engineering
[18]-[23] have been proposed. The dual-material gate (DMG)
devices show a great promise in this regard. Dual-material gate
technology was proposed by Long et. al. way back in 1999 [18].
This so called gate work function engineering allows the use of
lightly doped or nearly undoped body resulting in reduced mobility
degradation effects in the channel and improved performance.
Very few reports of DMG devices such as subthreshold analog
performance of bulk CMOS with DMG technology had been reported
by Chakraborty et al [20]. With SOI technology rapidly emerging as
the technology for next generation VLSI, the effects of the DMG
technology on the submicron SOI devices has to be investigated. In
the recent past, the market demand for energy constrained battery
operated devices has increased tremendously. Therefore the
design of devices and circuits for such ultra low power applications
is a challenging task. Analog circuits based on the subthreshold
operations of the devices gained interest in this regard of having
the higher gain in the subthreshold regime due to the exponential
behavior of drain-current resulting in the higher transconductance
generation factor ( g m / I d ) [24].
In this chapter, a systematic investigation of the subthreshold and
the superthreshold analog performance and the RF figure-of-merits
of a gate engineered (DMG) symmetric double gate device is
explored. Different analog parameters like the transconductance (
g m ) and the transconductance generation factor for the DMG and
the SMG n-channel devices are compared. Moreover to suit RF
applications, various RF figure-of-merits such as the maximum
oscillation frequency ( f max ), the cut-off frequency ( f t ) and the gain
bandwidth product (GBW) are studied for both the devices using
extensive simulations. The circuit performance of a simple inverting
amplifier for these devices is also explored.

5.2 DEVICE STRUCTURE & SIMULATION PARAMETERS

Fig. 5.1 Cross sectional view of a DMG double gate n-channel

MOSFET with
gate source/drain under lap.
The schematic cross-sectional view of an n-channel double gate
MOSFET with dual material gate technology is shown in Fig. 5.1.
Here the gate-source under lap structure is used to minimize the
parasitic capacitance as well as to suppress the short channel
effects [25]-[26]. The technology parameters and the supply
voltages used for device simulations are according to International
Technology Roadmap for Semiconductors (ITRS) for 100nm gate
length devices [27]. In both the DMG and the SMG n-channel
devices, the threshold voltage ( VT ) is maintained at a constant
voltage of +0.355V with a drain to source voltage of 0.1V. The
threshold voltage of the DMG device is adjusted by varying the
work-function of the metal gate M1 and the metal gate M2 to
achieve the desired values. Since for n-channel devices work-
functions (W1>W2), we use 4.55ev and 4.1ev which roughly equals
the work function of Molybdenum (Mo) and Aluminium (Al). The
proportion of length of the two gate metals (L1 and L2) is kept
equal for better performance [20]. The channel thickness is kept at
20nm while the front and the back gate oxide thickness are fixed at
3nm. The body doping of both the DMG and the SMG devices is
kept practically undoped (1015/cc) to reduce the effect of mobility
degradation by impurity scattering. The gate work function of the
SMG device is fixed at 4.56eV to maintain the same threshold
voltage as that of the DMG device.
Sentaurus of ISE TCAD [28] is used for 2-D device simulation. In our
simulation, we have used the density gradient model which solves
the quantum potential equations self-consistently with the Poisson
and the carrier continuity equations. The quantum potential is
introduced to include the quantization effects in a classical device
simulation. In the density-gradient transport approximation, the
quantum potential is a function of the carrier densities and their
gradients. The analog /RF performance of both the devices are
studied with the mixed-mode simulation with a highly précised RF
extraction tool for calculating the RF figure-of merits. All the
simulations performed are calibrated with standard experimental
data. The mobility is degraded as the silicon film thickness is
reduced due to the phonon scattering, the surface roughness
scattering and the coulomb scattering.
 In our work we have considered the silicon thickness to be
20nm. In thin silicon films (<15nm) the energy bands splits into
subbands and the electrons are redistributed in these several
subbands. Thus scattering effects become dominant in such
devices. So devices with 20nm film thickness will have only
coulomb scattering as the dominant factor for mobility degradation
[29] and hence in our simulations we have included the effects of
coulomb scattering, the high-field saturation and the normal
electric field to take into account of mobility degradation.

5.3 SIMULATION RESULTS & DISCUSSION

The surface electrostatic potential of the n-channel DMG device is

shown in Fig. 5.2 for the drain-to-source voltage of Vds = 2.0 V and
the gate-to-source voltage ( Vgs ) 0.2V and 1.0V. In this figure, the
position along the channel is plotted in the X-axis direction where
“0” indicates the center of the channel. At the interface of the two
metals, a step rise of the potential occurs. This is due to the fact
that the region under metal M1 has a higher threshold voltage due
to the higher work-function of metal M1. So the effective surface
potential under the metal gate M2 increases considerably due to its
lower work-function [18]. The advantage of such a step rise in
potential lies in the fact that the drain voltage variations or the
drain fields are mostly screened by the higher potential under the
metal M2. This so called screening of the region under the metal
M1 by the metal M2 is responsible for greater immunity to the drain
induced barrier lowering.
Fig. 5.2 Comparison of electrostatic surface potential for
gate to source voltage
of Vgs = 0.2V and 1.0V and drain to source voltage of
Vds = 2.0V in DMG
and SMG double gate n-channel devices.
Fig. 5.3 Comparison of lateral electric field for DMG and SMG
double gate n-
channel MOSFETs along the channel for gate to
source voltage of
Vgs = 0.2V and 1.0V and drain to source voltage of Vds =
2.0V.
Fig 5.4 Comparison of lateral electric field for DMG and SMG
double gate n-
channel MOSFETs at the drain end for gate to source
voltage of Vgs = 0.2V
and 1.0V a drain to source voltage of Vds = 2.0V.
The lateral electric field is shown in Fig. 5.3 and a detailed view of
the pattern at the drain end of the channel is shown in Fig. 5.4
where it reveals that the peak electric field at the drain side in the
n-channel DMG device is reduced considerably compared to that of
the SMG device and there exists an additional small electric field
peak at the interface of the two metals which causes the electron
velocity to increase rapidly at the source side compared to that of
the SMG n-channel MOSFET. Reduction of the drain electric field is
obviously attributed to another cause of reduced DIBL and the hot
carrier effects [24].
A closer look at the electric field distribution at the channel-
drain junction is shown in Fig. 5.4 where the peak field is reduced
nearly by 25% in case of the DMG device compared to the SMG DG
MOSFET at Vgs =1.0V. Due to a reduced peak field at the drain end,
the DIBL of the DMG device is lower than that of the single metal
counterpart. A measure of the severity of DIBL can be defined as
follows
Vt ,lin − Vt , sat
DIBL =
Vdd − Vd , lin
(5.1)
where Vdd is the supply voltage, Vd ,lin is the linear drain voltage, and
Vt ,lin and Vt , sat are the threshold voltages in the linear and the
saturated operations respectively. The DIBL of the SMG device is
about 0.01 V/V whereas that of the DMG device is around 0.004774
V/V.
The electron velocity is shown in Fig. 5.5 which exposes the fact
that the carrier transport efficiency is greatly improved in the case
of the DMG MOSFET. Due to the sudden increase of the electron
velocity at the source side, the DMG MOSFETs are expected to
show higher carrier transport efficiency than the SMG devices. As a
result of this, the electron concentration in the channel region is
increased along with reduced DIBL and the hot carrier effects.

Fig. 5.5 Comparison of electron velocity for DMG and SMG

double gate n-
channelMOSFETs along the channel for gate to
source voltage of
Vgs = 0.2V and 1.0V and drain to source voltage of Vds
= 2.0V.

Owing to lower effective threshold voltage under the metal M2, the
electron density increases in that region simultaneously increasing
the drain current and the transconductance as explained in the
next section. Thus a DMG FET provides the advantages of reduced
DIBL as well as increased transport efficiency.

5.4 ANALOG & RF PERFORMANCE

In this section, the different analog performance parameters for

both the DMG and the SMG n-channel devices are studied. Fig. 5.6
shows the variation of drain current I d and the transconductance
g m with the gate to source voltage Vgs for a drain to source voltage
Vds = 2.0V.

Fig. 5.6 Comparison of drain current and transconductance

in the DMG and the
SMG double gate n-channel MOSFETs as a function
of gate to source
voltage Vgs for drain to source voltage of Vds = 2.0V.

It is evident from Fig. 5.6 that both I d and g m are higher in the DMG
devices compared to the SMG devices. The improvement is more
visible in the subthreshold region compared to the strong inversion
operation. The sudden increase of the electron velocity at the
source side as explained earlier hold responsible for improvement
in both I d and g m for such devices. The drain current variation with
the drain to source voltage Vds for different gate to source voltages
is shown in Fig. 5.7 where it is visible that the DMG devices exhibit
higher current than the SMG device for the same gate to source
voltage. The interesting feature about the Id-Vds curve lies in the
fact that the drain current show more flatness at saturation for the
DMG device compared to the SMG transistors. This reduced
influence of the drain to source voltage on the drain current results
in reduced depletion width in the drain-body junction thus
increasing the output resistance.

Fig 5.7 Comparison of drain current in the DMG and the SMG n-
channel
MOSFETs as a function of drain to source voltage Vds for
gate to source
voltage of Vgs = 2.0V.
Fig 5.8 Comparison of transconductance generation factor
and Early voltage for
the SMG and the DMG n-channel MOSFETs as a
function of gate to
source voltage Vgs for drain to source voltage Vds =
2.0V.
Another important parameter for judging analog performance
is the transconductance generation factor (TGF) ( g m / I d ). This
parameter is viewed as the available gain per unit power
dissipation. As shown in Fig 5.8, the TGF for the DMG devices is
lower than the SMG devices in the subthreshold regime. This should
not affect the performance much in the subthreshold regime, since
the power dissipation is much less in that regime. Above the
threshold voltage, the difference between the two reduces
distinctly.
The early voltage variation is also shown in Fig. 5.8 where the
DMG device exhibits comparatively higher early voltage than the
SMG counterpart in the low gate voltage regime. The output
resistance of a MOS transistor at any Vgs is evaluated as
Ro = Va / I D
(5.2)
where VA and I D are the early voltage and the saturated drain
current at that particular Vgs .

Fig. 5.9 Comparison of output resistance Ro and intrinsic gain

(gmRo) for the
SMG and the DMG n-channel MOSFETs as a function of
gate to source
voltage Vgs for drain to source voltage Vds = 2.0V.
The output resistance ( Ro ) variation with the gate to source voltage
is shown in Fig. 5.9 where the DMG devices demonstrate a
considerable increase of Ro. The intrinsic gain which is product of
the transconductance and the output impedance is also shown in
the same figure. The DMG devices exhibit substantial increase of
the gain in the low gate voltage regime. The DMG devices are thus
expected to perform better in case of subthreshold analog
applications compared to the SMG devices.
The RF performance trends of DMG devices will be studied in this
section. The different RF figure-of-merits (FOM) such as the cutoff
frequency ( f t ) and the maximum oscillation frequency ( f max ) are
explored. Cut-off frequency is the frequency when the current gain
is unity. Maximum oscillation frequency is the frequency when the
power gain is unity and can be extracted by the Mason’s gain
formula [14]. The approximate values of f t and f max are shown in
equation (5.3) and (5.4)
gm
fT ≈ (5.3)
2.π. C gg
gm
f max ≅
C (5.4)
2π C gs 4( Rs +Ri +Rg)( g ds + gm ) gd
C gs
where Cgs and Cgd are the gate-to-source and the gate-to-drain
capacitance respectively, g m and g ds are the transconductance and
the output conductance, C gg is the total gate capacitance ,Rg, Rs
and Ri are the gate, source and channel resistance respectively.
So it is obvious that both the figure-of merits are greatly
influenced by geometrical parameters. In the 2-D device simulator,
ac analysis is performed over a frequency range and the Y
parameters are computed. Then an advanced two port network RF
extraction tool is used to generate the different RF-FOMs using the
equations (3) and (4).

f t = f 0 .H 21 (5.5)
Y21 −
Y12 2

f max =
f0 . (5.6)
4[Re( Y)R
11 e( Y)22 Re( −Y)R
12 e( Y)]
21
Fig. 5.10 Comparison of different capacitances in the SMG and
the DMG n-
channelMOSFETs as a function of gate to source
voltage Vgs at drain to
source Voltage of Vds = 2.0V.

Fig. 5.11 Comparison of gate to drain capacitance in the SMG

and the DMG n-
 Channel MOSFETs as a function of gate to source
voltage Vgs at drain
to source voltage of Vds = 2.0V.
The different capacitance variations are shown in Fig. 5.10 and
5.11. Due to the lower work-function of the metal M2, the electron
density is increased near the drain end in case of the DMG device.
The gate to drain capacitance ( C gd ) is slightly increased for DMG
transistor compared to the SMG counterpart as shown in Fig. 5.11.
The enhancement becomes prominent for low drain to source
voltage of 1.0V. Due to the similarity of metal M1 of the DMG
device and the gate metal of the SMG transistor, the gate to source
capacitance ( C gs ) is more or less same for both the devices under
consideration. The total gate capacitance being the sum of C gs and
C gd shows more or less equality with slight increase in the strong
inversion regime due to the effect of increased C gd . So the DMG
devices with more or less equal gate capacitance and the increased
transconductance provide an increased cut-off frequency.
Fig. 5.12 shows the cut-off frequency versus the gate to source
voltage Vgs that reveals the increased cut-off frequency of the DMG
devices compared to the SMG devices. The maximum frequency of
oscillation for the DMG and the SMG devices for different drain to
source voltage is shown in Fig. 5.13. As seen from equation (5), the
gate to drain capacitance plays a major role in determining f max .
Fig. 5.12 Comparison of cut-off frequency as a function of gate
to source
voltage Vgs for the SMG and the DMG devices at drain
to
source voltage of Vds = 2.0V and 1.0V.

Fig. 5.13 Comparison of maximum frequency of oscillation

computed as a
 function of gate to source voltage Vgs for the SMG and
the DMG devices
at drain to source voltage of Vds = 2.0V and 1.0V

Another important parameter is the gate resistance Rg . The

use of metal gates results in reduced gate resistance. To get f max
the gate resistance is accounted for in the simulations itself. This
was done by modifying the parameter for the metal which is used
as gate in the device. The resistivity of the metal was chosen to be
5.2 ×10−6 Ω − cm which corresponds to Molybdenum material which is
a potential candidate for future metal gate technologies. Normally
f max varies with thickness of the gate electrode. Since the total gate
resistance consists of distributed gate electrode resistance and the
channel induced gate resistance, f max was obtained by converting
the admittances and capacitances obtained from ac simulations to
H- parameters, by post processing using ‘Inspect’. Owing to the
higher gate to drain capacitance at strong inversion, the maximum
frequency of oscillation of the DMG devices is more or less equal to
that of SMG devices with slight degradation at high gate voltages.
Fig. 5.14 Comparison of the Gain Bandwidth Product for a dc
gain of 10
computed for the SMG and the DMG n-channel
MOSFETs at drain to
source voltage of Vds = 2.0V and 1.0V.

Another important parameter for evaluating RF performance is the

gain bandwidth product (GBW) for a certain dc gain ( f A ). For a dc
gain of ten, it is given by (8)
gm
fA ≈ (5.7)
2. π
.10. C gd
The GBW for a dc gain of 10 is shown in Fig. 5.14. Due to slightly
higher electron density at the drain side of the DMG devices, the
gate to drain capacitance should be slightly higher than the single
metal counterpart. But the higher transconductance of the DMG
devices results in an increased GBW as seen in Fig. 5.14.
5.5 CIRCUIT PERFORMANCE

Fig. 5.15 Comparison of voltage gain of a simple inverting

amplifier with SMG
and DMG n-channel MOSFETs as a function of the
load resistance RLoad
for an output voltage of Voutput=VDD/2=1.0V

Finally, an inverting amplifier is simulated using varying load

resistance with both the DMG and the SMG n-channel MOSFETs and
the voltage gain is obtained by measuring the slope of the input-
output characteristics calculated at an output voltage of 1.0V . An
increase of around 13% is observed in the case of the DMG n-
channel MOSFETs compared to the SMG counterpart as shown in
Fig. 5.15

5.6 SUMMARY

In this paper, we have explored the analog and RF performances of

a symmetric Double Gate MOSFETs implemented with Dual Metal
Gate technology (DMG) both in the subthreshold and super-
 threshold regime of operation. The surface potential and the lateral
electric field clearly reveal the fact that DMG devices are better
immune to the short channel effects especially to the drain induced
barrier lowering (DIBL). An increased electron velocity at the source
end explains the higher carrier transport efficiency of the DMG
transistors. Various analog parameters like the drain current, the
transconductance; the transconductance generation factor, the
early voltage, the output resistance and the intrinsic gain of the
DMG devices are studied and compared with the SMG counterpart.
The circuit performance of a simple inverting amplifier with
varying load resistance also proves that the DMG devices are
superior to the SMG devices. The different RF FOMs also seems to
improve for DMG devices both in the superthreshold as well as in
the subthreshold regime. So it is concluded that the Double Gate
MOSFETs with the Dual Metal Gate technology will be very much
favorable for future analog and RF applications as well as low
power subthreshold analog circuits.

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 ______________

CHAPTER

6
______________

INFLUENCE OF THE CHANNEL AND THE

GATE ENGINEERING ON THE ANALOG AND
RF PERFORMANCE OF DG MOSFETs

6.1 INTRODUCTION
Over the past decade, silicon-on-insulator (SOI) technology
has proved itself to be of major importance in the MEMS industry
and has brought new functionality for the microelectronic
applications, radiation-hard, high voltage circuits or low voltage
and low consumption ICs, realized with partially/fully depleted
single and double gate (SG and DG) MOS devices [1]-[5]. DG SOI
devices are promising candidates for low-power low-voltage
applications as they exhibit steeper subthreshold slope, better
immunity to the short channel effects, volume inversion, the higher
drain current and the larger transconductance as compared to the
SG SOI devices. Moreover they show high tolerance to harsh
environments such as extreme temperature and radiative
conditions [6]–[13]. Although DG devices are classically projected
to be the ultimate structures for deep submicron MOS devices, long
channel DG devices would be extremely useful for high
performance analog applications such as high gain bandwidth
operational transconductance amplifiers (OTAs), MEMS (sensors
such as accelerometers with low output signals), current mirrors
and precision analog applications. Furthermore, MEMS utilizing
micro scale process and surface micromachining are fully
compatible with the DG technology, thus allowing easy integration
for very high gain applications.
Recently, the laterally asymmetric channel devices (also
known as graded channel (GC)) have been proposed by several
authors [14]-[16] both in bulk and the SOI MOSFETs to overcome
severe problems of the hot electron degradation, the threshold
voltage roll-off, analog performance reduction and parasitic bipolar
effects, exhibited by uniformly doped (UD) SG and DG devices.
In this chapter, a detailed investigation is carried out with
lateral asymmetric halo doped DG MOSFETs in the 100nm regime
for superior analog and RF performances. The optimization of the
halo length and the doping concentration is shown with detailed
simulation results. In the next section, a comparative analysis is
carried out between the gate engineering Dual Metal Gate
technology and the channel engineering HALO doped technology
implemented on an undoped symmetric DG MOSFET for the logic,
the analog and RF applications. For digital applications, the goals
are to maximize the I on / I off current ratio and minimize the delay
factor, whereas for analog and RF application, we need to improve
the output resistance, the intrinsic gain, the g m / I D ratio and the
cut-off frequency. All these above parameters are studied in details
with the help of a 2-D device simulator Sentaurus TCAD and a
comparison is made between the channel and the gate engineering
techniques for superior performance.

6.2 GRADED CHANNEL IN SOI/DG MOSFET

From the analog circuit design point of view, the enormous
potential provided by the FD SOI MOSFETs due to their larger
transconductance over drain current ratios has been demonstrated
in operational amplifiers and current mirrors. In a conventional SOI
MOSFETs however, the body (channel) region is normally
electrically floating, which reduces the drain breakdown voltage,
due to the so called floating body effect as discussed in chapter 2.
Such a problem is exacerbated at low gate voltages, decreasing the
output impedance and early voltage, which degrades the transistor
analog performance. The graded-channel (GC) SOI n-MOSFET is an
asymmetric channel device which has been introduced to minimize
the inherent parasitic bipolar effects of the SOI transistors (Fig.
6.1).

Fig. 6.1: Cross-section of a Graded Channel SOI n-

MOSFET.

An undoped region is preserved in the drain side of the

channel, i.e. the threshold voltage ion implantation is not
performed in this region. Such undoped region presents negative
threshold voltage and can be considered as an extension of the
drain region (through the inversion layer) below the gate. Thus, in a
first approximation, the device effective channel length ( Leff ) can
be estimated as the difference between the mask gate length ( L )
and the length of the undoped region ( LLD ). Previous results
showed that drain breakdown voltage and the single-transistor
latch are pushed to larger drain bias. GC transistors also present
significantly larger transconductance and reduced drain
conductance [14]. The combination of these characteristics
indicates the tremendous potential of this device for analog
applications [16].

6.3 FABRICATION OF THE GC DG MOSFET

Numerous reports are available in literature regarding the
fabrication of the graded channel SOI MOSFETs. As reported in [15],
the conventional FD and GC SOI n-MOSFETs were simultaneously
fabricated on p-type smart cut wafers featuring an initial boron
concentration of about 1015 cm-3. The initial 200 nm thick silicon
film was reduced by the oxidation and the strip process down to
100 nm. Semi recessed LOCOS was used to isolate the devices.
After the growth of a 30 nm thick gate oxide, the threshold voltage
ionic implantation was performed using photolithography to adjust
the position of this implantation along the channel in the GC
devices and keep the region near the drain at natural wafer doping.
It is important to point out that this photolithographic step was
performed when simultaneously masking the p-type devices to the
n-type threshold voltage ionic implant in a full CMOS processing,
such that no additional step has to be included. After the gate
patterning, the source and the drain regions are formed by arsenic
ionic implantation and thermal annealing. Conventional FD devices
with Lightly Doped Drain (LDD) structure were also fabricated in a
separate wafer through a phosphor ionic implantation followed by a
0.15 µ m spacer length definition before the source/drain
formation. Source/drain nickel silicidation was used on LDD
devices.
Fabrication of the DG devices with the halo doped regions or
the graded channel was also reported in [16] where the starting
material is a p-type UNIBOND material with the concentration of
about 1015cm-3. The mains steps are to etch the oxide on the
sidewalls of the silicon islands as well as in the buried oxide and a
cavity is created underneath the centre part of the silicon islands.
Gate oxide was grown over the exposed silicon and boron was
implanted to adjust the threshold voltage and polysilicon gate
material was deposited and doped n-type.
Despite the complex fabrication process for the short channel
DG devices, the long channel laterally asymmetric DG devices are
relatively easier to fabricate. Ionic implantation was carried on the
source side and a part of the length ( LLD ) at the drain was masked
in graded channel devices (GC) devices, thus preserving the
natural wafer doping. The GC SOI process is fully compatible with
fully depleted SOI MOSFET process flow, with no additional process
steps needed. The threshold voltage implanted region presents a p-
type doping level of about 1017 cm-3.
6.4 OPTIMIZATION OF THE LENGTH AND THE
DOPING CONCENTRATION IN DG HALO
MOSFETS
In a DG-MOSFET, due to very thin channel thickness, the
volume inversion occurs [17]. So the halo implant is placed near
the source end over the full channel thickness as proposed in [16]
(Fig. 6.2). One important aspect of the halo doped architecture is to
identify optimum value of the halo doped length and the doping
concentration. A small length of the halo doped region will need a
high doping for the adjustment of the threshold voltage and would
result in degradation of the performance due to higher mobility
degradation by the Coulomb’s scattering. Again a higher length of
the doped region may be not sufficient to minimize the depletion
width, thus degrading the output resistance due to channel length
modulation.

Fig. 6.2: Cross Section of a Double Gate MOSFET with Graded

Channel.

For this optimization work, we have taken four n-channel DG

MOSFETs with different halo doped lengths namely 5nm, 20nm,
30nm and 50nm. Correspondingly the doping concentration is
adjusted to maintain the same threshold voltage of the four devices
under consideration. The DIBL values of the four devices are shown
in Fig. 6.3 where the halo doped lengths around 20nm or 30nm
shows the minimum value. Fig. 6.4 shows the transconductance
generation factor g m / I D where it is visible that the device with halo
doped length of 20nm shows a slight decrease of the value in the
subthreshold regime compared to the other devices. But with the
increase of the gate voltage, the devices with halo lengths of 5nm
results in the degradation of g m / I D due to charge sharing effect in
short channel devices, which increase the body factor.

Fig. 6.3: Comparison of the DIBL factor for n-channel DG

MOSFETs with
different lengths of the halo doping.
The Early voltage is plotted as a function of the gate to source
voltage for a drain voltage of 2.0V where the device with 20nm
halo doped region shows the highest value (Fig. 6.5). The output
resistance of a MOS transistor at any Vgs is evaluated as
Ro = Va / I D (6.1)
where VA and I D are the early voltage and the saturated drain
current at that particular Vgs . The output resistance and the intrinsic
gain ( g m Ro ) are shown in Fig. 6.6 where it is visible that the 20nm
halo doped device show the best performance among the other
devices.
 Thus it is concluded that for the 100nm channel length, halo
doped length of 20nm is the optimum value for better analog
performances. In the halo implanted DG structure, the pocket
implantation is set at 7.91 × 1017 cm-3 to obtain the threshold voltage
of 0.3V at a drain voltage of 0.1V.

Fig. 6.4: Comparison of the gm/Id for n-channel DG MOSFETs with

different lengths
of the halo doping for drain voltage of V ds= 2.0V as a
function of the
normalized drain current
 Fig. 6.5: Comparison of the Early voltage for n-channel DG
MOSFETs with
different lengths of the halo doping for drain voltage
of Vds= 2.0V as a
function of the gate to source voltage.

Fig. 6.6: Comparison of the gmRo for n-channel DG MOSFETs with

different lengths of the halo doping for drain voltage of Vds=
2.0V.
Single Metal Double Gate (DG) MOSFET
The main advantage of DG MOS devices is the possibility of the use
of undoped body without much concern of the short channel
effects. With the double gate architecture, the effective gate
control is increased so that Vt -roll off or DIBL is controlled to some
extent compared to that of the bulk CMOS technology. Use of
undoped body also results in reduced mobility degradation by
Coulomb scattering thus increases the on-current considerably. As
reported in [17], the threshold voltage of a DG MOSFET depends
solely on the work-function of the gate metals. In the DG MOSFET
under consideration, the silicon film is kept practically undoped
(1015cm-3) and the gate work-function is fixed at 4.577eV to obtain
the threshold voltage of 0.3V at a drain voltage of 0.1V.

Dual Metal Double Gate (DM-DG) MOSFET

Fig. 6.7 Cross-sectional view of DG MOSFET with dual material

gate technology
The schematic cross-sectional view of DG MOSFET with the dual
material gate technology is shown in Fig. 6.7. The DMG architecture
calls for the optimization of two parameters viz.
1. Ratio of the length of the metals M1 and M2 (L1/L2 ratio)
2. Optimum work-function difference of the metal M1 and M2
As reported in [18], the optimum ratio of the gate metal lengths, L1
and L2, for both the logic and analog applications is L1/L2=1. With
equal gate lengths of metal M1 and M2, the reduced DIBL and the
off current along with increased transconductance and intrinsic
gain are obtained. Also from the photolithographic point of view,
the fabrication of DMG technology with equal gate lengths of M1
and M2 is much more feasible.
The change in the work-function of M1 and M2 results in
considerable deviation of the performance from the optimum. The
increase of the work-function difference results in the increase of
the threshold voltage so that the on-current as well as the off-
current decreases. Increase in the work-function difference results
in increase of the potential step at the interface of the two metals
along the channel. This may lead to higher output impedance but
the higher threshold voltage results in decrease of the
transconductance. Also higher threshold voltage may not be
feasible for sub-100nm devices. It was concluded in [18] that a
work-function difference of 0.4eV is the optimized value for
superior analog performances. In our work, the work-function of the
metal M1 and M2 are 4.55eV and 4.1eV respectively with equal
lengths of L1 and L2 and a threshold voltage of 0.3V at a drain
voltage of 0.1V is obtained.

6.5PERFORMANCE ANALYSIS OF CHANNEL

AND GATE ENGINEERED DG MOSFET
In this section, a systematic comparison is carried out
between the channel engineered DG MOSFET (HALO-DG) and the
gate engineered DG MOSFET (DM-DG) for logic, analog & RF
applications. The surface potential along the channel length for the
DG, DM-DG and HALO-DG n-channel MOSFETs for the gate voltage
of 0.3V and 2.0V at a drain to source voltage of 2.0V is shown in
Fig. 6.8. In this figure, the position along the channel is plotted in
the X-axis direction where “0” indicates the center of the channel.
The DM-DG MOS transistor shows a step potential profile at the
interface of the two metals along the channel. The HALO-DG MOS
transistor shows a small increase of the potential starting at the
interface of the halo doped portion and the silicon channel due to
abrupt change of the doping profile compared to the conventional
DG MOSFET. It is clearly visible that the DM-DG technology
provides a larger increase of the potential so that the major portion
of the channel is shielded from the drain voltage variations
compared to the other two devices.
The lateral electric field profile at the surface is shown in Fig.
6.9 for the gate voltage of 0.3V and 2.0V at a drain to source
voltage of 2.0V. The step increase of the surface potential in the
case of the DM-DG devices results in an additional electric field
peak at the interface in addition to that exists at the drain end. In
contrast, the halo doped DG MOS device exhibiting a smaller
increase of the surface potential at the abrupt doping profile
junction shows a comparatively smaller electric field peak at the
respective junction.

Fig. 6.8 : Comparison of the electrostatic surface potential for

n-channel DM-DG,
HALO-DG and conventional DG MOSFETs in weak and
strong inversion
for drain voltage of Vds= 2.0V.
 These additional peaks due to the gate or the channel
engineering techniques reduce the effective field at the drain end is
comparatively reduced resulting in a smaller drain induced barrier
lowering and hot carrier effects, a major effects in case of the short
channel MOS devices.
It is seen that for DM-DG MOS devices, the electric field
discontinuity at the interface of two gate metals causes channel
field flattening which results in larger average velocity when the
electrons enter the channel from the source. The nature of electron
velocity for the gate voltage of 0.3V and 2.0V at a drain to source
voltage of 2.0V shown in Fig. 6.10 is very much similar to electric
field so that the average velocity is increased along the channel in
case of the gate and the channel engineering devices compared to
that of the conventional DG MOS transistors. But in the halo doped
n-channel devices, the peak in electric field is observed near the
source end, simultaneously increasing its average velocity
compared to that of the gate engineering technique. The gate
engineering technique in contrast provides an increase of the
electron velocity at the centre of the channel compared to that of
the halo doped DG MOS transistor. It is indeed evident that the
increase of the electron velocity along the channel in both the
engineering techniques is more prominent incase of the weak
inversion regime i.e. for gate voltage of 0.3V compared to that of
the superthreshold regime. Thus the increased carrier transport in
both the gate and the channel engineering will provide more
advantage in case of the subthreshold regime.
 Fig. 6.9: Comparison of the electric field for n-channel DM-
DG, HALO-DG and
conventional DG MOSFETs in weak and strong
inversion for drain
voltage of Vds= 2.0V.

Fig. 6.10: Comparison of the electron velocity for n-channel DM-

DG, HALO-DG
and conventional DG MOSFETs in weak and strong
inversion for drain
 voltage of Vds= 2.0V.

Digital Performance
For Digital applications, according to ITRS specification for
100nm devices, the supply voltage is chosen to be 1.2V [19]. The
different parameters for comparing the digital performance are the
DIBL, the on-off current ratio and the delay. The DIBL co-efficient is
computed as
V −V
DIBL = t ,lin t , sat (6.2)
Vdd − Vd ,lin
where Vt ,lin and Vt , sat are the threshold voltages measured at
the linear and saturation region for drain voltages of 0.1v and 1.2V
respectively. The on-current refers to the drive current in the
saturation, while off-current refers to the total leakage current,
which is the sum of the subthreshold, the gate, and the junction
leakage currents. The delay is a measure of the speed of the device
and is measured as
C ×V
τ = gg dd (6.3)
I on
where C gg is the total gate capacitance at the supply voltage, Vdd is
the supply voltage and I on is the on current of the MOS device
under consideration. The different parameters are shown in table
no. 6.1 for the three n-channel devices under consideration.
Table 6.1: Logic performance parameters of DG, HALO-DG & DM-
DG MOSFETs
DIBL Ioff (A/ µ Ion (A/ µ Ion/ Ioff ( Delay
(mV/V) m) m) × 10-8) (ps)
DG 6.331 4.969 × 10 1.247 × 10 0.25099 2.5742
MOSFET -11 -3

HALO-DG 3.4602 7.961 × 10 1.202 × 10 0.1509 2.6461

MOSFET -11 -3
1
DM-DG 1.2434 6.465 × 10 1.322 × 10 0.2044 2.4452
MOSFET -11 -3

Due to the existence of a secondary electric field peak along

the channel in case of the gate or channel engineered DG MOS
devices, the electric field at the drain end is reduced considerably
resulting in reduced DIBL effects. The DIBL of DMDG devices is the
lowest than the other two devices because of the higher secondary
electric field peak at the interface of the two metals. The current in
the weak inversion regime of the DM-DG or HALO doped DG
MOSFETs is slightly increased compared to that of the conventional
DG MOSFETs due to higher carrier transport efficiency making them
more applicable for the subthreshold analog applications. The on
current in case of the DM-DG devices is the highest while it
degrades severely in the case of the HALO-DG devices due to the
mobility degradation at strong inversion. The on-off current ratio is
highest in case of the conventional DG MOSFETs with slight
degradation in the case of the DM-DG MOSFETs. The delay being
dependent on the gate capacitance and the on current is lowest in
case of the gate engineered architecture. It is shown in the next
section that the three devices under consideration do not show
much change in the total gate capacitance, the delay factor is
mostly dependent on the on current. The halo doped device
showing severe degradation of the on current results in increased
delay factor compared to that of the other two MOS devices. The
halo doped DG MOSFET shows a degradation of the performance in
strong inversion regime and thus delay factor is reduced
considerably. The gate engineered DG MOS transistor exhibits a
slight degradation of the on-off current ratio compared to that of
the conventional DG MOSFET but the delay factor is the minimum
amongst all due to maximum on-current.
Analog Performance
The different analog performance parameters like the
transconductance g m , the Early voltage, the transconductance
generation factor g m / I D and the output resistance Ro are studied in
this section. It can be seen from Fig. 6.11 that both g m and I D in
DM-DG devices are greater than the single metal counterpart. The
transconductance of halo doped DG MOS device degrades severely
as the gate voltage increases due to considerable reduction of the
mobility along the channel. The output characteristics of the three
MOS devices for different gate to source voltages is shown in Fig.
6.12 where it is evident that the gate engineering technique with
reduced effect of the drain field shows more independency of the
drain voltage at saturation.

Fig. 6.11: Comparison of the drain current and transconductance

for n-channel DM-
DG, HALO-DG and conventional DG MOSFETs as a
function of the gate
to source voltage for drain voltage of Vds= 2.0V.
 Fig. 6.12: Comparison of the drain current for n-channel DM-DG,
HALO-DG and
conventional DG MOSFETs as a function of the drain
voltage for
different gate voltages.

This architecture also shows increased drain current

compared to the other two due to higher carrier transport
efficiency. The halo doped DG MOSFET on the other hand shows
reduced drain current compared to that of the conventional one.
Another parameter to be mentioned is g m / I D which is viewed
as the available gain per unit value of power dissipation and is
shown in Fig. 6.13. In subthreshold region, its value is more or less
equal for HALO-DG and the DM-DG devices but is much more in
case of the conventional DG MOS transistor. At moderate inversion,
the DM-DG device shows considerable improvement and follows
the conventional one.

Fig. 6.13: Comparison of the transconductance generation

factor (gm/Id) for n-
channel DM-DG, HALO-DG and conventional DG
MOSFETs as a
function of the normalized drain current for drain
voltage of Vds= 2.0V.
 At strong inversion, g m / I D in all the three devices matches
with each other. The slight degradation of the g m / I D ratio in the
subthreshold regime for the gate or the channel engineering
technique may not be an important drawback because power
consumption in the subthreshold regime is very less [20]. The Early
voltage of the three n-channel devices is shown in Fig. 6.14
illustrating the fact that the gate engineered devices are superior
than the halo doped devices and the conventional DG MOSFET.
The output resistance and the intrinsic gain of the three
devices are shown in Fig. 6.15 as a function of the gate to source
voltage where it is visible that gate and channel engineering show
higher output resistance compared to conventional DG MOS device.
The intrinsic gain of both the gate and the channel engineering
techniques exhibits comparatively higher gain than the
conventional one, the performance being more prominent in the
subthreshold regime. The halo doped device shows a reduction of
the gain at higher gate voltage and the difference in performance
compared to the conventional one is minimized in the strong
inversion regime.
Fig. 6.14: Comparison of the Early voltage for n-channel DM-
DG, HALO-DG and
conventional DG MOSFETs as a function of the gate
to source voltage
for drain voltage of Vds= 2.0V.

Fig. 6.15: Comparison of the output resistance (Ro) and

intrinsic gain (gmRo) for n-
channel DM-DG, HALO-DG and conventional DG
MOSFETs as a
function of the gate to source voltage for drain
voltage of Vds= 2.0V.

RF Analysis
In this section, we focus on the intrinsic RF performances of
the gate and channel engineered DG MOSFETs. Cutoff frequency
(fT) and the maximum frequency of oscillation (fmax) are two
important parameters for evaluating the device potentials for RF
applications. The Cut-off frequency (fT) [18] is the frequency when
the current gain is unity, while fmax is the frequency when the power
gain is unity. The approximate values of fT and fmax are shown in
equation (3) and (4)
gm
fT ≈ (6.4)
2.π .C gs
 gm
f max =
C (6.5)
2π C gs 4(Rs + Ri + Rg )(g ds + g m gd )
C gs
where C gs and C gd are the gate-to-source and gate-to-drain
capacitance respectively. gm and gds are the transconductance and
the output conductance, C gg is the total gate capacitance, Rg , Rs
and Ri are the gate, source and channel resistance respectively. So
it is obvious that both the figure-of merits are greatly influenced by
geometrical parameters. In the 2-D device simulator, ac analysis is
performed over a frequency range and the Y- parameters are
computed. Then an advanced two port network RF extraction tool is
used to generate the fT and the f max .
f t = f 0 . H 21 (6.6)
Y21 − Y12 2

f max = f0 . (6.7)
4[Re(Y11 ) Re(Y22 ) − Re(Y12 ) Re(Y21 )]
where f 0 is the applied frequency.

Fig. 6.16: Comparison of the electron density for n-channel

DM-DG, HALO-DG
 and conventional DG MOSFETs for drain voltage of
Vds= 2.0V and gate
to source voltage of Vgs=0.3V.

The intrinsic gate capacitances represent an important parameter

in case of RF applications. All the capacitances are extracted from
the small signal ac device simulations at a frequency of 1MHz. In
Fig. 6.16, the electron density along the channel is shown for
Vgs=0.3V and Vds=2.0V for all the devices. The electron density at
the source end is considerably less compared to that at the drain
end in case of DM-DG device. This is due to the fact that the
channel at the source side is having a higher threshold voltage due
to higher work function material at the source side. The HALO-DG
MOS device exhibits reduced electron concentration along the
channel after the abrupt halo doped junction.
Fig. 6.17 and Fig. 6.18 shows the gate to source ( C gs ) and the
gate to drain capacitances ( C gd ) for the linear ( Vds =50mV) and
saturation regime ( Vds =2.0V) as a function of the gate to source
voltage. As is evident, the gate to source capacitance of all the
three devices is more or less equal in the saturation region. In the
linear region above threshold voltage, the halo doped DG MOSFET
shows a slight reduction of the capacitance.
 Fig. 6.17: Comparison of the gate to source capacitance for
n-channel DM-DG,
HALO-DG and conventional DG MOSFETs as a
function of the gate
to source voltage for drain voltage of Vds= 2.0V
and 50mV.

Fig. 6.18: Comparison of the gate to drain capacitance for n-

channel DM-DG,
HALO-DG and conventional DG MOSFETs as a
function of the gate
to source voltage for drain voltage of Vds= 2.0V and 50mV.

Fig. 6.18 reveals that the gate to drain capacitance of the gate and
the channel engineered DG devices is greater than that of the
conventional one; the difference is less in saturation region. The
larger values of C gd in case of the halo doped device results from
capacitance coupling between drain and gate electrode. The cause
of the same effect in case of the DM-DG device is that the effective
threshold voltage under M2 is lower due to reduced gate work
function as a result of which the electron concentration is higher
near the drain end. For typical analog applications, the transistor
operates in saturation with reduced gate voltage overdrive [22]. In
both the figures, it is clearly visible that for Vds =2.0V, both the
capacitance C gs and C gd for the three devices are approximately
equal for gate voltage around 1.0V.

Fig. 6.19: Comparison of cutoff frequency for n-channel DM-

DG, HALO-DG
and conventional DG MOSFETs as a function of
the drain current
for drain voltage of Vds= 2.0V.

The resulting cut-off frequency which depends on the ratio of

transconductance and gate capacitance is highest for the DM-DG
device as shown in Fig. 6.19. The halo doped DG MOSFET although
showing slightly reduced gate capacitance exhibits decreased cut-
off frequency due to severe degradation of the transconductance at
strong inversion. At a drain current of 300 µ A / µ m , the DM-DG device
shows a 21.6% increase in cut-off frequency than the conventional
DG MOSFET as shown in fig. 12. In determining the maximum
oscillation frequency, the gate resistance plays an important role
and needs to be added to the intrinsic MOSFET core model to
predict the device behavior at high frequency. The effective gate
resistance consists of two parts: the R e ltd contributed by the
distributed gate electrode resistance and the distributed channel
resistance due to NQS effect ( R nqs ). It has been shown earlier that
the NQS effect becomes more significant in the case of longer
channel lengths [37]. So we have excluded R nqs from our
simulation. The gate electrode resistance is given by
Rg s,q W
Reltd = (6.8)
3 L
where Rg,sq is the sheet resistance of the gate material, W is the
width of the device, and L is the length of the channel region. In our
simulation study, the gate material for HALO-DG and single metal
DG MOSFETS is taken as Molybdenum with a resistivity of
5.2 ×10−6 Ω − cm and the gate electrode height is 20nm. So the gate
sheet resistance equals to 2.6Ω / sq and for a width of 10 µ m , the gate
electrode resistance comes out to be around 87Ω . Based on typical
source/drain contact resistivity [38] of 4Ω − µ m 2 , the contact
resistance is taken as160Ω . Determination of the electrode gate
resistance in case of the gate engineered DG MOSFET is very
difficult as the gate is composed of two different metals aligned
side by side. Evaluation of fmax for DM-DG devices is carried out in
two different ways.
The first technique assumes the same gate electrode
resistance as that of DG or HALO-DG MOSFETs. Here it is justified
that the variation in Rg for DM-DG devices will be nullified by the
high transconductance and lower output conductance. The second
approach is based on the assumption that the effective gate
electrode resistance is a parallel combination of two different
electrode resistances based on the resistivities of the two
respective metals Molybdenum and Aluminium as shown in Fig.
6.20(a). Here we have neglected any effect of the contact
resistance between two metals for DM-DG architecture. f max for the
three devices is shown in Fig. 6.20(b) where the second approach
of f max determination of the DM-DG device is termed as “ DM-DG
( Theoretical)”. As is evident, the peak fmax occurs at 200 µ A / µ m
and is highest for gate engineered DG devices. A HALO-DG device
shows degradation of f max due to lower transconductance. The
reduced drain conductance of the DM-DG MOSFET is another
important factor for highest f max among all. f max of DM-DG devices
calculated from a theoretical point of view is increased further due
to lower value of the gate resistance ( 30Ω ). The f max / fT ratio for
DG, HALO-DG and DM-DG MOSFETs are evaluated as 1.85, 1.90 and
1.83 respectively while that of DM-DG device by theoretical
approach is 2.

(a)

(b)
 Fig. 6.20 (a) Gate Resistance architecture in DM-DG MOSFETs (b) Comparison of
maximum oscillation frequency for n-channel DM-DG, HALO-DG and
conventional DG MOSFETs as a function of the gate to source voltage
for drain voltage of Vds = 1.0V.

Another important parameter for evaluating RF performance is the

gain bandwidth for a certain dc gain (fA). For a dc gain of ten, it is
given by (6.9)
gm
fA ≈ (6.9)
2.π.10. C gd
From Fig. 6.21, it is evident that the DM-DG and the conventional
DG devices show improved gain bandwidth for low gate overdrive
voltages. The DM-DG device exhibits degraded performance at
strong inversion due to increased gate to drain capacitance in this
regime. The halo doped DG device although showing least gate to
drain capacitance exhibits lowest GBW product owing to
degradation of transconductance. The conventional DG MOSFET
showing moderate transconductance and least gate to drain
capacitance shows improved performance.
Fig. 6.21: Comparison of gain bandwidth product for devices
for n-channel DM-
DG, HALO-DG and conventional DG MOSFETs as a
function of the
gate to source voltage for drain voltage of Vds=
2.0V.

Effects on Channel Mobility

The channel mobility in a MOS structure is not constant but
has a universal relationship with effective normal electric field i.e.
the field perpendicular to the Si-SiO2 interface [22]. In short channel
MOSFETs, the electron velocity in the channel is also a function of
this normal electric field. From the simulated results, we saw that
both the HALO-DG and the DM-DG MOSFETs show improved
intrinsic gain in the subthreshold regime. As seen from the electron
velocity plot in Figure 6.9, the velocity at the source end is slightly
higher in halo doped device than DM-DG MOSFET in the
subthreshold regime i.e. for Vgs =0.3V. This is due to the fact that
the highly doped halo is placed adjacent to the source side. The
electron velocity at the source end is crucial for judging analog
performance in MOSFETs. So channel engineering shows better
performance than the conventional DG MOSFET in the subthreshold
regime. But as gate to source voltage increases and gate regains
control over the channel i.e. in the superthreshold region, the
normal electric field at the source end increases.
The electron mobility being a function of normal electric field
decreases considerably with this increasing electric field which
becomes dominant when the doping concentration is high. So the
HALO-DG device having heavy implant at the source side shows
considerable degradation in performance compared to DM-DG
MOSFETs in the superthreshold region. As is evident from the same
figure, the electron velocity for the HALO-DG MOSFETs does not
exceeds that of the gate engineered DG device in the strong
inversion regime, thus is not favorable for high power high
frequency applications. Double gate MOSFETs with dual material
gate technology show increased carrier transport efficiency and is
applicable for subthreshold analog performance as well as for high
power RF applications.
6.6 SUMMARY

In this chapter, we have clearly analyzed the influence of gate and

channel engineering on the digital, the analog and the RF
performances of double gate MOSFETs. For digital applications, the
parameters such as on-off current ratio, the DIBL and the delay
factor and for the analog and RF applications the
transconductance, output impedance, the gain, g m / I D and the cut-
off frequency are discussed in detail. The halo doped DG MOSFETs
show a considerable degradation of performance in case of I on / I off
ratio and delay factor. The gate engineering devices shows least
DIBL and delay factor with a slight reduction of the on-off current
ratio compared to that of the conventional DG MOS devices. In case
of analog applications, both the engineering techniques show
considerable increase in the intrinsic gain over the entire gate
voltage regime with reduction of g m / I D factor in weak inversion
regime. The gain of the halo doped DG MOSFET degrades severely
at strong inversion. The cut-off frequency is increased in case of
the DMDG devices than the other devices showing its superiority in
the field of RF applications. From lithographic point of view, the
channel engineered DG MOS devices are much easier to fabricate
compared to that of the complex dual metal gate technology. But
several reports are there regarding the fabrication of the DMG FET
in bulk technology. Also for thin film SOI or DG MOS devices, the
gate work-function engineering such as the dual metal gate
technology is most favorable one for low power subthreshold
analog performances as well as high power RF applications.

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______________
CHAPTER

7
________________
 INVESTIGATION OF NOVEL ATTRIBUTES OF
SINGLE HALO DUAL MATERIAL DOUBLE
GATE MOSFETs FOR ANALOG / RF
APPLICATIONS

7.1 INTRODUCTION

The rigorous downscaling of the MOS transistors in the past

30 years has made it the prime candidate to rule the
microelectronics industry. In addition to its excellent performance
in digital applications, CMOS technology has also started
dominating the analog and RF market which was previously
dominated by the BJT, MESFET and the BICMOS devices [1].
Furthermore, the scaling of CMOS technology with improved RF
Figure of Merits has made it attractive for system-on-chip (SoC)
applications, where the analog circuits are realized with the digital
circuits in the same integrated circuit in order to reduce the cost
and improve the performance [2-4]. But conventional CMOS
technology is facing greater challenges in terms of scaling due to
the reduced gate control and the increased leakage currents.
Double-Gate (DG) MOSFETs have emerged as the promising
devices for the nano-scale circuits due to their better scalability
below 45nm compared to the bulk CMOS technology. However, for
channel lengths below 100nm, DG MOSFETs still show considerable
leakage currents and to overcome this effect, the different
engineering techniques can be used. One of them is the use of the
single halo or lateral asymmetric channel (LAC) which shows
considerable reduction of SCEs [5] – [13]. Quite a few reports are
available on the performance of LAC devices for both digital and
mixed signal applications [12]. On the other hand, the gate
engineering technique such as Dual Metal Gate (DMG) MOSFET has
been proposed in which the structure has two gates with different
work functions [14]-[19].
A threshold voltage model has been proposed by Zunchao Li et al
in [13] where a SOI MOSFET is implemented with the lateral
 asymmetric channel along with the dual metal gate technology.
The characteristics of the novel device are compared with the
single-halo doped SOI MOSFETs. Various reports are available
regarding the application of the channel and the gate engineering
in DG devices separately. In this chapter, we explore the novel
attributes regarding the digital, analog and RF performances of a
Single Halo doped DG MOSFET with Dual Metal gate technology
(SHDM). The idea behind this work is to simulate a novel device
which shows better performance in both the subthreshold and
saturation regime.

7.2 DEVICE STRUCTURES AND PARAMETERS

The schematic cross-sectional view of a Single Halo DG MOSFET

implemented with Dual Metal Gate technology (SHDM) is shown in
Fig. 7.1(a). The technology parameters and the supply voltages
used for the device simulations are according to the International
Technology Roadmap for Semiconductors (ITRS) for 100nm gate
length devices [2].
Fig. 7.1 (a) Two dimensional view of a n-channel Single Halo – Dual Metal Gate DG
MOSFET (SHDM). (b) The variation of the threshold voltage of an n-channel
DG MOSFET with the halo doping concentration.

The Effect of halo doping on the threshold voltage of the n-channel

DG MOSFET is illustrated in Fig. 7.1(b). For comparatively low
doping profile, the threshold voltage increases at a slower rate. The
rate increases as the doping level crosses a certain limit of around
2 × 1018 / cc . The pocket implantation is set at 7.5 × 1017 cm-3 and the
length of the halo doping is fixed at 20nm. An optimization work is
carried out regarding the length and the doping of the highly doped
halo pockets. As the length of the pocket is increased, a smaller
doping will be necessary for tuning the same threshold voltage. The
optimization of the device indicated that a halo length of 20nm and
a doping concentration of 7.5 × 1017 cm-3 results in most superior
performance in respect of the DIBL, the output impedance and the
intrinsic gain. In SHDM double gate MOSFET, the work function of
metal M1 and M2 are fixed at 4.55ev and 4.1ev respectively and
their lengths are kept at equal proportions for the superior
performance as suggested in [15]. In both the devices, the body
doping is kept undoped (~10^15/cc) to reduce the effect of mobility
degradation by Coulomb scattering.
 Various process steps have been suggested to realize the dual
metal gate technology. A novel Split-Gate MOSFET was reported in
[18] with mono-nickel-silicide (NiSi) as a promising gate metal.
Antimony implantation in the polysilicon gate prior to silicidation
results in the reduction of NiSi work function. By using proper
masking technology, Antimony can be implanted to the NiSi gate
close to the drain side thus forming high-low work-function
architecture. Another process steps was reported by Zhou et al.
[19] where five additional steps are required prior to LDD
formation. The metal with high work-function can be deposited
using the self-aligned asymmetric spacer process with a high
degree of thickness control.
Sentaurus of ISE TCAD [21] is used for 2-D simulation. In our
simulation, we have used the density gradient model which solves
the quantum potential equations self-consistently with the Poisson
and the carrier continuity equations. The quantum potential is
introduced to include the quantization effects in a classical device
simulation. In the density-gradient transport approximation, the
quantum potential is a function of the carrier densities and their
gradients.

7.3 SIMULATION RESULTS AND DISCUSSION

The surface electrostatic potential of the n-channel SHDM and SH

DG MOSFET is shown in Fig. 7.2 for the drain-to-source voltage of
Vds = 2.0 V and the gate-to-source voltage ( Vgs ) = 0.3V and 2.0V. As
is evident from Fig. 2, the surface potential at a gate voltage of 0.3
V i.e. in the subthreshold condition shows a step rise at the
interface of the two metals along the channel in the SHDM
technology than the SH structure. Due to discontinuity of the metal
work function in SHDM structure, the rise in the potential occurs at
the interface of the two metals thus indicating the fact that the
drain voltage variations are shielded from affecting the channel
region. This effect results in reduced drain induced barrier lowering
and increased output resistance of the SHDM MOSFET. Fig. 7.3
reveals that there is step rise in the electric field at the interface of
two metals in the SHDM structure at the centre of the channel
which implies that resulting field at drain end is considerably
reduced resulting in reduced DIBL and hot carrier effects.

Fig 7.2: Comparison of electrostatic surface potential along the channel for gate to
Source voltage of Vgs = 0.3V and 2.0V and drain to source voltage of Vds =
2.0V in SHDM and SHdouble gate n-channel devices.

Fig. 7.3: Comparison of Lateral Electric Field along the channel for gate to source
Voltage of Vgs = 0.3V and 2.0V and drain to source voltage of Vds = 2.0V in
 SHDM and SH double gate n-channel devices.

The nature of electron velocity shown in Fig. 7.4 is very

much similar to electric field so that there is a flattening of the
electron velocity along the channel. Because of the acceleration by
the additional higher electron velocity, carriers will travel through
the channel more quickly in SHDM than SH. Therefore the carriers
transport efficiency in SHDM is enhanced as compared with SH
MOSFET resulting in improved analog and RF performance.
It is of prime importance that the sudden rise of the electric
field or the electron velocity at the interface of the two gate metals
in case of the SHDM architecture is more prominent in case of the
subthreshold regime or gate voltage of 0.3V. Thus the SHDM
technology results in improved performance with more prominence
in the subthreshold region.

Fig. 7.4 Comparison of Electron Velocity along the channel for gate to source
voltage of Vgs = 0.3V and 2.0V and drain to source voltage of Vds = 2.0V in
SHDM and SH double gate n-channel devices.

The DIBL of SHDM n-channel MOSFET and SH device are

respectively obtained as 0.8354 mV/V and 3.46 mV/V. The delay of
SHDM and the SH
architecture are 2.45ps and 2.66ps respectively resulting in a
decrease of around 9%.

7.3.1 ANALOG PERFORMANCE

The different analog performance parameters like the

transconductance g m , the transconductance generation factor (
g m / I D ) and the output resistance Ro are studied in this section. The
drain current and the transconductance variation with the gate to
source voltage for a drain voltage of 2V are shown in Fig. 7.5. As is
evident, the drain current and the transconductance in SHDM
architecture is increased compared to the SH structure. The reason
behind such improvement of the drain current is attributed to the
increased electron velocity at the source end and thus improved
carrier transport efficiency of the dual metal gate technology. The
improvement is more prominent in the subthreshold regime thus
making the device applicable for low power subthreshold analog
circuits.

Fig. 7.5 Comparison of drain current and transconductance in the SHDM and the
SH
 double gate n-channel MOSFETs as a function of gate to source voltage Vgs
for drain tosource voltage of Vds = 2.0V.

Fig. 7.6 Comparison of drain current in the SHDM and the SH n-channel
MOSFETs as a function of drain to source voltage Vds for different gate to
source voltage.
The variation of the drain current with the drain to source voltage
for different gate to source voltages is shown in Fig. 7.6. It is clearly
visible that the SHDM architecture results in increased drain
current with more independency with the drain to source voltage in
the saturation region. This denotes the higher Early voltage and the
output resistance of the SHDM DG MOSFET than the SH
counterpart.
Another parameter to be mentioned is g m / I D ratio or the
transconductance generation factor (TGF) which is viewed as the
available gain per unit value of power dissipation. In a MOS
transistor, the g m / I D is maximum when in weak inversion and
degrades severely with increasing drain current in the strong
inversion regime. Fig. 7.7 shows the g m / I D curve implying that the
TGF for the SHDM architecture is lower than the SH device in the
subthreshold regime. This should not affect the performance much
in the subthreshold regime, since the power dissipation is much
less in that regime. As the gate voltage increases beyond the
threshold voltage, the TGF of both the device merge and no
improvement or degradation of the performance is observed. The
early voltage variation with the gate to source voltage is also
shown in Fig. 7.7 where the SHDM DG MOSFET exhibits
comparatively higher early voltage than the SH counterpart over
the entire range of the gate voltage.

Fig. 7.7 Comparison of transconductance generation factor and Early voltage for the
SHDM and the SH n-channel MOSFETs as a function of gate to source
voltage Vgs for drain to source voltage Vds = 2.0V.
Such an improvement is due to the fact that the region of the
channel under the metal M2 provides a shielding effect such that
the channel region under the M1 is not affected by the drain to
source voltage variations. The output resistance variation with the
gate to source voltage is shown in Fig. 7.8 where the SHDM devices
demonstrate a considerable increase of Ro due to the shielding
effect of the channel by the metal gate M2. The intrinsic gain which
is product of transconductance and output impedance is also
shown in the same figure. The SHDM n-channel device exhibits a
substantial increase in the gain and is more prominent in the low
gate voltage regime. The SHDM devices are thus expected to
perform better in case of subthreshold analog applications
compared to the SH devices.

Fig. 7.8 Comparison of output resistance Ro and intrinsic gain (gmRo) for the SHDM
and the SH n-channel MOSFETs as a function of gate to source voltage
Vgs for drain to source voltage Vds = 2.0V.

7.3.2 RF PERFORMANCE

In this section, we focus on the intrinsic RF performances of the

gate and the channel engineering technology. The different
capacitance variations are shown in Fig. 7.9 and 7.10. The electron
density is increased near the drain end in case of the SHDM n-
channel device due to the lower work-function of the metal M2. The
gate to drain capacitance ( C gd ) is slightly increased for SHDM
device compared to the SH counterpart as shown in Fig. 7.9. The
enhancement becomes prominent for the low drain to source
voltage of 1.0V. Due to the similarity of the channel and gate
architecture of the SHDM and SH DG MOSFET, the gate to source
capacitance ( C gs ) is more or less same for both the devices under
consideration. The total gate capacitance being the sum of C gs and
C gd shows more or less equality with slight increase in the strong
inversion regime due to the effect of increased C gd as evident from
Fig. 7.10.

Fig. 7.9 Comparison of gate to drain capacitance in the SHDM and the SH n-channel
MOSFETs as a function of gate to source voltage Vgs at drain to source
voltage of Vds = 2.0V.
Fig 7.10 Comparison of different capacitance in the SHDM and the SH n-channel
MOSFETs as a function of gate to source voltage Vgs at drain to source voltage
of Vds = 2.0V.

Fig. 7.11 Comparison of cut-off frequency computed as a function of gate to source

 voltage Vgs for the SHDM and the SH n-channel MOSFETs at drain to
source voltage of Vds = 2.0V and 1.0V.
Fig. 7.11 shows the cut-off frequency versus the gate to
source voltage Vgs that reveals the increased cut-off frequency of
the SHDM devices compared to the SH devices. The maximum
frequency of oscillation for the SHDM and the SH devices for the
different drain to source voltage is shown in Fig. 7.12. The gate to
drain capacitance plays a major role in determining f max . Owing to
the higher gate to drain capacitance at strong inversion, the
maximum frequency of oscillation of the SHDM devices is only
slightly higher that of the SH devices with slight degradation at
high gate voltages.
Fig. 7.13 shows the Gate Bandwidth (GBW) product for a gain of
10 implying that SHDM DG MOSFET is superior to SH MOSFET when
the gate voltage is below the supply voltage( VDD / 2 ). As the gate to
source voltage approaches the supply voltage, owing to the
increased gate to drain capacitance at higher drain to source
voltage, the SHDM devices shows slight degradation of
performance.

Fig. 7.12 Comparison of maximum frequency of oscillation computed as a function of

 gate to source voltage Vgs for the SHDM and the SH devices at drain to
source voltage of Vds = 2.0V and 1.0V.

Fig. 7.13 Comparison of the Gain Bandwidth Product for a dc gain of 10 computed for
the SHDM and the SH n-channel MOSFETs at drain to source voltage of
Vds = 2.0V and 1.0V.
7.3.3 CIRCUIT APPLICATIONS
Fig. 7.14 Circuit diagram of a simple two stage cascode amplifier implemented with n-
channel SHDM and SH MOSFETs.

The circuit performance of n-channel SHDM devices is studied and

compared with it’s SH counterpart. The circuit of a two stage
cascode amplifier is shown in Fig. 7.14 where MOSFET M2 is biased
by the biasing voltage Vb and the input is fed to the gate of MOSFET
M1. The drain conductance of the device M2 can be tuned using the
bias voltage Vb . The output impedance Rout of the cascode amplifier
is given by equation (1)
Rout = [ 1 + ( gm2 R2o ]) R1o +R2o
(7.1)
where m 2 is the transconductance of the MOSFET M2, Ro1 and Ro 2
g
are the output resistance of the MOSFET M1 and M2 respectively.
Thus owing to the higher drain conductance of the device M2, the
output impedance of the circuit is boosted so that the total gain of
the circuit with the SHDM devices is increased significantly
compared to SH devices as shown in fig. 15.
Fig. 7.15 Comparison of voltage gain of a two stage cascode amplifier with the SHDM
and the SH n-channel DG MOSFETs as a function of the bias voltage Vb for
an output voltage of Voutput=VDD/2=1.0V

The total gain Av is given by

Av = g m1 Rout
(7.2)
g
where m1 is the transconductance of the MOSFET M1. The gain is
calculated by taking the slope of the input-output curve for
different values of the bias voltage Vb calculated at an output
voltage of 1.0V. The gain of the cascode amplifier with the SHDM
devices increases by about 21.5% compared to that of the circuit
with the SH devices. Thus the SHDM n-channel DG MOSFET
behaves superior than the DG MOSFET with SH architecture.

7.4 SUMMARY

In this paper, we have clearly analyzed the effect of lateral

asymmetric halo doping along with the dual metal technology
(SHDM) in respect of digital, analog and RF performance and
 compared it with that of a single halo doped DG-MOSFET (SH). The
use of the dual metal gate technology enhances the performances
of the single halo doped DG MOSFET in respect of the
transconductance, the g m / I D ratio, the output impedance and the
intrinsic gain. The improvement is more prominent in the weak
inversion regime thus making it more applicable for low power
subthreshold analog performance. The different RF-FOMs also show
improvement in SHDM devices than the SH devices biased at a
voltage of VDD / 2 . The performance of a two stage cascode amplifier
is also illustrated using the SHDM and the SH architecture. The
amplifier with SHDM DG MOSFET shows an increase of gain by
around 21.5% than the SH counterpart. Thus it can be concluded
that SHDM devices show improved performance than SH devices
for ultra low power as well as RF applications.

REFERENCES

1. Pierre H.Woerlee, Mathijs J. Knitel, Ronald van Langevelde, Dirk B. M.

Klaassen, Luuk F. Tiemeijer, Andries J. Scholten, and Adrie T. A. Zegers-van
Duijnhoven , “RF-CMOS Performance Trends ” IEEE Trans. Electron Devices, vol.
48, no. 8, pp. 1776-1782.
2. International Technology Roadmaps for Semiconductor (ITRS), 2005 edition
3. H.S. Momose, E. Monfuzi, T. Yoshitomi, T. Ohguro, M. Saito, T. Morimoto,
Y.Katsumata, and H. Iwai, “ High frequency AC characteristics of 1.5-nm gate
oxide MOSFETs,” in IEDM Tech. Dig., 1996, pp. 105-107.
4. Y.Momiyama, T.Hirose, H.Kurata, K.Goto, Y.Watanabe, and T.Sugii, “A 140
Ghz ft and 60 Ghz fmax DTMOS integrated with high performance SOI logic
technology,” in IEDM Tech. Dig., 2000, pp. 451-455.
5. F.Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “ Double-gate
silicon-on-insulator transistor with volume inversion: A new device with greatly
enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, pp.410, 1987
6. D. Frank, S. Laux, and M. Fischetti, “Monte Carlo simulation of a 30nm dual-
gate MOSFET: How far can silicon go?” 1992 IEDM Tech. Dig., pp.553.
7. H.-S. P. Wong, D.J. Frank, and P.M.Solomon, “Device design considerations for
double-gate, ground-plane, and single-gate ultra-thin SOI MOSFET’s at the 25 nm
gate length generation, ”IEDM Tech. Dig., 1998.
8. V. Kilchytska et al., “Influence of Device Engineering on the Analog and RF
Performance of SOI MOSFETs”, IEEE Trans. Electron Devices, vol. 50, no. 3, pp.
577-588, 2003.
9. A. Kranti, T. M. Chung, D. Flandre and J. P. Raskin, “Laterally Asymmetric
Channel Engineering in Fully Depleted Double Gate SOI MOSFETs for High
Performance Analog Applications”, Solid State Electronics, 48(2004) 947-959.
10. A.Bansal and K. Roy, “Asymmetric Halo CMOSFET to reduce static power
dissipation with improved performance,” IEEE Trans. Electron Devices, vol.52,
no.3, pp. 397-405.
11. D. G. Borse, Manjula Rani K.N, Neeraj K. Jha, A.N. Chandorkar, J. Vasi, V.
Ramgopal Rao, B. Cheng, and J. C. S. Woo “Optimization and Realization of
Sub-100-nm Channel Length Single Halo p-MOSFETs” IEEE Trans. Electron
Devices, vol. 49, no. 6, pp. 1077- 1078.
12. S. Chakraborty, A. Mallik, C.K.Sarkar and V.Ramgopal Rao, “ Impact of halo
doping on the subthreshold performance of deep-sub micrometer CMOS devices
and circuits for ultralow power analog/mixed signal applications” IEEE Trans.
Electron Devices, vol. 54, no. 2, pp. 241-248.
13. Zunchao Li, Yaolin Jiang, Lili Zhang, “A Single-Halo Dual-Material Gate SOI
MOSFET”, IEDST 2007, pp. 66-69
14. W. Long, H. Ou. J. Kuo, and K.K. Chin ,“ Dual-Material Gate ( DMG) Field Effect
Transistors ,” IEEE Trans. Electron Devices, vol. 46, no. 5, pp.865-870, 1999.
15. A.Chaudhry and M.Jagadesh Kumar, “Investigation of the Novel Attributes of
a Fully Depleted Dual-Material Gate SOI MOSFET,” IEEE Trans. Electron Devices,
vol. 51, no. 9, pp.1463-1467, 2004.
16. S. Chakraborti, A. Mallik and C.K.Sarkar, “Subthreshold performance of dual-
material gate CMOS devices and circuits for ultralow power analog/mixed –signal
applications,” IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 827-832, 2008.
17. M.Saxena, S.Haldar, M.Gupta, R.S.Gupta, “Physics-Based Analytical Modeling
of Potential and Electric Field Distribution in Dual Material Gate (DMG)-MOSFET
for Improved Hot Electron Effect and Carrier Transport Efficiency” IEEE Trans.
Electron Devices, vol. 49, no. 11, pp. 1928-1938, 2002.
18. J.Yuan, J.C.S. Woo, “A Novel Split-Gate MOSFET Design Realized by a Fully
Silicided Gate Process for the Improvement of Transconductance and Output
Resistance”, IEEE. Electron Devices Letters, vol. 26, no. 11, pp. 829-831, 2005.
19. Xing Zhou, “ Exploring the Novel Characteristics of Hetero-Material Gate
Field-Effect Transistors (HMGFET’s) with Gate-Material Engineering” , IEEE Trans.
Electron Devices, vol. 47, no. 1, pp. 113-120, 2000.
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231, Jun. 1977.
21. Integrated Systems Engineering (ISE) TCAD Manuals, 2006. Release 10.0
 ______________
CHAPTER

8
_______________

OVERVIEW OF TCAD TOOLS

OVOOOOERVIE TCAD (Technology Computer Aided Design) is

a technology that solves the equations representing the
manufacturing process of Large Scale Integration (LSI) or
transistors, or equations representing the physical / chemical
phenomena relevant to electrical conduction. TCAD simulates and
predicts characteristics of a transistor or semiconductor circuit and
thereby increases the efficiency in designing and development of
LSI. In other words, TCAD means a CAD technology that covers the
physical/chemical phenomena on the semiconductors.

8.1 WHAT IS TECHNOLOGY-CAD?

Technology CAD (or Technology Computer Aided Design, or
TCAD) is a branch of electronic design automation that models the
semiconductor fabrication and the semiconductor device operation.
The modeling of the fabrication is termed as the Process TCAD,
while the modeling of the device operation is termed as the Device
TCAD. Included are the modeling of process steps (such as diffusion
and ion implantation), and modeling of the behavior of the
electrical devices based on fundamental physics, such as the
doping profiles of the devices. TCAD may also include the creation
of compact models (such as the well known SPICE transistor
models), which try to capture the electrical behavior of such
devices but do not generally derive them from the underlying
physics. Technology Computer-Aided Design (TCAD) refers to the
use of computer simulations to develop and optimize
semiconductor processing technologies and devices. Figure 8.1
depicts a hierarchy of process, device and circuit levels of
simulation tools. On each side of the boxes indicating modeling
level are icons that schematically depict the representative
applications for TCAD. The left side gives emphasis to the Design
For Manufacturing (DFM) issues such as: shallow-trench isolation
(STI), extra features required for phase-shift masking (PSM) and
challenges for multi-level interconnects that include processing
issues of chemical-mechanical planarization (CMP), and the need to
consider electro-magnetic effects using electromagnetic field
solvers. The right side icons show the more traditional hierarchy of
expected TCAD results and applications: complete process
simulations of the intrinsic devices, predictions of drive current
scaling and extraction of technology files for the complete set of
devices and parasitics.
 Fig. 8.1: Hierarchy of technology CAD tools building from the
process level to circuits.

In this work, all the devices are simulated by TCAD tool

provided by Synopsys. Synopsys TCAD offers a comprehensive
suite of products that includes industry leading process and device
simulation tools, as well as a powerful GUI-driven simulation
environment for managing simulation tasks and analyzing
simulation results. The TCAD process and device simulation tools
support a broad range of applications such as CMOS, power,
memory, image sensors, solar cells, and analog/RF devices. In
addition, Synopsys TCAD provides tools for interconnect modeling
and extraction, providing critical parasitic information for
optimizing chip performance.

Technology computer aided design has become a central part

of semiconductor modeling and design. It is important to note that
the accurate TCAD simulations and modeling of physical devices
depend significantly on calibrated physical models and proper input
data. A typical device tool flow the creation of a device structure by
a process simulation (Sentaurus Process) followed by re-meshing.
Sentaurus Device is used to simulate the electrical characteristics
of the device. Sentaurus Device simulates numerically the electrical
behavior of a single semiconductor device in isolation or several
physical devices combined in a circuit. Terminal currents, voltages,
and charges are computed based on a set of physical device
equations that describes the carrier distribution and the conduction
mechanisms. Finally, Tecplot SV is used to visualize the output
from the simulation in 2D and 3D, and Inspect is used to plot the
electrical characteristics.

8.2 SENTAURUS PROCESS

Sentaurus Process is a complete and highly flexible,
multidimensional, process modeling environment. With its modern
software architecture, it constitutes a new tool generation and a
solid base for process simulation. It is calibrated to a wide range of
latest experimental data using proven calibration methodology,
Sentaurus process offers unique predictive capabilities for modern
silicon and non-silicon technologies.
The main file types used in sentaurus process are:
• Sentaurus Process command file ( * . cmd)
This file is the main input file for Sentaurus process. It contains all
the process steps and can be edited. This file is referred to as the
command file or input file.
• Log file ( * . log)
This file is generated by sentaurus process during a run. It contains
information about each processing step and the models and values
of physical parameters used in it. The amount of information
written to the log file can be controlled by certain parameters
specified in the process command file.
• Structure file (has no extension)
This is the Sentaurus process internal format for saving the
simulation. It contains the complete information about the
geometry of the device and all datasets. Users can save the
simulation in this format at points of interest or at the end of the
simulation.
• TDR boundary file ( *_bnd . tdr)
This Synopsys specific format stores the geometry of the device
and is usually saved by the user at the end of the simulation. This
file is used as input to the meshing engines and can be loaded into
tecplot for viewing.
• TDR grid and doping file ( *_fps . tdr)
This single file stores two kind of information. One is the
information about the geometry of the device and the grid. The
other is information about the distribution of doping and other
datasets in the device. A TDR file can be reloaded into Sentaurus
process to continue the simulation and can be loaded into tecplot
for visualization.
To start Sentaurus Process in the interactive mode type sprocess

A 2D process simulation example using Sentaurus process is given

below.

#----------------------------------------------------------------------
# 2D nMOSFET (0.18um technology)
#----------------------------------------------------------------------

#--- Declare initial grid (half structure) ----------------------------

line x location= 0.0 spacing= 1.0<nm> tag=SiTop
line x location=50.0<nm> spacing=10.0<nm>
line x location= 0.5<um> spacing=50.0<nm>
line x location= 2.0<um> spacing= 0.2<um>
line x location= 4.0<um> spacing= 0.4<um>
line x location=10.0<um> spacing= 2.0<um> tag=SiBottom

line y location=0.0 spacing=50.0<nm> tag=Mid

line y location=0.40<um> spacing=50.0<nm> tag=Right

#--- Silicon substrate definition -------------------------------------

region silicon xlo=SiTop xhi=SiBottom ylo=Mid yhi=Right

#--- Initialize the simulation ----------------------------------------

init concentration=1.0e+15<cm-3> field=Phosphorus

#--- p-well, anti-punchthrough & Vt adjustment implants ---------------

implant Boron dose=2.0e13<cm-2> energy=200<keV> tilt=0
rotation=0
implant Boron dose=1.0e13<cm-2> energy= 80<keV> tilt=0
rotation=0
implant Boron dose=2.0e12<cm-2> energy= 25<keV> tilt=0
rotation=0

#--- p-well: RTA of channel implants ----------------------------------

diffuse temperature=1050<C> time=10.0<s>

#--- Saving structure -------------------------------------------------

struct tdr=NMOS1 ; # p-Well

#--- MGOALS settings for automatic meshing in newly generated

layers -
mgoals on min.normal.size=1<nm> max.lateral.size=2.0<um> \
normal.growth.ratio=1.4 accuracy=2e-5

#--- Gate oxidation ---------------------------------------------------

diffuse temperature=850<C> time=10.0<min> O2
grid remesh
select z=Boron
layers
struct tdr=NMOS2 ; # GateOx

#--- Poly gate deposition ---------------------------------------------

deposit poly type=anisotropic thickness=0.18<um>
#--- Poly gate pattern/etch -------------------------------------------
mask name=gate_mask left=-1 right=90<nm>
etch poly type=anisotropic thickness=0.2<um> mask=gate_mask
etch oxide type=anisotropic thickness=0.1<um>
struct tdr=NMOS3 ; # PolyGate

#--- Poly reoxidation -------------------------------------------------

diffuse temperature=900<C> time=10.0<min> O2
pressure=0.5<atm> \
mgoals.native
struct tdr=NMOS4 ; # Poly Reox

#--- LDD implantation -------------------------------------------------

refinebox silicon min= {0.0 0.05} max= {0.1 0.12} \
xrefine= {0.01 0.01 0.01} yrefine= {0.01 0.01 0.01} add
refinebox remesh

implant Arsenic dose=4e14<cm-2> energy=10<keV> tilt=0

rotation=0
diffuse temperature=1050<C> time=0.1<s> ; # Quick activation
struct tdr=NMOS5 ; # LDD Implant

#--- Halo implantation: Quad HALO implants ----------------------------

implant Boron dose=0.25e13<cm-2> energy=20<keV> \
tilt=30<degree> rotation=0
implant Boron dose=0.25e13<cm-2> energy=20<keV> \
tilt=30<degree> rotation=90<degree>
implant Boron dose=0.25e13<cm-2> energy=20<keV> \
tilt=30<degree> rotation=180<degree>
implant Boron dose=0.25e13<cm-2> energy=20<keV> \
tilt=30<degree> rotation=270<degree>
#--- RTA of LDD/HALO implants -----------------------------------------
diffuse temperature=1050<C> time=5.0<s>
struct tdr=NMOS6 ; # Halo RTA

#--- Nitride spacer ---------------------------------------------------

deposit nitride type=isotropic thickness=60<nm>
etch nitride type=anisotropic thickness=84<nm>
etch oxide type=anisotropic thickness=10<nm>
struct tdr=NMOS7 ; # Spacer

#--- N+ implantation --------------------------------------------------

refinebox silicon min= {0.04 0.05} max= {0.18 0.4} \
xrefine= {0.01 0.01 0.01} yrefine= {0.05 0.05 0.05} add
refinebox remesh
implant Arsenic dose=5e15<cm-2> energy=40<keV> \
tilt=7<degree> rotation=-90<degree>

#--- N+ implantation & final RTA -------------------------------------

diffuse temperature=1050<C> time=10.0<s>
struct tdr=NMOS8 ; # S/D implants

#--- Contacts ---------------------------------------------------------

deposit Aluminum type=isotropic thickness=30<nm>

mask name=contacts_mask left=0.2<um> right=1.0<um>

etch Aluminum type=anisotropic thickness=0.25<um>
mask=contacts_mask
etch Aluminum type=isotropic thickness=0.02<um>
mask=contacts_mask

#--- Reflect ---------------------------------------------------------

transform reflect left
struct smesh=NMOS ; # Final

# save final structure:

# - 1D cross sections
SetPlxList {BTotal NetActive}
WritePlx NMOS_channel.plx y=0.0 silicon
SetPlxList {AsTotal BTotal NetActive}
WritePlx NMOS_ldd.plx y=0.1 silicon

SetPlxList {AsTotal BTotal NetActive}

WritePlx NMOS_sd.plx y=0.35 silicon

The various process steps in the above example can be viewed as

Figure 8.2 (A-F)

(A) (B)
(C) (D)

(E) (F)
 (F)
Fig 8.2(A-F): Different process steps in 2D n-MOSFET using
Sentaurus Process

In addition to these features, Sentaurus Process can also be used to

calibrate the files with experimental data for accurate results.
8.3 SENTAURUS STRUCTURE EDITOR

Sentaurus Structure Editor is a structure editor for 2D and

3D device structures. It has three distinct operational nodes: 2D
structure editing, 3D structure editing and 3D process
emulation.From the graphical user interface (GUI), 2D and 3D
device models are created geometrically using 2D or 3D primitives
such as rectangles,polygons,cuboids etc. The GUI features a
command-line window in which Sentaurus Structure editor prints
script commands corresponding to the GUI operations.
In the process emulation mode (Procem), Sentaurus
Structure Editor translates processing steps such as etching and
deposition, patterning, fill and polish into geometric operations.
Procem supports various options such as isotropic or anisotropic
etching and deposition, rounding and blending.
To start Sentaurus Structure Editor , on the command line, enter:
sde

Fig. 8.3 Graphical user interface of Sentaurus Structure Editor

Fig. 8.4 Constant Profile Placement dialog box

Fig. 8.5 Multibox Placement dialog box

 Fig. 8.6 Build Mesh dialog box

Fig. 8.7 Two-dimensional SOI MOSFET with its current Meshing

and doping
conditions
 The input and output files of Sentaurus Structure Editor are
• Scheme script file ( . scm)
This is a user-defined script file that contains scheme script
commands describing the steps to be executed by Sentaurus
Structure Editor in creating a device structure. This file can be
edited to change its contents.
• ACIS SAT file ( . sat)
This file contains the model geometry in native ACIS format and
cannot be edited directly.
• DF-ISE boundary file ( . bnd)
This is a boundary representation file written in the DF-ISE format.
It can be directly loaded into Sentaurus Structure Editor and then to
mesh engines.
• DF-ISE doping and refinement file ( . cmd)
This is a DF-ISE format file containing doping and mesh refinement
information that, in conjunction with the corresponding boundary
file, uniquely defines the geometry of the model.

8.4 SENTAURUS DEVICE

The typical tool flow of the device from process to plot is
shown in Fig. 2.68.
Fig. 8.8 Typical tool flow with device simulation using Sentaurus
Device
A real semiconductor device, such as a transistor, is
represented in the simulator as a ‘virtual’ device whose physical
properties are discretized onto a non-uniform ‘grid’ (or ‘mesh’) of
nodes. A virtual device is an approximation of a real device.
Continuous properties such as doping profiles are represented on a
sparse mesh and, therefore, are only defined at a finite number of
discrete points in space. The doping at any point between nodes (or
any physical quantity calculated by Sentaurus Device) can be
obtained by interpolation. Each virtual device structure is described
in the Synopsys TCAD tool suite by two files:

 The grid (or geometry) file contains a description of the various

regions of the device, that is, boundaries, material types, and
the locations of any electrical contacts. This file also contains
the grid (the locations of all the discrete nodes and their
connectivity). The typical contents of this file, such as the
boundary and grid of a typical MOSFET structure, are shown in
Figure 2.69(a).
 The data (or doping) file contains the properties of the device,
such as the doping profiles, in the form of data associated with
the discrete nodes. Figure 2.69(b) is an example. By default, a
device simulated in 2D is assumed to have a ‘thickness’ in the
third dimension of 1 μm.

The features of Sentaurus Device are many and varied. They can
be summarized as:

• An extensive set of models for device physics and effects in

semiconductor devices (drift-diffusion, thermodynamic, and
hydrodynamic models).
• General support for different device geometries (1D, 2D, 3D,
and 2D cylindrical).
• Mixed-mode support of electro thermal net lists with mesh-
based device models and SPICE circuit models.
 (a) (b)
Fig. 8.9 (a) Left - Region boundaries of a MOSFET structure with
nodes and mesh
(b) Right- Two-dimensional doping profile that is
discredited on the
Node simulation grid

8.4.1 PHYSICAL APPROACH OF THE TOOL

The Physics section allows a selection of the physical models
to be applied in the device simulation. In the example shown below,
it is sufficient to include basic mobility models and a definition of
the band gap (and, therefore, the intrinsic carrier concentration).
Potentially important effects, such as impact ionization (avalanche
breakdown at the drain), are ignored at this stage.

Physics {

Mobility (DopingDependence HighFieldSat Enormal)

EffectiveIntrinsicDensity (BandGapNarrowing
(OldSlotboom))

Mobility (DopingDependence HighFieldSat Enormal)

Physical phenomena in semiconductor devices are very

complicated and, depending on applications, are described by
partial differential equations of different level of complexity.
Coefficients and boundary conditions of equations (such as
mobility, generation–recombination rate, material-dependent
parameters, and interface and contact boundary conditions) can be
very complicated and can depend on microscopic physics, the
structure of the device, and the applied bias. Sentaurus Device
allows for arbitrary combinations of transport equations and
physical models, which allows for the possibility to simulate all
spectrums of semiconductor devices, from power devices to deep
submicron devices and sophisticated heterostructure.

8.4.1.1 Transport equations

Depending on the device under investigation and the level of
modeling accuracy required, the user can select four different
simulation modes:
 Drift-diffusion Isothermal simulation, described by basic
semiconductor equations. Suitable for low-power density
devices with long active regions.
 Thermodynamic Accounts for self-heating. Suitable for
devices with low thermal exchange, particularly, high-power
density devices with long active regions.
 Hydrodynamic Accounts for energy transport of the carriers.
Suitable for devices with small active regions.
 Monte Carlo Allows for full band Monte Carlo device
simulation in the selected window of the device.

8.4.1.2 Poisson equation and continuity equations

 The three governing equations for charge transport in
semiconductor devices are the Poisson equation and the electron
and hole continuity equations. The Poisson equation is:
∇.ε∇ϕ=− q( −p +n − N D− Nρ)A trap (8.1)
where ε is the electrical permittivity, q is the elementary
electronic charge, n and p are the electron and hole densities,
N D is the concentration of ionized donors, N A is the concentration
of ionized acceptors, and ρtrap is the charge density contributed by
traps and fixed charges. The keyword for the Poisson equation is
Poisson. The keywords for the electron and hole continuity
equations are electron and hole, respectively. They are written
as:
→ ∂n → ∂p
∇. J n = qRnet + q −∇. J p = qRnet + q (8.2)
∂t ∂t
→
where Rnet is the net electron–hole recombination rate, J n is the
→
electron current density, and J p is the hole current density.

8.4.1.3 Drift-diffusion model

The drift-diffusion model is widely used for the simulation of
carrier transport in semiconductors and is defined by the basic
semiconductor equations (see equation 4.1 and 4.2), where current
densities for electrons and holes are given by
→
J n = −nq µn ∇Φn
→ (8.3)
J p = − pqµ p ∇Φ p
where µ n and µ p are the electron and hole mobilities, Φ n and Φ p
are the electron and hole quasi-Fermi potentials, respectively.

8.4.1.4 Quantization models

Some features of current MOSFETs (oxide thickness, channel

width) have reached quantum-mechanical length scales. Therefore,
the wave nature of electrons and holes can no longer be neglected.
The most basic quantization effects in MOSFETs are the shift of the
threshold voltage and the reduction of the gate capacity. To include
quantization effects in a classical device simulation, Sentaurus
Device introduces potential- like quantity in the classical density
formula:
EF ,n − EC −Λn
n = N CF1/ 2 ( ) (8.4)
kTn
The most important effects related to the density modification (due
to quantization) can be captured by proper models for Λn and Λp .
Other effects (for example, single electron effects) exceed the
scope of this approach.
Sentaurus Device implements four quantization models, that
is, four different models for Λn and Λp . They differ in physical
sophistication, numeric expense, and robustness:

 The van Dort model is a numerically robust, fast, and

proven model. It is only suited to bulk MOSFET simulations.
While important terminal characteristics are well described
by this model, it does not give the correct density distribution
in the channel.
 The 1D Schrödinger equations is the most physically
sophisticated quantization model. It can be used for MOSFET
simulation, and quantum well and ultrathin SOI simulation.
Simulations with this model tend to be slow and often lead to
convergence problems, which restrict its use to situations
with small current flow. Therefore, the Schrödinger equation
is used mainly for the validation and calibration of other
quantization models.
 The density gradient model is numerically robust, but
significantly slower than the van Dort model. It can be
applied to MOSFETs, quantum wells and SOI structures, and
gives a reasonable description of terminal characteristics and
charge distribution inside a device. Compared to the other
quantization models, it can describe 2D and 3D quantization
effects.
 The modified local-density approximation (MLDA) is a
numerically robust and fast model. It can be used for bulk
MOSFET simulations and thin SOI simulations. Although it
 sometimes fails to calculate the accurate carrier distribution
in the saturation regions because of its one-dimensional
characteristic, it is suitable for three-dimensional device
simulations because of its numeric efficiency.

8.4.1.5 Density gradient model

For the density gradient model [88]-[89], Λn in equation 4.4 is

given by a partial differential equation:
γ h2 1 γ h2 ∇
2
n
Λn = − ∇
{ ln +
2
n ∇( ln n) =} −
2
(8.5)
12 mn 2 6mn n
where γ is a fitting parameter. The density gradient equation for
electrons and holes is activated by the eQuantumPotential and
hQuantumPotential switches in the Physics section. These
switches can also be used in region wise or material wise Physics
sections. In metal regions, the equations are never solved. Apart
from activating the equations in the Physics section, the equations
for the quantum corrections must be solved by using
eQuantumPotential or hQuantumPotential, or both in the Solve
section. For example:

Physics {
eQuantumPotential
}
Plot {
eQuantumPotential
}
Solve {
Coupled {Poisson eQuantumPotential}
Quasistationary (
Do Zero InitialStep=0.01 MaxStep=0.1 MinStep=1e-5
Goal {Name="gate" Voltage=2}
){
Coupled {Poisson Electron eQuantumPotential}
}
}

The various features of the Density gradient model are listed below

 Fitting parameters: The parameter has been calibrated

only for silicon. The quantum correction affects the densities
and field distribution in a device. Therefore, parameters for
mobility and recombination models that have been calibrated
to classical simulations (or simulations with the van Dort
model) may require recalibration.
 Tunneling: The density gradient model increases the current
through the semi conducting potential barriers. However, this
effect is not a trustworthy description of tunneling through the
barrier. To model tunneling, use one of the dedicated models
that Sentaurus Device provides.
 Convergence: In general and particularly for the density
gradient corrections, solving additional equations worsens
convergence. Typically, it is advisable to solve the equations
for the quantum potentials whenever the Poisson equation is
solved (using a Coupled statement). Usually, the best strategy
to obtain an initial solution at the beginning of the simulation is
to do a coupled solve of the Poisson equation and the quantum
potentials, without the current and temperature equations.
Often, using initial bias conditions that induce a current flow
work well for a classical simulation, but do not work when the
density gradient model is active. In such cases, start from
equilibrium bias conditions and put an additional voltage
ramping at the beginning of the simulation. If an initial solution
is still not possible, consider using Fermi statistics. Check grid
refinement and pay special attention to interfaces between
insulators and highly doped semiconductor regions. For
classical simulations, the refinement perpendicular to such
interfaces is often not critical, whereas for quantum
mechanical simulations, quantization introduces variations at
small length scales, which must be resolved.
 Speed: Activate the equations only for regions where the
quantum corrections are physically needed. For example,
usually, the density gradient equations do not need to be
 computed in insulators. Using the model selectively, typically,
also benefits convergence.

8.4.1.6 Mobility Models

Sentaurus Device uses a modular approach for the
description of the carrier mobilities. In the simplest case, the
mobility is a function of the lattice temperature. This so-called
constant mobility model described in Mobility due to phonon
scattering should only be used for undoped materials. For doped
materials, the carriers scatter with the impurities. This leads to a
degradation of the mobility. Models that describe the mobility
degradation at interfaces, for example, the silicon–oxide interface
in the channel region of a MOSFET, are introduced in the command
Enormal. These models account for the scattering with surface
phonons and surface roughness. Models that describe the effects of
carrier–carrier scattering are introduced in the command Carrier-
CarrierScattering. The Philips unified mobility model is a well-
calibrated model, which accounts for both impurity and carrier–
carrier scattering. Finally, the models that describe mobility
degradation in high electric fields are discussed in High-field
saturation.

8.4.1.6.1 Doping-dependent mobility degradation

The models for the mobility degradation due to impurity

scattering are activated by specifying the DopingDependence
flag to Mobility:
Physics {Mobility (DopingDependence ...) ...}
Different models are available and are selected by options to
DopingDependence: Physics {Mobility (DopingDependence
([Masetti | Arora |UniBo]) ...) ...}
If DopingDependence is specified without options, Sentaurus
Device uses a material-dependent default. The default model used
by Sentaurus Device to simulate doping-dependent mobility in
silicon was proposed by Masetti et al. [90]:
Pc µconst −µ min 2 µ1
µdop =µ min1 exp(− +) −α (8.6)
N tot 1 + (Ntot /Cr ) 1+ (Cs / Ntot )β
The reference mobilities µmin1 , µ min 2 and µ1 , the reference doping
concentrations Pc , Cr Cs and the exponents α and β are
accessible in the parameter set DopingDependence. The
corresponding values for silicon are given in Table 2.5.

8.4.1.6.2 Mobility degradation at interfaces

In the channel region of a MOSFET, the high transverse

electric field forces carriers to interact strongly with the
semiconductor–insulator interface. Carriers are subjected to
scattering by acoustic surface phonons and surface roughness. The
models in this section describe mobility degradation caused by
these effects. To select the calculation of field perpendicular to the
semiconductor–insulator interface, specify the Enormal option to
Mobility:

Table No 8.1 : Masetti model: Default coefficients

Physics {Mobility (Enormal ...) ...}

The surface contribution due to acoustic phonon scattering has the
form:
B C (N / N 0) λ
µac = + 1/3 tot (8.7)
Fn Fn (T / 300K ) k
And the contribution attributed to surface roughness scattering is
given by:
Fn / Fref ) A* Fn3 −1
µ sr = ( + ) (8.8)
δ η
These surface contributions to the mobility are then combined with
the bulk mobility according to Mathiessen’s rule
1 1 D D
= + +
µ µ bµ µ
ac sr
(8.9)
where Fref=1V/cm , Fn= Normal electric field, D= exp (–x⁄ lcrit) (where
x is the distance from the interface and l crit is a fit parameter). In
the Lombardi model [91], the exponent in equation 4.8, A * is equal
to 2. According to another study [92], an improved fit to measured
data is achieved if A * is given by:
α ( n + p ) N ref
v

A* = A + ⊥ (8.10)
( N tot + N1 )v
The respective default parameters that are appropriate for silicon
are given in table 2.5.
Table 8.2: Lombardi model: Default coefficients for silicon
8.4.1.6.3 High-field saturation

In high electric fields, the carrier drift velocity is no longer

proportional to the electric field, instead, the velocity saturates to a
finite speed vsat. The high-field saturation models comprise three
sub models: the actual mobility model, the velocity saturation
model, and the driving force model. With some restrictions, these
models can be freely combined. The actual mobility model is
selected by flags eHighFieldSaturation or
hHighFieldSaturation. The default is the Canali model. The
Canali model [93] originates from the Caughey–Thomas formula
[94], but has temperature- dependent parameters, which were
fitted up to 430K by Canali et al. [93]:
(α +1)µ
µ( F) = low
(α +1)µ F (8.11)
α +[1+ ( low hfs
) ] β 1/β
vsat
where µ low denotes the low-field mobility, Fhfs is the driving field.
The exponent β is temperature dependent according to:
 T βexp
β =β 0 ( )
300 K
(8.12)

Table 8.3: Canali model parameters (default values for silicon)

8.4.2 MATHEMATICAL APPROACH OF THE TOOL

Sentaurus Device solves the device equations (which are

essentially a set of partial differential equations) self-consistently,
on the discrete mesh, in an iterative fashion. For each set of
iteration, an error is calculated and Sentaurus Device attempts to
converge on a solution that has an acceptably small error. For most
problems, Newton iterations converge best with full derivatives.
Furthermore, for small-signal analysis, and noise and fluctuation
analysis, using full derivatives is mandatory. Therefore, by default,
Sentaurus Device takes full derivatives into account. For rare
occasions where omission of derivatives improves convergence or
performance significantly, use the keywords AvalDerivatives and
–Derivatives to switch off mobility and avalanche derivatives. The
derivatives are usually computed analytically, but a numeric
computation can be used by specifying numerically. The basic
command system of the math section is shown below

Math {
Extrapolate
RelErrControl
NotDamped=50
Iterations=20
 }
Extrapolate
In quasistationary bias ramps, the initial guess for a given step is
obtained by extrapolation from the solutions of the previous two
steps (if they exist).
RelErrControl
Switches error control during iterations from using internal error
parameters to more physically meaningful parameters
NotDamped=50
Specifies the number of Newton iterations over which the right-
hand side (RHS)-norm is allowed to increase. With the default of 1,
the error is allowed to increase for one step only. It is
recommended that NotDamped > Iterations is set to allow a
simulation to continue despite the RHS-norm increasing.
Iterations=20
Specifies the maximum number of Newton iterations allowed per
bias step (Default=50). If convergence is not achieved within this
number of steps, for a quasistationary or transient simulation, the
step size is reduced by the factor decrement and simulation
continues.

• SOLVE SECTION

The Solve section defines a sequence of solutions to be

obtained by the solver. To simulate the Id–Vg characteristic, it is
necessary to ramp the gate bias and obtain solutions at a number
of points. By default, the size of the step between solutions points
is determined by Sentaurus Device. As the simulation proceeds,
output data for each of the electrodes (currents, voltages, and
charges) is saved to the current file after each step and, therefore,
the electrical characteristic is obtained. This can be plotted using
Inspect. The Solve section is shown below.

Solve {
Poisson
Coupled {Poisson Electron}
Quasistationary (Goal {Name="gate” Voltage=2})
{Coupled {Poisson Electron} }
}
Poisson
This specifies that the initial solution is of the nonlinear Poisson
equation only. Electrodes have initial electrical bias conditions as
defined in the Electrode section.
Coupled {Poisson Electron}
The second step introduces the continuity equation for electrons,
with the initial bias conditions applied. In this case, the electron
current continuity equation is solved fully coupled to the Poisson
equation, taking the solution from the previous step as the initial
guess. The fully coupled or ‘Newton’ method is fast and converges
in most cases.
Quasistationary (Goal {Name="gate" Voltage=2})
{Coupled {Poisson Electron}}
}
The Quasistationary statement specifies that quasi-static or
steady state ‘equilibrium’ solutions are to be obtained. A set of
Goals for one or more electrodes is defined in parentheses. In this
case, a sequence of solutions is obtained for increasing gate bias
up to and including the goal of 2 V. A fully coupled (Newton)
method for the self-consistent solution of the Poisson and electron
continuity equations is specified in braces. Each bias step is solved
by taking the solution from the previous step as its initial guess. If
Extrapolate is specified in the Math section, the initial guess for
each bias step is calculated by extrapolation from the previous two
solutions.
During a Solve statement, Sentaurus Device tries to
determine the value of an equation variable, such that the
computed update ∆x (after kth nonlinear iteration) is small enough:
∆x
x*
<1 (8.13)
x
εR ε +A
x*
where εR = −
10 Digits and x* is a scaling constant. For large
values of x, the conditions equation 4.13 is equivalent to the
relative error criterion:
 ∆x
<εR (8.14)
x
Conversely, for small values of x, the absolute error conditions are:
∆x
<εA (8.15)
x*
Sentaurus Device uses the expression to ensure a smooth
transition between absolute and relative error control.

8.5 INSPECT:

Inspect is a versatile tool for efficient viewing of XY plots such as

doping profiles and I-V curves. Inspect extracts parameters such as
junction depth, threshold voltage and saturation currents from the
respective XY plot. Users can manipulate curves interactively by
using scripts. Inspect features a large set of mathematical functions
for curve manipulation such as differentiation, integration and to
find min/max. The inspect script language is open to Tcl and
therefore inherits all the power and flexibility of Tcl.

To start inspect, at the command line type: inspect

Parameter extractions are an integral part of device simulation. In

this section, scripts for extracting standard electrical parameters
based on the result of CMOS and BJT simulations are presented.
These scripts can be directly loaded into Inspect and, with
appropriate input data, Inspect calculates and reports the results
about the required parameters. All the scripts presented here can
be downloaded by following the appropriate link at the end of each
subsection.
Fig. 8.10 Graphical user interface of inspect showing output
curves
Fig. 8.10 Graphical user interface of inspect create curves dialog
box

To run the script from the command line, use:

> inspect -f inspect Script . cmd

Where, inspect Script . cmd is the name of the script file.

This command opens the Inspect GUI while executing the script.
The results from the extraction are sent to the standard output
terminal, usually the command window in which the inspect
command was invoked.

To suppress the display of the Inspect GUI, run the script in batch
mode as:

> inspect -batch -f inspect Script . cmd

The script can also be loaded into and run from an existing Inspect
GUI: Script > Run Script.

For easier reading of the script, lines are color coded:

• Gray: Comment.
• Blue: Standard Inspect code related to loading and plotting
the curve.
• Red: Inspect code specific to the extraction.
• Green: Lines that may need to be changed before using this
script in conjunction with a different data file (for example, to
update the data file name).

Maximum gm Threshold Voltage: Vtgm

# Definition: Threshold voltage defined as the intersection of
# the tangent at the maximum conductance (gm) point with the
# gate voltage (Vg) axis.
# Required input: IdVg curve, simulated with Vd<0 and Vg=0-Vdd.
# Output: Vtgm and the IdVg curve if the Inspect GUI is running.
# Note: The input file for this script is IdVg_lin_des.plt. Change
# it into your own file before running the script.
# (The ft_scalar call is needed for the parameter extraction under
# Sentaurus Workbench)

# Start of the script

set ProjectName "IdVg_Vtgm"

set CurveName "IdVg"

proj_load IdVg_lin_des.plt $ProjectName

cv_createDS $CurveName "$ProjectName gate OuterVoltage"\

"$ProjectName drain TotalCurrent" y
cv_abs $CurveName y
cv_setCurveAttr $CurveName "IdVg" red solid 2 none 3 defcolor 1
defcolor
gr_setAxisAttr X {Gate Voltage (V)} 12 {} {} black 1 10 0 5 0
gr_setAxisAttr Y {Drain Current (A/um)} 12 {} {} black 1 10 0 5 0

# Get location of maximum transconductance

set gm_index [cv_compute\
"veczero(diff(<$CurveName>)-vecmax(diff(<$CurveName>)))" \
AAAA]
# Create tangent on IdVg curve at max gtm point
cv_createWithFormula Tangent\
"tangent(<$CurveName>,$gm_index )" A A A A
# Extract Vt as zero crossing of tangent
set Vtgm [cv_compute "vecvalx(<Tangent>, 0)" A A A A ]

# Write extracted values

puts "Vtgm=[format %.3f $Vtgm] V"
ft_scalar Vtgm [format %.3f $Vtgm]

# End of the script

Download the Inspect script and the corresponding data file by
right-clicking the respective links and using Save Target As:

• Vtgm_ins.cmd
• IdVg_lin_des.plt
Run it with:
> inspect -f Vtgm_ins.cmd

Fig. 8.11 Extraction of the threshold voltage using the drain

current versus gate
voltage curve

8.6 TECPLOT:
Tecplot SV is software for scientific visualization that has been
extended by Synopsys to accommodate the special
requirements of the Synopsys simulation environment.

Tecplot SV can be started at the command prompt without loading

any data file:

> tecplot_sv
Alternatively, Tecplot SV can be launched from within Sentaurus
Workbench. To launch Tecplot SV from Sentaurus Workbench:

• Extensions > Run Tecplot SV.

Fig. 8.12 Main window of Tecplot SV in 2D/3D mode

The main window includes the Synopsys menu bar and sidebar, the
status line, and the Tecplot workspace, which contains a page with
frames. On the bottom of the window is the status line, which
displays useful information such as functions of the mouse-pointed
tool buttons and/or the position of the pointer inside the workspace.
8.6.1 Loading Data Files
Two types of file can be loaded into Tecplot SV:

• The first type is the .tdr file, for example, nmos_mdr.tdr. This
file is used to describe a device structure, its meshing, and
 the values of field quantities existing in the corresponding
device. Many TCAD tools, including Sentaurus Structure
Editor, Mesh, and Sentaurus Device, can read and export
these types of file.
NOTE: In the DF-ISE format, the files that can be loaded are
.grd (for the device structure and its meshing) and .dat (for the
value of field quantities).
• The other type of file is the DF-ISE XY plot file, often with a .plt
extension, for example, n1_des.plt. Datasets included in this
type of file can be used by Tecplot SV to generate XY plots.

To follow this tutorial, right-click the following links and download

the respective files using Save Target As:

• nmos_mdr.tdr
• n1_des.plt

Loading can be performed initially when Tecplot SV is started from

the command line or interactively after Tecplot SV has started.

To start Tecplot SV and simultaneously load data files for a device,

use the following command:

> tecplot nmos_mdr.tdr

To load data files from an open Tecplot SV interface:

• File > Load.

 Fig. 8.13 Read Synopsys file dialog box

8.6.2 Creating Plots

In Tecplot SV, an XY plot can only be generated after both the x
and y axes of the plot have been specified. To generate a plot other
than the default:

1. Select a data file from the Datasets area. All the data groups
included in the selected file are displayed in the pane under
the Datasets area.
2. To show the actual datasets included in each group, click the
group name, for example, gate, which expands the datasets
included in the group in the pane below the group list.
3. To assign a specific dataset to an axis, select the dataset
from the expanded dataset pane and then click one of the
two axis buttons (X1, Y1), which are located below the
dataset list. Note that under the tool window, the current x-
 axis variable is displayed. The variable can be modified by
clicking the button and selecting the new variable.

When the x and y axes of a plot have been specified, Tecplot SV

generates, in a frame, a plot corresponding to the selected
datasets. In some cases, the generated plot may not display
properly because the default range set by Tecplot SV for the axes is
too large.

Fig. 8.14 Id Vg curve: X is set to gate outer voltage and Y is set

to total drain current

8.7 SENTAURUS WORK BENCH

Sentaurus Workbench is the primary graphical front end that
integrates Sentaurus simulation programs into one environment. It
is used throughout the semiconductor industry to design, organize,
and run simulations. Simulations are comprehensively organized
into projects. Sentaurus Workbench automatically manages the
information flow, which includes preprocessing of user input files,
parameterizing projects, setting up and executing tool instances,
and visualizing results. Sentaurus Workbench allows users to define
parameters and variables in order to run comprehensive
parametric analyses. The resulting data can be used with statistical
and spreadsheet software.
8.7.1 Starting Sentaurus Workbench
Before starting Sentaurus Workbench, users must set the STDB
environment variable. This variable is set to a directory path,
usually called DB or STDB, in the home directory of the user.

To set STDB:

Create a directory called DB using the mkdir command in UNIX.

Set the environment variable STDB using one of the following two
sequences of commands:

mkdir DB
setenv STDB /remote/users1/<your_login>/DB
mkdir DB
set STDB=/remote/users1/<your_login>/DB
export STDB

Then, to start Sentaurus Workbench, type: swb

8.7.2 Loading Sentaurus Workbench Projects

To run a project, copy the project from the Examples Library:

1. Open the Examples Library > Getting Started, and select the
project SWB_nmos.
2. Right-click and select Copy.
3. Select the tmp folder, right-click, and select Paste to place
the project in tmp.
4. Open the tmp folder and double-click the project SWB_nmos.
Fig. 8.15 Main widow of Sentaurus work bench showing tool flow,
parameters
and simulation
8.7.3 Calibration
To create a Calibration Kit project or scenario: Calibration >
Project Wizard.

The Project Wizard is displayed (see Figure 5). Follow the

instructions.
 Fig. 8.16 Calibration Kit Project Wizard

To create a short loop experiment for Calibration Kit projects:

Calibration > Process Wizard.
Follow the instructions of the Process Wizard.

To create a Calibration Kit project for optimizing calibration

parameters: Calibration > Optimization Wizard. Follow the
instructions of the Optimization Wizard.

8.8 SUMMARY

An important benefit of using TCAD is that it can help in

understanding how semiconductor devices work. Examination of
detailed device operation, such as how the energy levels and the
carrier (electrons and holes) distribution inside the device varies
with the biasing conditions, can provide valuable insight into the
relationship between a change in process conditions or device
design and the resulting impact on device performance. These
quantities are often difficult to obtain experimentally. In contrast,
they are readily available through computer simulations, which
directly provide feedback and guidance for device design. Moreover
simulations provide a guide line to researchers in fabricating new
novel devices and improve the yield management.

REFERENCES
1. Integrated Systems Engineering (ISE) TCAD Manuals, 2006, Release
10.0
 ______________
CHAPTER

9
________________

CONCLUSION

We have derived a concise analytical threshold voltage model

for the deep submicron asymmetric DG MOSFETs by considering
the distribution of the minority carriers in the silicon channel. The
2-D Poisson equation is solved by considering both the depletion
and the mobile charges in the thin silicon body which proves the
accuracy of the model for both the subthreshold and super
threshold operations. It has also been noticed that the threshold
voltage adjustability is more for the thin silicon channels, thus
providing more flexibility in device designs.
In the second phase, an optimization work on the effect of
the length of the two gate metals M1 and M2 has been carried out
by suitable simulation results. It was observed that the equal
lengths of the two metals are preferred from the point of view of
improved performance as well as photolithographic technique. The
main drawback of this technology is the fabrication procedure that
requires the use of an additional masking step. Also the proper
choice of metals to be selected to get the desired threshold voltage
is of significant concern.
In the next phase, we have demonstrated the effect of gate
engineering technique, the dual metal gate technology on the
analog and the RF performance parameters of undoped symmetric
double gate MOSFETs with gate under lap. This technique seems to
improve the intrinsic gain of the MOS transistor with more
improvement in the subthreshold regime. The cut-off frequency at
strong inversion seems to increase in case of the gate engineered
DG MOSFET by considerable amount that makes it suitable for high
frequency applications.
The fourth phase of the work is based on the study of DG
MOSFETs with lateral asymmetric channel such as the HALO doping
technique. The effect of channel engineering such as the lateral
asymmetric channel is explored on the performance of DG MOSFET.
The length and concentration of the heavily doped region is also
optimized for superior performance. The channel and the gate
engineered DG MOSFETs were compared in terms of the
transconductance, the early voltage, the intrinsic gain, the cut-off
frequency etc. It was found that the channel engineered DG
MOSFET suffers severe mobility degradation at the strong inversion
due to increasing effect of the vertical electric field in the double
gate architecture which becomes dominant with increased doping
density. Compared to that, the gate engineering technique like the
dual metal gate DG MOSFET exhibit improved analog performance
both in the subthreshold as well as in the strong inversion regime.
In the next phase,we have clearly analyzed the effect of
lateral asymmetric halo doping along with dual metal technology
(SHDM) in respect of the digital, analog and RF performance and
compared it with that of a single halo doped DG-MOSFET (SH). The
use of the dual metal gate technology enhances the performances
of the single halo doped DG MOSFET in respect of the
transconductance, the g m / I D ratio, the output impedance and the
intrinsic gain. The improvement is more prominent in the weak
inversion regime thus making it more applicable for low power
subthreshold analog performance.
It is thus concluded that as there is a transition from bulk
CMOS technology to SOI and multigate architectures of thin silicon
channel, the potential of channel engineering technique decreases
considerably due to increasing field dependent mobility
degradation along the channel. On the other hand, the double gate
MOS transistor with the dual metal gate technology that adopts the
same undoped channel with increased carrier transport efficiency
shows improved analog/RF performance parameters compared to
that of the conventional architecture and thus may be suitable for
SoC applications in the nano regime.
• SCOPE OF FUTURE WORKS
 The effect of the gate work-function and the channel
engineering implemented on the multigate devices can be
extended to the realization of different analog circuits like the
operation amplifiers. The other different analog parameters
like the linearity, noise parameter etc. can be analyzed for
both the gate and the channel engineering method in the sub
100nm regime. Different high frequency circuits can also be
implemented with these advanced DG MOS devices. The
advanced DG/SOI devices can be explored in the 45 nm gate
length regime for improved RF performance.

 The effect of mobility degradation in case of the channel

engineering technique can be modeled by suitable
mathematical approach in case of shorter gate length and
ultra thin channel below 20nm taking into account the effects
of phonon scattering. The gate engineering technique that
shows increased electric field along the channel may exhibit
mobility degradation due to the velocity saturation effects.
This may lead to an interesting modeling approach of the
gate engineered DG MOSFETs.

 Performance analysis of sub 25 nm Double gate MOSFETs in

the analog and RF regime will be an interesting study.

 The effects of gate resistance and source/drain resistance on

the performance of advanced DG MOSFETS for RF
applications need to be explored.