Description

A 4-bit synchronous counter built from D-flipflops with carry-input (count-enable) and
carry-output. In this circuit, the single clock signal is directly connected to all flipflops, so
that all flipflops change state at the same time.
lick the clock and nreset input switches or type the !c! (clock), !r! (reset), and !"! (carry-in)
bindkeys to operate the counter.
#b$iously, this counter consists of four identical stages with a D-type flipflop, an %#&-gate,
and a two-input A'D-gate each. (he %#&-gate in front of the D input of the flipflop
basically con$erts the D-type flipflop into a toggle ((-type) flipflop. (his is the same
structure as the )*-flipflop with both ) and * tied to logical-+, as shown in the pre$ious
applet.
,hile the carry-logic shown in the pre$ious applet re-uired an n-input A'D gate for stage n,
the carry-chain used in this applet is based on two-input gates. (he difference in structure is
similar to the carry-lookahead and the ripple-carry adders shown in the pre$ious chapter.
#b$iously, the output of any A'D gate is only high when all lower stage A'D gates (and the
carry input) are also high.
In other words,
D
n
= Q
n
XOR (Q
n-1
AND Q
n-2
AND ... AND Q
1
AND Q
0
AND carry_in)
.rint $ersion / &un this demo in the 0ades editor ($ia )a$a ,eb1tart)2sage / 3A4 / About /
5icense / 3eedback / (utorial (.D3) / &eferen6karte (.D3, in 7erman) Impressum http899tams-
www.informatik.uni-hamburg.de9applets9hades9webdemos9:;-counters9:;-sync9sync-dff.html