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Full Adder Design Using LEDIT
Full Adder Design Using LEDIT
Full Adder Design Using LEDIT
The purpose of this assignment is to introduce an essential component to binary computation - a full adder. For simplification the single bit full adder
will be considered (from which the device can be scaled to multiple bits). Input-to-Sum and Carry-in to Carry-out timing restrictions are also factored
into this sizing consideration.
The (non-optimized) full adder's functionality using MUX is summarized in Figure below.
The behavioral description focuses on block behavior. Figure 7 shows how two instances of the same building block, the half adder, can be used to
implement a full adder using a structural approach.
Exercise: Show that the sum function can be written as shown at left
This alternate representation of the sum function allows the 1-bit full adder to be implemented in complex CMOS with 28 transistors, as shown
at left below.
Carry_out internal node is used as an input to the adder complex CMOS gate
Exercise: Show that the two P-trees in the complex CMOS gates of the carry_out and sum are optimizations of the proper dual
derivations from the two N-tree networks.
HOW THE
SUM
SUM
[AAB + AAC + ABC + ABB + ABC + BBC + ABC +ACC + BCC + ABC]
[(AB+BC+AB).(A+B+C) + ABC]
(AB+BC+AB).(A+B+C) + ABC
Finally, Fig. above shows the circuit diagram of a CMOS one-bit full adder. The circuit has three inputs, and two outputs, sum and carry_out. All input
and output signals have been arranged in vertical polysilicon columns. Notice that both the sum-circuit and the carry-circuit have been realized using one
uninterrupted active area each.
<PMOS Capacitor>
<NMOS Capacitor>
<PCAP Capacitor>
<subs>
<allsubs>
<Metal1>
<poly wire>
<pcap wire>
<Metal2>
<LPNP emitter>
<LPNP collector>
<POLY_CAP1>
* Warning:
<Pad Comment>
<NMOS Capacitor>
<PMOS Capacitor>
<PCAP Capacitor>
<ndiff>
<pdiff>
<subs>
<allsubs>
<Metal1>
<poly wire>
<pcap wire>
<Metal2>
<LPNP emitter>
<LPNP collector>
<POLY_CAP1>
13 = Ain (-22.5 , 3)
Cpar1 1 0 C=8.744f
Cpar2 6 0 C=17.488f
Cpar3 7 0 C=7.168f
Cpar4 8 0 C=27.048f
* Warning: Node 11 has zero nodal parasitic capacitance.
Cpar5 12 0 C=8.744f
$ (92 6 94 14)
$ (117 -35 119 -31)
$ (142 -35 144 -31)
$ (83 -35 85 -31)
$ (41 6 43 14)
$ (69 6 71 14)
$ (55 6 57 14)
$ (16 6 18 14)
* Total Nodes: 21
* Total Elements: 37
* Total Number of Shorted Elements not written to the SPICE file: 0
* Output Generation Elapsed Time: 0.000 sec
* Total Extract Elapsed Time: 2.371 sec
.END
Cell0
Version 1.02
mamin08.ext
09/18/2013 - 21:37
13 = Ain (-22.5 , 3)
VDD 16 0 5
VGND 17 0 0
Cpar1 1 0 C=8.744f
Cpar2 6 0 C=17.488f
Cpar3 7 0 C=7.168f
Cpar4 8 0 C=27.048f
* Warning: Node 11 has zero nodal parasitic capacitance.
Cpar5 12 0 C=8.744f
* Warning: Node 13 has zero nodal parasitic capacitance.
* Warning: Node 14 has zero nodal parasitic capacitance.
Cpar6 15 0 C=10.288f
Cpar7 16 0 C=34.776f
Cpar8 17 0 C=16.64f
Cpar9 18 0 C=20.608f
* Warning: Node 20 has zero nodal parasitic capacitance.
* Warning: Node 21 has zero nodal parasitic capacitance.
$ (92 6 94 14)
$ (117 -35 119 -31)
$ (142 -35 144 -31)
$ (83 -35 85 -31)
$ (41 6 43 14)
$ (69 6 71 14)
$ (55 6 57 14)
$ (16 6 18 14)
* Total Nodes: 21
* Total Elements: 37
* Total Number of Shorted Elements not written to the SPICE file: 0
* Output Generation Elapsed Time: 0.000 sec
* Total Extract Elapsed Time: 2.371 sec
.END
C:\Users\DhanRajShehrawat\Pictures\FA_1bit.spc
dcap = 2
defnrs = 0 [sq]
defnrb = 0 [sq]
tnom = 25 [deg C]
*
* General options:
*
temp = 25 [deg C]
*
* Output options:
threads = 1
defnrd = 0 [sq]
acout = 1
ingold = 0
*
* Device and node counts:
*
MOSFETs - 28
BJTs - 0
MESFETs - 0
Capacitors - 9
Inductors - 0
* Transmission lines - 0
*
Voltage sources - 5
MOSFET geometries - 32
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Coupled transmission lines - 0
Current sources - 0
VCVS - 0
VCCS - 0
CCVS - 0
CCCS - 0
V-control switch - 0
Macro devices - 0
HDL devices - 0
Subcircuits - 0
Independent nodes - 16
Total nodes - 22
I-control switch - 0
External C model instances - 0
Subcircuit instances - 0
Boundary nodes - 6
*SEDIT: Alter=0
*SEDIT: Analysis types DCOP 0 ACMODEL 0 AC 0 TRANSIENT 1 TRANSFER 0 NOISE 0
*WEDIT: .tran
2e-009
TRANSIENT ANALYSIS
Time<s>
v(1,0)<V>
v(12,0)<V>
v(13,0)<V>
v(14,0)<V>
v(11,0)<V>
0.02 seconds
* Setup
0.09 seconds
* DC operating point
0.06 seconds
* Transient Analysis
0.79 seconds
* Overhead
1.47 seconds
* ----------------------------------------* Total
2.43 seconds
* Simulation completed