S.E. Sem.

III [CMPN]
Digital Logic Design and Applications
Nov. '08 : Mumbai University − Examination Paper Solution
Time : 3hrs] [Marks : 100

N.B. : (1) Question No. 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.
(3) Assume suitable data and state it clearly.

1. (a) Convert (157.63)8 into decimal, binary and hexadecimal system. [4]
Soln.:
(157.63)8
Octal to Decimal :
Step 1 : Get the octal no. 1 5 7 . 6 3
Step 2 : Write corresponding weights 82 81 80 . 8−1 8−2
Step 3 : Multiple columnwise 64 40 7 . 3/4 3/16
3 3
Step 4 : Add the contents of row 3 = 64 + 40 + 7 + + = (111.9375)10
4 16
Octal to Binary :
Step 1 : Get the octal no. 1 5 7 . 6 3
Step 2 : Convert each digits into binary 001 101 111 . 110 011
∴ (157.63)8 = (001 101 111 . 110 011)2

Octal to Hexadecimal :
Step 1 : Convert into binary (0 0 1 1 0 1 1 1 1 . 1 1 0 0 1 1)
Step 2 : Convert binary to hexadecimal (0 0110 1111 . 1100 11)2
Add three zeros on extreme left (on MSB) and
Add 2 zero on extreme right side.
Binary (0000 0110 1111 . 1100 1100) group of 4 bit,
Hexa number 0 6 F . C C
(157.63)8 = (6F.CC)16

1. (b) Simplify using boolean laws : AB + A + AB . [4]

Soln.:
Y = (AB + A + AB)
But AB = A + B … De-Morgan's first theorem
∴ Y = (A + B + A + AB)
But A + A = A (∵ A + A = A)
∴ Y = (A + B + AB)
∴ Y = A.B.AB
But A = A and B = B
∴ Y = A.B.AB
But AB = (A + B) … De-Morgan's first theorem
∴ Y = A.B(A + B) = AAB + ABB
But AA = 0 and BB = 0
∴ Y =0.B+A.0
=0+0 … since 0 . B = 0 and A . 0 = 0
∴ Y =0

1
(2) S.E. − DLDA (CMPN)

1. (c) Design full adder using half adders. [4]

Soln.:
Full Adder using Half Adder :
• The full adder circuit can be constructed using two half adders as shown in fig.1 and the
detail circuit is shown in fig.2.

Fig.1
• A full adder can be implemented using two half adders and the OR gate as shown in fig.2

Fig.2
• Now let us prove that this circuit acts as a full adder.

Proof :
• Refer fig.2 and write the expression for sum output as,
S = (A ⊕ B) ⊕ Cin = A ⊕ B ⊕ Cin
This expression is same as that obtained for the full adder.
• Now write the expression for carry output C0 as
C0 = (A ⊕ B) Cin + AB
C0 = (AB + AB)Cin + AB
= ABCin + ABCin + AB
= ABCin + ABCin + AB(1 + Cin )
= ABCin + ABCin + AB + ABCin
= BCin (A + A) + ABCin + AB
= BCin + ABCin + AB
= BCin + ABCin + AB(1 + Cin )
= BCin + ABCin + AB + ABCin
= BCin + AB + ACin + (B + B)
∴ C0 = BCin + AB + ACin
• This expression is same that for a full adder. Thus we have proved that circuit shown in fig.2
really behaves like a full adder.

Applications of Full Adder :

• The full adder acts as the basic building block of the 4 bit/8 bit binary/BCD adder ICs such as
7483.

2
 Examination Paper Solution (3)

1. (d) State and prove De Morgan's theorem. [4]

Soln.:
De Morgan's theorem :
The two theorems suggested by De-Morgen and which are extremely useful in Boolean algebra
are as follows :

Theorem 1 : AB = A + B : NAND = Bubbled OR

• This theorem states that the complement of a product is equal to addition of the complements.
• This rule is illustrated fig.1. The left hand side (LHS) of this theorem represents a NAND
gate with inputs A and B whereas the right hand side (RHS) of the theorem represents an OR
gate with inverted inputs.
• This OR gate is called as "Bubbled OR". Thus we can state De-Morgans first theorem as,
NAND = Bubbled OR

Fig.1 : Illustration of De-Morgan's first theorem.

This theorem can be verified by writing a truth table as shown in fig.2.

A B AB A B A+B
0 0 1 1 1 1
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 0 0 0
LHS AB + A + B RHS
Fig.2 : Verification of the theorem AB = A + B

Theorem 2 : A + B = A.B : NOR = Bubbled AND

• The LHS of this theorem represents a NOR gate with inputs A and B whereas the RHS
represents an AND gate with inverted inputs.
• This AND gate is called as "Bubbled AND". Thus we can state De-Morgan's second theorem as :
NOR = Bubbled AND

Fig.3 : Illustration of De-Morgan's second theorem.

• This theorem can be verified by writing a truth table for both the sides of the theorem
statement. This truth table is shown in fig.4, which shows that LHS = RHS.
A B A+B A B A.B
0 0 1 1 1 1
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 0
LHS A + B = A.B RHS
Fig.4 : Truth table to verify De-Morgan's theorem

3
(4) S.E. − DLDA (CMPN)

1. (e) Implement the boolean function with NAND – NAND logic, F (A, B, C) = ∑ m(0, 1, 3, 5). [4]

Soln.:
F (A, B, C) = ∑ m (0, 1, 3, 5)
∴ F (A, B, C) = B0 + B1 + B + B5
(1) Prepare K-map
BC BC BC BC BC
A 00 01 11 10
3
A 0 1 1 1 0
1 0 1 3 2

L 1 0 1 0 0
4 2 5 7 6

(2) Write the minizal logical expression

∴ F (A, B, C) = A B + BC + AC
Logic Diagram :
Step 1 : Implementing the given expression using AND-OR-NOT logic.
The implementation using AND-OR-NOT gate as shown in figure.
A B C

F (A, B, C)

Step 2 : Convert AND-OR-NOT into NAND-NAND logic

Replace every AND by NAND
every OR by a bubbled OR
every inverter by a NAND inverter to get the NAND-NAND logic
A B C

F (A, B, C)

Step 3 : Draw circuit using only NAND gate,

A B C

F (A, B, C)

4
 Examination Paper Solution (5)

2. (a) Using boolean laws, prove NAND and NOR gates as universal gates. [10]

Soln.:
• The NAND and NOR gates are called as "Universal Gates" because it is possible to
implement any Boolean expression with the help of only NAND or only NOR gates.
• Hence a user can build any combinational circuit with the help of only NAND gates or only
NOR gates.
• This is a great advantage because a user will have to make a stock of only NAND or NOR
gate ICs.

Universal Property
NAND Gate
The NAND gate can be used to generate the NOT function, the AND function, the OR function,
and the NOR function.

NOT Function:
An inverter can be made from a NAND gate by connecting all of the inputs together and creating,
in effect, a single common input, as shown in Fig. 1, for a two−input gate:

Fig. 1: NOT function using NAND gates

AND Function :
An AND function can be generated using only NAND gates. It is generated by simply inverting
output of NAND gate; i.e. AB = AB. Fig. 2 shows the two input AND gate using NAND gates.

Fig. 2 : AND function using NAND gates

A B AB A B AB AB
0 0 0 0 0 1 0
0 1 0 ≡ 0 1 1 0
1 0 0 1 0 1 0
1 1 1 1 1 0 1
Table : Truth Table

OR Function :
OR function is generated using only NAND gates as follows : We know that Boolean expression
for OR gate is
Y =A+B

5
(6) S.E. − DLDA (CMPN)

= A+B Rule 9 : [A = A]
= A.B DeMorgan’s Theorem 1

The above equation is implemented using only NAND gates as shown in the Fig. 3.

Fig. 3 : OR function using only NAND gates

Note : Bubble at the input of NAND gate indicates inverted input.

A B A+B A B A.B A.B

0 0 0 0 0 1 0
0 1 1 ≡ 0 1 0 1
1 0 1 1 0 0 1
1 1 1 1 1 0 1

Table : Truth table

NOR Function :

NOR function is generated using only NAND gates as follows : We know that Boolean
expression for NOR gate is

Y = A+B
= A. B
= A. B DeMorgan’s Theorem 2
Rule 9 : [ A = A ]

The above equation is implemented using only NAND gates, as shown in the fig. 4.

Fig. 4 : NOR function using only NAND gates

6
 Examination Paper Solution (7)

A B A+B A B A.B A.B A.B

0 0 1 0 0 1 0 1
0 1 0 ≡ 0 1 0 1 0
1 0 0 1 0 0 1 0
1 1 0 1 1 0 1 0
Table : Truth Table

NOR Gate
Similar to NAND gate, the NOR gate is also a universal gate, since it can be used to generate the
NOT, AND, OR and NAND functions.

NOT Function :
An inverter can be made from a NOR gate by connecting all of the inputs together and creating,
in effect, a single common input, as shown in Fig. 5.

Fig. 5 : NOT function using NOR gate

OR Function :
An OR function can be generated using only NOR gates. It can be generated by simply inverting
output of NOR gate; i.e. A + B = A + B. Fig. 6 shows the two input OR gate using NOR gates.

Fig. 6 : OR function using NOR gates

A B A+B A B A+B A+B

0 0 0 0 0 1 0
0 1 1 ≡ 0 1 0 1
1 0 1 1 0 0 1
1 1 1 1 1 0 1
Table : Truth table

AND Function :
AND function is generated using only NOR gates as follows : We know that Boolean expression
for AND gate is
Y = A. B
= A.B Rule 9 : [ A = A ]
= A+B DeMorgan’s Theorem 2

The above equation is implemented using only NOR gates as shown in the Fig. 7.

7
(8) S.E. − DLDA (CMPN)

Fig. 7 : AND function using NOR gates

Note : Bubble at the input of NOR gate indicates inverted input.

A B A+B A B A+B A+B

0 0 0 0 0 1 0
0 1 0 ≡ 0 1 1 0
1 0 0 1 0 1 0
1 1 1 1 1 0 1

Table : Truth table

NAND Function :
NAND function is generated using only NOR gates as follows : We know that Boolean
expression for NAND gate is
Y = A.B
= A+B DeMorgan’s Theorem 1
= A+B Rule 9 : [ A = A ]

The above equation is implemented using only NOR gates, as shown in the Fig. 8.

Fig. 8 : NAND function using only NOR gates

A B A+B A B A+B A+B A+B

0 0 1 0 0 1 0 1
0 1 1 ≡ 0 1 1 0 1
1 0 1 1 0 1 0 1
1 1 0 1 1 0 1 0

Table : Truth table

8
 Examination Paper Solution (9)

2. (b) Draw 3-bit binary up-down counter and explain the operation. [10]

Soln.:
• The requirements of counter are :
1. 3-bit : Hence three FFs are required.
2. UP/DOWN : So a mode control input is essential.
• We know that for a ripple up counter, the Q output of preceding FF is connected to the clock
input of the next one.
• And for a ripple down counter, the Q output of the preceding FF is connected to the clock
input of the next one.
• Let the selection of Q or Q output of the preceding FF be controlled by the mode control
input M such that,
If M = 0 … UP counting. So connect Q to CLK
If M = 1 … DOWN counting. So connect Q to CLK
• Let us design a combinational logic to satisfy all the requirements stated above.

Truth table of combinational circuit :

The truth table of such a combinational circuit is shown table 1.

Inputs Outputs
M Q Q Y
0 0 0 0
Y=Q
0 0 1 0
for up
0 1 0 1
counting
0 1 1 1
1 0 0 0 Y= Q
1 0 1 1
for down
1 1 0 0
counting
Fig.(a) : Block diagram of 1 1 1 1
combinational circuit Table 1 : Truth table.

K-map and simplified expression for output :

Fig.(b) shows the K-map and simplified expression for Y.

Logic diagram for combinational circuit :

The logic diagram for the combinational circuit is shown in figure (c).

QQ
M 00 01 11 10 MQ
0 0 0 1 1
1 0 1 1 0
Expression for Y : MQ
Y = MQ + MQ
Fig.(b) : K-map for Y. Fig.(c)

Logic diagram of a 3-bit up/down counter :

The combinational circuit is connected between every pair of flip-flops to obtain the 3-bit
up/down counter as shown in figure (d).

9
(10) S.E. − DLDA (CMPN)

Fig.(d) : A 3-bit up/down ripple counter.

Operation of 3-bit up down ripple counter :

1. With M = 0 (Up counting mode) :
• If M = 0 and M = 1, then the AND gates 1 and 3 in figure (d) will be enabled whereas the
AND gates 2 and 4 will be disabled.
• Hence QA gets connected to the clock input of FF-B and QB gets connected to the clock input of FF-
C.
• These connections are same as those for the normal up counter. Thus with M = 0 the circuit
works as an up counter.
2. With M = 1 (Down counting mode ) :
• If M = 1, then AND gates 2 and 4 in figure (d) are enabled whereas the AND gates 1 and 3 are
disabled.
• Hence Q A gets connected to the clock input of FF-B and Q B gets connected ot the clock input of
FF-C.
• As discussed earlier, these connections will produce a down counter. Thus with M = 1 the
circuit works as a down counter.

3. (a) What is race condition ? How it is overcome in Master-slave J-K flip flop ? Explain. [10]

Soln.:
• The "Race Around Condition" that we are going to explain occurs when J = K = 1 i.e. when
the latch is in the toggle mode.
• Refer figure 1 which shows the waveforms for the various modes, when a rectangular
waveform is applied to the "Enable" input

Fig.1 : Waveforms for various modes of a JK latch.

10
 Examination Paper Solution (11)

Interval t0-t1 :
• During this interval J = 1, K = 0 and E = 0.
• Hence the latch is disabled and there is no change in Q.

Interval t1-t2 :
• During this interval J = 1, K = 0 and E = l.
• Hence this is a set condition and Q becomes 1.

Interval t2-t3 : Race Around

• At instant t2, J = K = 1 and E = 1 Hence the JK latch is in the toggle mode and Q becomes
low (0) and Q = l.
• These changed outputs get applied at the inputs of NAND gates 3 and 4 of the JK latch. Thus
the new inputs to Gates 3 and 4 are :
NAND-3 : J = 1, E = l, Q = 1
NAND-4 : K = 1, E = 1, Q = 0.
• Hence R' will become 0 and S' will become 1.
• Therefore after a time period corresponding to the propagation delay, the Q and Q outputs
will change to, Q = 1 and Q = 0.
• These changed output again get applied to the inputs of NAND-3 and 4 and the outputs will
toggle again.
• Thus as long as J = K = 1 and E = 1, the outputs will keep toggling indefinitely as shown in figure
1. This multiple, toggling in the J-K latch is called as Race Around condition. It must be
avoided.

Interval t3-t4 :
• During this interval J = 0, K = 1 and E = 1. Hence it is the reset condition.
• So Q becomes zero.

Master Slave JK Flip-Flop :

• Figure 2 shows the master slave JK flip flop.

• It is a combination of a clocked JK latch and clocked SR latch.
• The clocked JK latch acts as the master and the clocked SR latch acts as the slave.
• Master is positive level triggered. But due to the presence of the inverter in the clock line, the
slave will respond to the negative level.
• Hence when the clock = 1 (positive level) the master is active and the slave is inactive.
Whereas when clock = 0 (low level) the slave is active and the master is inactive.

Fig.2 : Master Slave JK Flip Flip.

• Table 1 gives truth table of master slave JK flip flop.

11
(12) S.E. − DLDA (CMPN)

Table 1 : Truth table of master slave JK flip flop.

Inputs Outputs
Case Remark
CLK J K Qn + 1 Qn +1
I × 0 0 Qn Qn No change
II (1) 0 0 Qn Qn No change
III (1) 0 1 0 1 Reset
IV (1) 1 0 1 0 Set
V (1) 1 1 Qn Qn Toggle

Operation :
• We will discuss the operation of the master slave JK FF with reference to its truth table.
• We must always remember one important thing that in the positive half cycle of the clock, the
master is active and in the negative half cycle, the slave its active. This is shown in figure 3.

Fig.3

Case 1 : Clock = ×, J = K = 0
(i) For clock = 1, the master is active, slave inactive. As J = K = 0. Therefore, outputs of master i.e. Q
and Q1 will not change. Hence the S and R inputs to the slave will remain unchanged.
(ii) As soon as clock = 0, the slave becomes active and master is inactive. But since the S and R
inputs have not changed, the slave outputs will also remain unchanged.
∴ he outputs will not change if J = K = 0.

Case 2 : Clock = ,J=K=0

This condition has been already discussed in case 1.

Case 3 : Clock = , J = 0 and K = 1

• Clock = 1: Master active, slave inactive.
• Therefore, outputs of the master become Q1 = 0 and Q1 = 1. That means S = 0 and R= 1.
• Clock = 0: Slave active, master inactive.
• Even with the changed outputs Q = 0 and Q = 1 fed back to master, its outputs will Q1 = 0
and Q1 = 1. That means S = 0 and R = 1.
• Hence with clock = 0 and slave becoming active, the outputs of slave will remain Q = 0 and
Q1 = 1.
• Thus we get a stable output from the Master slave.

Case 4 : Clock = , J = 1 and K = 0

• Clock = 1 : Master active, slave inactive.
∴ outputs of master become Q1 = 1 and Q1 = 0, i.e., S = 1, R = 0.
• Clock = 0 : Master inactive, slave active.
∴ outputs of slave become Q = 1 and Q = 0.
• Again if clock = 1 then it can be shown that the outputs of the slave are stabilized to Q = 1
and Q = 0.

12
 Examination Paper Solution (13)

Case 5 : Clock = , J = 1 and K = 1

• Clock = 1 : Master active, slave inactive.
∴ outputs of master will toggle. So S and R also will be inverted.
• Clock = 1 : Master inactive, slave active.
∴ outputs of the slave will toggle.
• These changed output are returned back to the master inputs.
• But since clock = 0, the master is still inactive. So it does not respond to these changed outputs.
• This avoids the multiple toggling which leads to the race around condition. Thus the master
slave flip flop will avoid the race around condition.
• The waveforms for the master slave flip flop are shown figure 4.

Fig.4 : Waveforms of master slave JK flip flop

Observations from the waveforms :

• We can make the following important observations from the waveforms of the master slave
JK FF.
• The slave always follows the master, after a delay of half clock cycle period.
• The multiple toggling or the race around condition is successfully avoided.

3. (b) State truth table of 3-bit gray to binary conversion and design using 3 : 8 decoder and additional
gates. [10]

Soln.:
A gray number can be converted to binary step by step as follows.
Step I : MSB bit is kept as it is.
Step II : This bit is EX−ORed (added) with next bit from gray code.
Step III : The resulting bit in step II is EX−ORed with next bit from gray code.
Step IV : Step III is repeated till you reach LSB.

13
(14) S.E. − DLDA (CMPN)

We will talk in terms of B3 B2 B1 B0 and G3 G2 G1 G0. Let’s say given gray code is G3 G2 G1 G0
(Refer table for EX−OR table 23).
(a) B3 (binary MSB) = G3 (MSB as it is)
(b) B3 bit should be EX−ORed with next of gray, means B3 ⊕ G2, this will give B2,
∴B2 = B3 ⊕ G2.
(c) Resulting bit in step II is B2, is EX−ORed with next bit from gray i.e. G1, i.e. B2 ⊕ G1. The
resulting bit is B1, B2 ⊕ G1 = B1.
(a) Step III Continued
∴B0 = B1 ⊕ G0.
Now we reached LSB so stop. The above procedure graphically represented as follows.
MS LSB
Gray G G2 G1 G

⊕ ⊕ ⊕
Binary Code B3 B2 B1 B0
(MSB (LSB)
)
Let’s take one example to understand the same convert 0 1 0 1 gray to equivalent binary.
MS LSB
Gray 0 1 0 1

⊕ ⊕ ⊕
Binar 0 1 1 0
MSB
B3 B2 B1 B0
B3 = G3 = 0.
B2 = B3 ⊕ G2 = 0 ⊕ 1 = 1
B1 = B2 ⊕ G1 = 1 ⊕ 0 = 1
B0 = B1 ⊕ G0 = 1 ⊕ 1 = 0
∴gray 0 1 0 1 ⇒ 0 1 1 0 binary.
Note : The same conversion you can perform by “Addition” method. For addition refer table 24.

The code conversion from gray to binary is given in following table.

Gray Binary
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

14
 Examination Paper Solution (15)

Figure (a) shows 3-to-8 line decoder. Here, 3 inputs are decoded into eight outputs, each output
represent one of the minterms of the 3-input variables. The three inverters provide the
complement of the inputs, and each one of the eight AND gates generates one of the minterms.
Enable input is provided to activate decoded output base don data inputs A, B and C. The table
shows the truth table for 3 to 8 decoder.

Table : Truth table for a 3-to-8 decoder.

Inputs Outputs
EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

Fig.: 3 : 8 line decoder.

15
(16) S.E. − DLDA (CMPN)

4. (a) Simplify using K-map, f (A, B, C, D) = π M (0, 2, 3, 6, 7, 8, 9, 12, 13). Write simplified SOP and
POS equations and draw logical diagram using NAND gates only. [10]

Soln.:
f (A, B, C, D) = π M (0, 2, 3, 6, 7, 8, 9, 12, 13)
(1) The given expression,
y = M0 M2 M3 M6 M7 M8 M9 M12 M13

(2) In K-map enter 0's corresponding to these mixtures and enter is in the viewing cells as shown
in figure and group the zero, as show in figure for the further simplification.

CD CD CD AB CD
AB 00 01 11 10
AB 00 0 1 0 0
0 1 3 2

AB 01 1 1 0 0
4 5 7 6

AB 11 0 0 1 1
12 13 15 14

AB 10 0 0 1 1
8 9 11 10

SOP, y = AC + ACD + ABC

POS, y = (A + C) (A + C) (B + C + D)

Logic Diagram :
Step 1 :
A B C D

Step 2 : Convert AND-OR-NOT into NAND-NAND logic

Replace every AND by NAND
every OR by a bubbled OR
every inverter by a NAND inverter to get the NAND-NAND logic

A B C D

16
 Examination Paper Solution (17)

Step 3 : Draw circuit using only NAND gates :

A B C D

4. (b) Simplify the function using Quine McClusky method, f (A, B, C, D) = ∑ m (4, 5, 8, 9, 11, 12, 13,
15). Draw the logical diagram using NAND gates. [10]
Soln.:
(1) Arrays all minterms according to the number of 1's and group are form as one 1's, two 1's,
etc., as shown in table.
Group Minterm A B C D
1 4 0 1 0 0
8 1 0 0 0
2 5 0 1 0 1
9 1 0 0 1
12 1 1 0 1
3 11 1 0 1 1
13 1 1 0 1
4 15 1 1 1 1
Table (a)
(2) Combine the minterms into a group of two :
• Table shows the matched pairs of minterms in the adjacent groups of table (a) which
differ at only one location (bit position) with respect to each other. Place (
) mark on the
matched pairs in table (a).
• The bit position where the minterms differ are represented by dashes (−) in the new terms
written in front of matched pairs.
Group Minterm A B C D
1 4−12 − 1 0 0

8−12 1 − 0 0

2 5−13 − 1 0 1

9−11 1 0 − 1

8−13 1 − 0 1

12−13 1 1 0 −
3 11-15 1 − 1 1

13−15 1 1 − 1

Table (b)

(3) Combine the minterm pairs into groups of four (Quad) :

Group the minterm pairs of table (b) (adjacent groups) to form minterm quads as shown in table
(c) and place a (
) mark on the matched pairs in table (b).
Group Minterm A B C D
1 4−12−5−13 − 1 0 −
8−12−9−13 1 − 0 −
2 9−11−13−15 1 − − 1
9−13−11−15 1 − − 1
Table (c)
17
(18) S.E. − DLDA (CMPN)

No further grouping is possible after this. So the process of grouping stops here.

(4) Collect all nonchecked terms :

Collect all the nonchecked (non-tick marked) terms from tables (a), (b) and (c), because they
are the prime implicants (PI)
∴ y = AD + BC + AC + ABC

(5) Prepare the PI table and obtain the EPIs :

The PI table is shown in table (d).

Decimal number Give Minterms

PI
corresponding to PI 4 5 8 9 11 12 13 15
ABC 12, 13 × ×
AD 9, 11, 13, 15 × × × ×
BC 4, 5, 12, 13 × × × ×
AC 8, 9, 12, 13 × × × ×
Table (d)

(6) In the PI table find the columns containing only 1 cross (×) and encircle those (×) marks. Put
(
) mark in front of the corresponding PIs.
These (
) marked prime implicants in table (d) are the essential prime implicants (EPIs).
Hence the simplified expression for F is
F (A, B, C, D) = BC + AD + AC

Logic Diagram :
Step 1 : A B C D

Step 2 : Convert AND-OR-NOT into NAND-NAND logic

Replace every AND by NAND
every OR by a bubbled OR
every inverter by a NAND inverter to get the NAND-NAND logic

A B C D

18
 Examination Paper Solution (19)

Step 3 : Draw circuit using only NAND gates :

A B C D

5. (a) Draw a 2-input TTL NAND gate and explain its operation. [10]

Soln.:
• A two input TTL-NAND gate is shown in Figure 1. A and B are the inputs while Y is the
output terminal of this NAND gate.

Operation :
• In order to understand the operation of this circuit, let us replace transistor Q1 by its
equivalent circuit shown in Figure 2.
1. A and B are the input terminals. The input voltages A and B can be either LOW (zero
volts ideally) or HIGH (+ VCC ideally).
2. A and B both LOW : If A and B both are connected to ground, then both the B-E
junctions of transistor Q1 are forward biased.

• Hence diodes D1 and D2 in Figure 2 will conduct to force the voltage at point C in Figure 3 to
0.7V.

Fig. 1 : Two input TTL NAND gate Fig. 2 : Transistor Q1 is replaced by its
equivalent

• This voltage is insufficient to forward bias-emitter junction of Q2. Hence Q2 will remain OFF.
• Therefore its collector voltage VX rises to VCC.
• As transistor Q3 is operating in the emitter follower mode, output Y will be pulled up to high
voltage.
∴ Y = 1(HIGH) ….For A = B = 0 (LOW)
• The equivalent circuit for this input condition is shown in Figure 3(a).

19
(20) S.E. − DLDA (CMPN)

(a) Equivalent circuit for A = B = 0 (b) Equivalent circuit for A = 1, B = 0

Fig. 3
Either A or B LOW :If nay one input (A or B) is connected to ground with the other terminal
left open or connected to +VCC’ then the corresponding diode (D1 or D2) will conduct.
• This will pull down the voltage at “C” to 0.7V.
• This voltage is insufficient to turn ON Q2. So it remains OFF.
• So collector voltage VX of Q2 will be equal to VCC. This voltage acts as base voltage for Q3.
• As Q3 acts as an emitter follower, output Y will be pulled to VCC.
∴Y = 1 if A = 0 and B = 1
if A = 1 and B = 0
• The equivalent circuit for this mode is shown in Figure 3(b).

A and B both HIGH : If A and B both are connected to +VCC’ then both the diodes D1 and D2
will be reverse biased and do not conduct.
• Therefore diode D3 is forward biased and base current is supplied to transistor Q2 via R1 and
D3 .
• As Q2 conducts, the voltage at X will drop down and Q3 will be OFF, whereas voltage at Z
(across R3) will increase to turn ON Q4.
• As Q4 goes into saturation, the output voltage Y will be pulled down to a low voltage.
• The equivalent circuit for this mode of operation is shown in Figure 4.
• This discussion reveals that the circuit operates as a NAND gate.

Fig. 4 : Equivalent circuit for A = B = 1

20
 Examination Paper Solution (21)

5. (b) Simplify F (P, Q, R, S) = π M (3, 4, 5, 6, 7, 10, 11, 15) and implement using minimum no. of
gates. [10]

Sol.:
1) The given Expression
y = M3 M4 M5 M6 M7 M10 M11 M15

2) In K map enter 01, corresponding mixtures and enter 1’s in the remaining as shown in figure
and Group the zero1, as shown in figure below for the further simplification.

CD CD CD CD CD
AB 00 01 11 10
A B 00 0
0 1 3 2

A B 01 0 0 0 0
4 5 7 6

AB 11 0
12 13 15 14

A B 10 0 0
8 9 11 10

y = (A + B) (C + D) (A + B + C + D)

3) Logic Diagram
A B C D

6. (a) Design MOD−6 synchronous counter and explain its operation. [10]

Soln.:

For designing mod 6 counter using the formula

2n ≥ N
Here N = 6
∴ n =3 i.e., 3 flip-flops are required.

21
(22) S.E. − DLDA (CMPN)

Excitation table for T Flip-flop.

Qn Qn + 1 T
0 0 0
0 1 1
1 0 1
1 1 0

State Table :
CP QC QB QA QC+1 QB+1 QA+1 TC TB TA
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 0 1 1
2 0 1 0 0 1 1 0 0 1
3 0 1 1 1 0 0 1 1 1
4 1 0 0 1 0 1 0 0 1
5 1 0 1 0 0 0 1 0 1

K-map Simplification :

Logic Diagram :

6. (b) Draw 4-bit universal shift register and explain its operation. [10]

Soln.:
1. A shift register which can shift the data in only one direction is called as a unidirectional shift
register.
2. A shift register which can shift the data in both the directions is called as a bi-directional shift
register.
3. Applying the same logic, a shift register which can shift the data in both the directions (shift
right or left) as well as load it parallely, then it is called as a universal shift register.
Figure shows the logic diagram of a universal shift register.
• This shift register is capable of performing the following operations :
1. Parallel loading (parallel input parallel output)
2. Left shifting

22
 Examination Paper Solution (23)

3. Right shifting
• The Mode control input is connected to Logic 1 for parallel loading operation whereas it
is connected to 0 for serial shifting.
• With mode control pin connected to ground, the universal shift register acts as a bi-
directional register.
• For serial left operation, the input is applied to the serial input which goes to AND gate-1
in Figure 1.
• Whereas for the shift right operation, the serial input is applied to D input (input of AND
gate 8).
• The well known example of universal shift register in the IC form is IC7495.

Parallel inputs

A B C D
Mode
control
Serial
input 1 2 3 4 5 6 7 8

Clock 1 M
light shift
M
R R R R
Clock 2 left CK CK CK CK
shift (load) S QA S QB S QC S QD

(LSB) QA QB QC QD (MSB)

Outputs

Fig. 1: Logic diagram of a universal shift register

4. Universal Shift Register IC 7495 :

General description :
• IC 7495 is a TTL MSI shift register.
• It is a 4-bit shift register with serial and parallel synchronous operating modes.
• Because of its capability to operate in all the possible modes, it is called as a universal
shift register.

5. Features :
The important features of this chip are as follows :
• Synchronous shift left capacity.
• Synchronous parallel loading is possible.
• It has separate clock inputs one for shift operation and the other for load operation.
• Expansion with shift right is possible. That means cascading of two or more 7495 ICs for
more than 4−bits is possible.

6. Operations performed by IC 7495 :

IC 7495 is capable of performing the following operations,
• Parallel loading (parallel input parallel output)
• Left shifting
• Right shifting

23
(24) S.E. − DLDA (CMPN)

Parallel Loading (PIPO) :

• The connection diagram for operating IC 7495 in the parallel input parallel output mode is
shown in Figure 2.

1 0 1 1 Binary number to be loaded

2 3 4 5
A B C D +VCC
1
CLK 6
pulses 0 CLK 2 7495
8 Mode
QA QB QC QD
13 12 11 10

Outputs
Fig. 2: 7495 used for parallel loading
• The mode control (M) is connected to logic 1. This will enable the AND gates 2, 4, 6, 8. The
AND gates 1, 3, 5, 7 are disabled. This allows the data transfer from the inputs A, B, C, D to
the flip-flops and disables the serial transfer of data.
• The 4 bit binary number which is to be loaded parallely is applied to the A B C D inputs.
• The clock applied at clock − 2 input only will be passed through to the flip-flops because with
M = 1 the AND gate − 10 is enabled and gate − 9 is disabled.
• As soon as a falling edge of clock is applied, all the flip-flops will change their status
simultaneously and the binary number applied to ABCD inputs will be loaded into the shift
register.
• The unused inputs such as input and clock − 1 can be left open or connected to ground
because they are the don’t care inputs for this mode.

Serial Shift Right Operation :

• The connection diagram for serial shift right mode is shown in Figure 3.
• Make mode control = 0, therefore AND gates 1, 3, 5, 7 will be enabled and AND gate 2, 4, 6,
8 will get disabled. Hence the ABCD inputs become don’t care.
• The data input to FF-A is now the serial input.
• Clock −2 input is don’t care. This is because AND gate 9 is enabled and gate 10 is disabled.

Serial 1 Mode control = 0

input
CLK 2 7495
1 6
0 9 QA QB QD
QC
13 12 11 10

Direction of data shifting

Fig. 3: 7495 connected for serial right shifting

• Apply CLOCK input to clock 1.

• A HIGH to low transition on enabled clock 1 input transfers data serially from serial input to
QA, QA to QB, QB to QC to QD respectively (right shift).

Serial Shift Left Operation :

24
 Examination Paper Solution (25)

• The connection diagram of 7495 for the shift left operation is shown in figure 4. Note that QD
is connected to C, QC to B and QB to A and the serial data is+V
applied at input D.
CC

1 A QB
1 CLK 2 M
Clock 0 Mode control = 1
7495
D Serial input
B QB C QD

Fig. 4: 7495 connected for serial shift left operation

• Mode control is connected to 1. Hence the AND gates 2, 4, 6, 8 are enabled whereas 1, 3, 5
and 7 are disabled.
• This will make the serial input (pin no. 1) a don’t care input.
• the serial data is applied to D which will be routed through the enabled AND gates 2, 4, 6, 8
to facilitate the right shifting operation.
• As M = 1, AND gate 10 is enabled and gate −9 is disabled. So clock −1 becomes a don’t care
input. Apply clock pulses to CLK − 2 (shift left).
• Each high to low transition of clock will transfer data from D to QD, QD to QC, QC to QB and
QB to QA. Thus the shift left operation is performed.

7. Write short notes on :

7. (a) Multiplexer and demultiplexer.

Soln.:
Multiplexer (Data Selector) :
• Multiplexer is a special type of combinational circuit. The block diagram of an n-to-1
multiplexer is shown in Figure 1(a) and its equivalent circuit is shown in Figure 1(b).
• As shown, there are n-data inputs, one output and a m select inputs, with 2m = n.
• A multiplexer is a digital circuit which selects one of the n data inputs and routes it to the
output. The selection of one of the n inputs is done by the select inputs.
• To select n inputs we need m select lines such that 2m = n. Depending on the digital code applied at
the select inputs, one out of n data sources is selected and transmitted to the single output Y.
• E is called as a strobe or enable input which is useful for cascading. It is generally an active
low terminal, that means it will perform the required operation when it is low.
• As shown in Figure 1(b) the multiplexer acts like a digitally controlled single pole, multiple way
switch. The output gets connected to only one of the n data inputs at given instant of time.
MUX

D0 D0
D1
D1
D2 n:1
Multiplexer Y (Output) D2 (Output)

Dn−1
E Dn−1
(Enable
input)
Sm−1 S1 S0 Sm−1 S0
Select inputs
(a) Block diagram of an n : 1 multiplexer (b) Equivalent circuit
Fig. 1

25
(26) S.E. − DLDA (CMPN)

Necessity of Multiplexers :
• In most of the electronic systems, the digital data is available on more than one lines. It is
necessary to route this data over a single line.
• Under such circumstances we require a circuit which select one of the many inputs at a time.
• This circuit is nothing else but a multiplexer. Which has many inputs, one output and some
select inputs.
• Multiplexer improves the reliability of the digital system because it reduces the number of
external wired connections.

Advantages of Multiplexers :
1. It reduces the number of wires.
2. So it reduces the circuit complexity and cost.
3. We can implement many combinational circuits using MUX.
4. It simplifies the logic design.
5. It does not need the k maps and simplification.

Types of Multiplexers :
The types of multiplexer
1) 2 : 1 multiplexer 2) 4 : 1 multiplexer 3) 8 : 1 multiplexer
4) 16 : 1 multiplexer 5) 32 : 1 multiplexer

Applications of a Multiplexer :
Some of the important applications of a multiplexer are as follows :
1. It is used as a data selector to select one out of many data inputs.
2. It is used for simplification of logic design.
3. In the data acquisition system.
4. In designing the combinational circuits.
5. In the D/A converters.
6. To minimize the number of connections.

Multiplexer Tree :
• The multiplexer having more number of inputs can be obtained by cascading two or more
multiplexers with less number of inputs.
• This is called as a multiplexer tree.
• This concept will be clear after solving the following examples.

Demultiplexer Principle :
• The block diagram of a demultiplexer or decoder is shown in Figure 2(a).
• It has only one input, “n” outputs, and “m” select inputs.
• A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and
distributes it over several outputs.
• At a time only one output line is selected by the select lines and the input is transmitted to the
selected output line.
• Hence a demultiplexer is equivalent to a single pole multiple way switch as shown in Figure 2(b).

Y0 Y0
Data Y1 Y1
Dn
input Y2 Data Y2
Demultiplexer Outputs input Outputs

Enable E
Yn−1 Yn−1

Sm−1 Sm−2 S0 Select inputs

Select inputs 26
(a) 1 : n demultiplexer (b) Equivalent circuit
Fig. 2
 Examination Paper Solution (27)

• The enable input will enable the demultiplexer.

• The relation between the n output lines and m select lines is as follows :
n = 2m

Types of Demultiplexers :
Similar to the multiplexers, the demultiplexers are classified as follows :
1. 1:2 demultiplexer 2. 1:4 demutliplexer
3. 1:8 demultiplexer 4. 1:16 demultiplexer

Demultiplexer Tree :
• Similar to multiplexer we can construct the demultiplexer with more number of lines using
demultiplexers having lower number lines.
• This is called as demultiplexer tree. It is also called as cascading of demultiplexers.
• This concept will be clear by solving the following examples.

Comparison of Multiplexer and Demultiplexer :

Table : Comparison of MUX and DEMUX

Sr. Parameter Multiplexer Demultiplexer
No.
1. Type of logic circuit Combinational Combinational
2. Number of data inputs n l
3. Number of select inputs m m
4. Number of data output l n
5. Relation between input / n = 2m n = 2m
output lines and select lines
6. Operation principle Many to 1 or as data selector 1 to many or data distributor
7. Application • As a universal logic • We can implement some
circuit. We can implement combinational circuit.
any combinational
circuit using a MUX.
• In time division
multiplexing at the • In TDM system at
sending end. receiving end.

7. (b) ALU
Arithmetic Logic Unit (ALU) :
• ALU is a very widely used and popular combinational circuit.
• It is capable of performing the arithmetic as well as the logic operations.
• ALU is the heart of any microprocessor.
• Figure 1 shows the block diagram of ALU IC 74181, Table 1 gives the pin description and
Figure 2 gives its pin configuration.
• 74181 is a 24-pin IC dual in line (DTP) package.
• A (A0 − A3) and B (B0 − B3) are the two 4 bit variables.

Table 1: Pin description of 74181

Pin Name Description
A0 − A3 Operated inputs

27
(28) S.E. − DLDA (CMPN)

B0 − B3 Operand inputs
S0 − S3 Function select inputs
M Mode control input
Cn Carry input (active low)
F0 − F3 Function output
Pin Name Description
A=B Comparator output (equality output)
G Carry generate output
P Carry propagate otput
Cn + 4 Carry output (active low)

Fig. 1 : Block diagram of ALU IC 74181 Fig. 2 : Pin configuration of the ALU IC 74181

• It can perform a total of 16 arithmetic operations which includes addition, subtraction,

compare and double operations.
• It provides many logic operations such as AND, OR, NOR, NAND EX-OR, compare etc on
the two four bit variables.
• 74181 is a high speed 4 bit parallel ALU.
• It is controlled by four function select inputs S0 − S3. These lines can select 16 different
operations for one mode (arithmetic) and 16 another operations for the other mode (logic).
• M is the mode control input. It decides the mode of operation to be either arithmetic or logic.
M=0 For arithmetic operations
M =1 For logic operations

• G and P outputs are used when a number of 74181 circuits are to be used in cascade
alongwith 74182, the look ahead carry generator circuit to make the arithmetic operations
faster.
• When mode control input is high (M = 1), then the logic operations are performed on the
individual bits and all the internal carries are enabled.

28
 Examination Paper Solution (29)

• When mode control input is low (M = 0), the arithmetic operations are performed on the two
4-bit words and all the internal carriers are enabled.
• IC 74181 incorporates full internal carry lookahead. This enhances its speed of operation to a
great extent.
• It provides a ripple carry between the devices using the Cn+4 output. (see cascading of two
74181s).
• Or for exploiting the option of carry lookahead between the packages, we have to use the P
(carry propagate) and G (carry generate) outputs. This option should be used only when the
speed requirements are stringent.
• If low speed of operation is acceptable, the ripple carry operation using Cn+4 and Cn should be
exercised.

A = B Output :

1. A = B output indicates the logical equality of the two operands. This output goes HIGH when
the unit is in the subtract mode and A = B.
2. This output also goes high when all the four “Function outputs” are HIGH.
3. It is possible to wire AND the A = B outputs when more than one 74181s are being used. The
wire ANDing becomes possible because A = B is an open collector output. This enables us to
compare words which are longer than 4-bits.

Function tables : (If the question is 10 marks, then mention the functional table in details)

• Table 2(a) shows the function table for IC 74181. It is valid for the active high operands and
active high outputs, and with Cn = 1 i.e. no carry.

Table 2(a): Function table for IC 74181 with active high data and Cn = 1 (no carry)

Function Select Inputs Active high data and Cn = 1

S3 S2 S1 S0 Logic operations (M = 1) Arithmetic operations (M = 0)
0 0 0 0 F = A (Inversion) F=A
0 0 0 1 F = A + B (NOR) F=A+B
0 0 1 0 F = A.B F=A+ B
0 0 1 1 F=0 F = minus 1 (2’s comp)
0 1 0 0 F = AB (NAND) F = A plus A B
0 1 0 1 F = B (Invert) F = (A + B)plus A B
0 1 1 0 F = A ⊕ B (EXOR) F = A minus B minus 1
0 1 1 1 F= AB F = A B minus 1
1 0 0 0 F= A+B F = A plus AB
1 0 0 1 F = A ⊕ B (EXNOR) F = A plus B
1 0 1 0 F=B F = (A + B ) plus AB
1 0 1 1 F = AB (AND) F = AB minus 1
1 1 0 0 F = logic 1 F = A plus A*
1 1 0 1 F=A+ B F = (A + B) plus A
1 1 1 0 F = A + B (OR) F = (A + B ) plus A
1 1 1 1 F=A F = A Minus 1

Each bit is shifted to the next more significant position.

• The arithmetic operations listed in function Table 2(a), correspond to no carry input. They
will get modified if the carry input is present as shown in Table 2(b).

29
(30) S.E. − DLDA (CMPN)

• It is possible to use IC 74181 with either active high inputs or with active low inputs. With
active low inputs the device produces active low outputs and with active high inputs it
produces active high outputs.
• The function table for active low inputs and outputs has been given in Table 2(b).

Table 2(b) : Function table for IC 74181 with active low data and C n = 0 (with carry).
Function Active Low data and Cn = 0
Select Inputs
S3 S2 S1 S0 Logic operations M = 0 Arithmetic operations M = 1
0 0 0 0 F = A (inversion) F = A minus 1
0 0 0 1 F = AB (NAND) F = AB minus 1
0 0 1 0 F= A+B F = A B minus 1
0 0 1 1 F=1 F = minus 1
0 0 1 1 F = A+B F = A plus (A + B )
0 1 0 1 F = B (inversion) F = AB plus (A + B )

7. (c) Asynchronous vs synchronous counter.

Soln.:
Asynchronous / Ripple Counters
Figure 1 shows 2-bit asynchronous counter using JK flip-flops. As shown in figure 1 the clock
signal is connected to the clock input of only first stage flip-flop. The clock input of the second
stage flip-flop is triggered by the QA output of the first stage. Because of the inherent
propagation delay time through a flip-flop, a transition of the input clock pulse and a transition of
the QA output of first stage can never occur at exactly the same time. Therefore, the two flip-
flops are never simultaneously triggered, which results in asynchronous counter operation.

Fig.1 : A two-bit asynchronous binary counter.

Figure 1(a) shows the timing diagram for two-bit asynchronous counter. It illustrates the changes
in the stat eof the flip-flop outputs in response to the clock.

Fig.1(a) : Timing diagram for the counter of Fig.1.

Synchronous Counters
When counter is clocked such that each flip-flop in the counter is triggered at the same time, the
counter is called as synchronous counter. Figure 2 shows two stage synchronous counter.

30
 Examination Paper Solution (31)

Fig.2 : A two-bit synchronous binary counter.

Here, clock signal is connected in parallel to clock inputs of both the flip-flops. But the QA
output of first stag eis used to drive the J and K inputs of the second stage. Let us see the
operation of the circuit. Initially, we assume that the QA = QB = 0. When positive edge of the
first clock pulse is applied, flip flop A will toggle because JA = KA = 1, whereas flip-flop B output
will remain zero because JB = KB = 0. After first clock pulse QA = 1 and QB = 0. at negative
going edge of the second clock pulse both flip-flops will toggle because they both have a toggle
condition on their J and K inputs (JA = KA = JB = KB = 1). Thus after second clock pulse, QA = 0
and QB = 1. At negative going edge of the third clock pulse flip-flop A toggles making QA = 1,
but flip-flop B remains set i.e., QB = 1. Finally, at the leading edge of the fourth clock pulse both
flip-flop toggle as their JK inputs are at logic 1. This result QA = QB = 0 and counter recycled
back to its original state. The timing details of above operation is shown in figure 3.

CP

QA

QB

Fig.3 : Timing diagram and state sequence for the 2-bit synchronous counter.

A 3-bit Synchronous Binary Counter

Figure 4 shows 3-bit synchronous binary counter and its timing diagram. The state sequence for
this counter is shown in Table 1.

Fig.4(a) : A three-bit synchronous binary counter.

Fig.4(b) : Timing diagram for 3-bit synchronous binary counter.

Table : State sequence for 3-bit binary counter.

CP QC QB QA

31
(32) S.E. − DLDA (CMPN)

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Looking at figure 4(b), we can see that QA changes on each clock pulse as we progress from its
original state to its final state and then back to its original state. To produce this operation, flip-
flop A is held in the toggle mode by connecting J and K inputs to HIGH. Now let us see what
flip-flop B does. Flip-flop B toggles, when QA is 1. When QA is a 0, flip-flop B is in the no-
change mode and remains in its present state. We can notice that flip-flop C has to change its
state only when QB and QA both are at logic 1. This condition is detected by AND gate and
applied to the J and K inputs of flip-flop C. Whenever both QA and QB are HIGH, the output of
the AND gate makes the J and K inputs of flip-flop C HIGH, and flip-flop C toggles on the
following clock pulse. At all other times, the J and K inputs of flip-flop C are held LOW by the
AND gate output, and flip-flop does not change state.

III. Table : Comparison of Synchronous and Asynchronous Counters :

Sr.
Parameter Asynchronous counter Synchronous counter
No.
1. Circuit complexity Logic circuit is simple. With increase in number of
states, the logic circuit
becomes complicated.
2. Connection patternOutput of the preceding FF, is There is no connection
connected to clock of the next between output of preceding
FF. FF and CLK of next one.
3. Clock input All the FFs are not clocked All FFs receive clock signal
simultaneously. simultaneously.
4. Propagation delay P.D. = n × (td) where n is P.D. = (td)FF + (td)gate.
number of FFs and td is p.d. It is much shorter than that or
per FF. asynchronous counter.
5. Maximum frequency Low because of the long High due to shorter
of operation propagation delay. propagation delay.

7. (d) Octal to binary encoder.

Soln.:
Octal to Binary Encoder :
• The octal to binary encoder has 8 − input lines and 3 − output lines. Corresponding to the
eight input octal numbers we get three bit binary output.
• Note that in encoders only one input will have a one value at any given time.
• Figure 1 shows the block diagram of octal to binary encoder and Table gives its truth table.

Table : Truth table of octal to binary encoder

Inputs Outputs
D0 D0 D1 D2 D3 D4 D5 D6 D7 B0 B1 B2
D1 1 0 0 0 0 0 0 0 0 0 0
D2 B0 0 1 0 0 0 0 0 0 0 0 1
D3 0 0 1 0 0 0 0 0 0 1 0
Inputs B1 Outputs 0 0 0 1 0 0 0 0 0 1 1
D4
D5 B2 0 0 0 0 1 0 0 0 1 0 0
D6
D7 32

Fig. 1: Block diagram of octal

to binary encoder
 Examination Paper Solution (33)

0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Logical expressions for the outputs :

Referring to the truth table we can write the logical expressions for the outputs as follows :
B0 = D4 + D5 + D6 + D7
B1 = D2 + D3 + D6 + D7
B2 = D1 + D3 + D5 + D7

Implementation using basic gates :

The octal to binary encoder using the basic gates is shown in Figure 2.
D0 D1 D2 D3 D4 D5 D6 D7

B0 = D4 + D5 + D6 + D7

B1 = D2 + D3 + D6 + D7

B2 = D1 + D3 + D5 + D7

Fig. 2: Octal to binary encoder

Encoder IC 74148 (Octal to Binary Encoder) :

• Pi configuration of IC 74148 is as shown in Figure 3. This is an 8 input priority encoder.
• All the inputs are active low inputs with a well defined priority associated with them.
• Input I7 has the highest priority and I0 has the lowest priority.
• This encoder has three output lines which provide the binary representation of the selected
input.

I4 1 16 VCC
Pins Description
I5 2 15 EO
I0 to I7 Active low inputs
I6 3 14 GS
A 0 to A 2 Ative low outputs
I7 4 13 I3
IC 74148 EI Enable Input
EI 5 12 I2
EO Enable Output
A2 6 11 I1
GS Group Singal
A1 7 10 I0

GND 8 9 A0

Fig.: Pin configuration of IC 74148

33
(34) S.E. − DLDA (CMPN)

Description :
• I0 to I7 are the eight active low inputs.
• A 0 to A 2 are the three active low outputs.
• EI is the active low enable input terminal. If EI is at logic 1 then it will force all the output to
become high i.e. inactive. This feature can be used to allow some time for the new input data
to settle down.
• GS is the group signal output. It is used for indication that one of the inputs is low i.e. active.
• If all the inputs are inactive (high) the enable output (EQ) goes to logic 0.

Truth table :
The truth table of IC 74148 is shown in Table.

Table : Truth table IC 74148 i.e. octal to binary encoder

Inputs Outputs
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X X X 0 0 0 0 0 1



34