Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University
ECEN689: Special Topics in High-Speed
Links Circuits and Systems
Spring 2011
Lecture 19: Forwarded Clock DeskewCircuits
Announcements
No class on Friday
Project preliminary report #2 due on Monday in
class
Expand on report #1
Project feedback meetings during Thursday office
hours (9-10:30AM)
Exam 2 is on Friday April 29
Comprehensive, but will focus on lectures 11 and later
60 minutes
1 standard 8.5x11 note sheet (front & back)
Bring your calculator
2
Agenda
Forwarded Clock I/O Overview
Data & Clock Skew Performance Impact
J itter Impulse Response and J itter Transfer
Function
Forwarded Clock DeskewArchitectures
PLL/PI
DLL/PI
ILO
Fundamental, Super-Harmonic, Sub-Harmonic
3
Forwarded Clock I/O Architecture
4
Common high-speed reference
clock is forwarded from TX chip
to RX chip
Mesochronous system
Used in processor-memory
interfaces and multi-processor
communication
Intel QPI
Hypertransport
Requires one extra clock
channel
Coherent clocking allows low-
to-high frequency jitter tracking
Need good clock receive
amplifier as the forwarded clock
is attenuated by the channel
Forwarded Clock I/O Limitations
5
Clock skew can limited forward
clock I/O performance
Driver strength and loading
mismatches
Interconnect length
mismatches
Low pass channel causes jitter
amplification
Duty-Cycle variations of
forwarded clock
Forwarded Clock I/O De-Skew
6
Per-channel de-skew allows for
significant data rate increases
Sample clock adjusted to center
clock on the incoming data eye
Implementations
Delay-Locked Loop and Phase
Interpolators
Injection-Locked Oscillators
Phase Acquisition can be
BER based no additional
input phase samplers
Phase detector based
implemented with additional
input phase samplers
periodically powered on
Forwarded Clock I/O Circuits
7
TX PLL
TX Clock Distribution
Replica TX Clock Driver
Channel
Forward Clock Amplifier
RX Clock Distribution
De-Skew Circuit
PLL/PI
DLL/PI
Injection-Locked Oscillator
Data & Clock Skew Performance Impact
8
High speed forwarded clock
allows jitter tracking
between clock and data
Clock to data skew causes
that high frequency clock
and data jitters become out
of phase on the receiver
Impact of Clock to Data Skew on J itter
Tracking
9
UI = 100ps
Assuming 5UI skew in this example
J itter Frequency = 100MHz
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
data jitter
J
D
(
U
I
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
clock jitter
J
C
(
U
I
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
differential jitter
J
d
i
f
f
(
U
I
)
time
skew of mUI between
data and clock
Impact of Clock to Data Skew on J itter
Tracking
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
data jitter
J
D
(
U
I
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
clock jitter
J
C
(
U
I
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
differential jitter
J
d
i
f
f
(
U
I
)
time
J itter Frequency = 200MHz
Impact of Clock to Data Skew on J itter
Tracking
11
J itter Frequency = 400MHz
The clock skew flips the jitter phase of clock faster for higher frequency
jitter and results in higher differential jitter
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
data jitter
J
D
(
U
I
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
clock jitter
J
C
(
U
I
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-8
-0.5
0
0.5
differential jitter
J
d
i
f
f
(
U
I
)
time
Impact of Clock to Data Skew on J itter Tracking

12
[1] Ganesh Balamurugan et al., Modeling and mitigation of jitter in high-speed source-synchronous interchip communication systems, Conference
Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, vol. 2, no. 2, pp. 1681-1687, Nov. 2003.
0 1 2 3 4 5 6 7 8 9 10
x 10
8
0
0.5
1
1.5
2
2.5
3
3.5
4
J itter Frequency(Hz)
N
o
r
m
a
l
i
z
e
d

D
i
f
f
e
r
e
n
t
i
a
l

J
i
t
t
e
r
1UI
2UI
3UI
4UI 5UI
Larger clock to data skew
increases differential jitter
at lower jitter frequencies
Optimum J itter Tracking for 200MHz jitter

13
Controllable J TB over
70 - 800MHz is
desired
In 10Gb/s system,
UI = 100ps
J itter Frequency = 200MHz
J itter Impulse Response(J IR) and J itter Transfer
Function(J TF) Analysis Method
14
J IR: test the system response on jitter
J TF: ratio of output to input jitter as a function of frequency,
DTFT of J IR
B. Casper and F. OMahony, Clocking analysis, implementation and measurement techniques for high-speed data links a tutorial, IEEE Trans.
Circuits Syst. I, vol. 56, no. 1, pp. 683688, J an. 2009.
Ideal clock waveform superimposed with
clock incorporating jitter impulse stimulus
Output clock waveforms using ideal
clock versus jitter impulse clock
J itter impulse response
Extraction of J IR in rate system where both clock edges are using
A clock systems effect on an input jitter sequence can be evaluated
by convolving the jitter sequence with the jitter impulse response
Filter/Amplifier Frequency Response
& J itter Transfer Response
15
Low-pass frequency response
(buffer, distribution
interconnect) is similar to a
high-pass jitter filter
High frequency jitter is
amplified
High-pass frequency response
(AC coupling cap) is similar to an
all-pass jitter filter, except for
Nyquist-rate jitter (duty cycle
error)
Band-pass frequency response
(band-pass filter) is similar to a
low-pass jitter filter with the
center frequency aligned with
the fundamental clock frequency
B. Casper and F. OMahony, Clocking analysis, implementation and measurement techniques for high-speed data links a tutorial, IEEE Trans.
Circuits Syst. I, vol. 56, no. 1, pp. 683688, J an. 2009.
J itter Amplification
Low-pass frequency response (buffer, distribution
interconnect) is similar to a high-pass jitter filter
High frequency jitter is amplified as it propagates
across the channel
16
0 2 4 6 8 10 12 14
-60
-50
-40
-30
-20
-10
0
Frequency (GHz)
S
2
1

(
d
B
)

0 1 2 3 4 5
x 10
9
0.5
1
1.5
2
2.5
3
Frequency(Hz)
J
i
t
t
e
r

A
m
p
l
i
f
i
c
a
t
i
o
n

F
a
c
t
o
r
Channel Response
J itter Transfer/ Amplification
PLL or DLL/PI Forwarded Clock Deskew
TX clock is forwarded along an independent
channel to the RX chip where it is distributed
to the RX channels
17
The PLL or DLL locks onto
the forwarded clock and
serves as a multi-phase
generator and a jitter filter
The PI mixes the phases to
produce sampling clocks at
the optimal phase for
maximum timing margin or
BER
B. Casper and F. OMahony, Clocking analysis, implementation and measurement techniques for high-speed data links a tutorial, IEEE Trans.
Circuits Syst. I, vol. 56, no. 1, pp. 683688, J an. 2009.
PLL/PI Forwarded Clock DeskewExample
18
DIMM n
Forward
clock
receiver
Lane1
Lane0
Receiver
r
e
s
y
n
c
Transmitter
Forward Clock
Tree
fclk0 fclkn fclk6
Central
PLL
Transmit Clock
Tree
txclk0 txclkn txclk6
Forward
clock
transmitter
DIMM n-1 DIMM n+1
D0
D1
Dn
D13
FW_clk
D0
D1
Dn
D13
FW_clk
Clean up PLL
Phase
Recovery
fclk
txclk
X 7
Fully buffered DIMM transceiver
[Prete I SSCC 2006]
PLL/PI Forwarded Clock DeskewExample
19
PLL low-pass jitter transfer characteristic filters high
frequency jitter
Desired for uncorrelated jitter
Not desired for correlated high frequency jitter
[Prete I SSCC 2006]
VCO
Loop
Filter
0/180 90/270
Data
Samplers
45/225 135/315
Phase recovery
controller
+
ph_cnt<63:0>
data even/odd
edges even/odd
fw_clock
Phase detector
mixing
Phase recovery loop (BW ~ 500KHz)
Phase Locked loop (BW > 150MHz)
+
data_in
PLL disadvantages
J itter accumulation in
VCO
Stability
More area and
complex than DLL
implementations
DLL/PI Forwarded Clock DeskewExample
20
DLL advantages
No jitter accumulation
Inherently stable
Simpler and less area
than PLL
Finite bandwidth of DLL
delay line can result in
jitter amplification
DLL displays an all-pass jitter transfer function
Desired for correlated jitter
Not desired for uncorrelated jitter
[BalamuruganJ SSC 2008]
Injection Locking in LC Tanks
21
a) a free-running oscillator
consisting of an ideal
positive feedback amplifier
and an LC tank;
b) we insert a phase shift in
the loop. We know this will
cause the oscillation
frequency to shift since the
loop gain has to
have exactly 2 phase shift
(or multiples).
22
Phase Shift for Injected Signal
Assume the oscillator locks onto the injected
current and oscillates at the same frequency.
Since the locking signal is not in general at
the resonant center frequency, the tank
introduces a phase shift
In order for the oscillator loop gain to be equal
to unity with zero phase shift, the sum of the
current of the transistor and the injected
currents must have the proper phase shift to
compensate for the tank phase shift.
Injection Locked Oscillator Phasors
23
Note that the frequency of the injection signal determines the extra phase shift

0
of the tank. This is fixed by the frequency offset.
The current from the transistor is fed by the tank voltage, which by definition
the tank current times the tank impedance, which introduces
0
between the
tank current/voltage.
The angle between the injected current and the oscillator current must be
such that their sum aligns with the tank current.
Injection Geometry
24
The geometry of the problem implies the following constraints on the injected
current amplitude relative to the oscillation amplitude.
Locking Range
25
At the edge of the lock range, the injected current is orthogonal to the tank current.
The phase angle between the injected current and the oscillator is 90 +
0,max
iosc
inj
iosc
inj
inj osc inj osc
inj
T
inj
I
I
if
I
I
I I I I
I
I
I
= =
+ +
= =

cos . , sin
cos 2
sin
sin sin
max , 0
2 2
0
2 2
0
0
0
0
1 1 1
0 0
2 2
0
2 2
0
2
0 1
0
, tan
) (
2
tan
) ( tan ) ( tan
2
,
1
), ( 2
) ( tan
2
inj osc T
T
inj
p
p
I I I
I
I
Q
x x
Q R
L
R
L
= =

= =

A second-order parallel tank consisting of L. C, Rp

exhibits a phase shift of:
Source: Razavi
Locking Range
26
2
2
0
0
0
0
2
2
2
2
0
0
1
1
2
) (
2
1
1
1
1
) (
2
osc
inj
osc
inj
inj
osc
inj
osc
inj
osc
inj
osc
inj
T
osc
osc
inj
T
inj
I
I
I
I
Q
Q
I
I
I
I
I
I
I
I
I
I
I
I
Q
I
I

osc
inj
inj L
I
I
Q
=

2
0
0 ,


osc inj
I I <<
1 . 0 , 5 , 10 :
0
= = = =
osc
inj
I
I
K Q GHz When
MHz
L
100
,
=>

Locking range is inversely proportional to oscillator Q

Digital Controlled Oscillator (DCO) with Injection Locking
27
The digitally controlled switch-capacitor bank tunes the free-running
frequency of DCO to adjust the phase of the forwarded clock and also
compensate for PVT.
Shekhar, Sudip et al, Strong Injection Locking in Low-Q LC Oscillators: Modeling and Application in a Forwarded-Clocked I/O
Receiver, IEEE J SSC, 2009.
Ring Oscillator ILO Example
28
[Hu J SSC 2010]
Ring Oscillator ILO Example
29
[Hu J SSC 2010]
ILO J itter Transfer
ILOs have a first-order low-pass
filter function to input (injection
clock) jitter
ILOs have a first-order high-pass
filter function to VCO jitter
30
P
P
VCO
s
s
JTF

+
=
1

=
=

K
A
Q
A
A
K
o
1
ss
2
2
2
P P
sin : phase skew - de desired the of function a is
2
: ank resonant t RLC parallel a For
: bandwidth cking jitter tra the is where
P
INPUT
s
JTF

+
=
1
1
ILO J itter Transfer
ILO jitter transfer bandwidth decreases as the
oscillator is locked further from the free-running
frequency,
o
, to obtain a larger phase shift
ss
31
P
INPUT
s
JTF

+
=
1
1

K
A
A
K
1
ss
2
2
2
P
sin

[HossainJ SSC 2009]
ILO J itter Transfer
ILO jitter transfer bandwidth increases with
injection strength
32
P
INPUT
s
JTF

+
=
1
1

K
A
A
K
1
ss
2
2
2
P
sin

[HossainJ SSC 2009]
ILO J itter Transfer
ILO jitter transfer bandwidth increases with
injection strength
33
P
INPUT
s
JTF

+
=
1
1

K
A
A
K
1
ss
2
2
2
P
sin

[HossainJ SSC 2009]
ILO Phase Noise Filtering
Up to jitter tracking
bandwidth, ILO output
phase noise is dominated
by injection clock
Can be better than VCO
J TB depends on desired
de-skew phase
At high frequencies, VCO
phase noise dominates
34
( )
2 2
2
2 2
2
2 2
2 2
2
2
cos
cos

=
+
+
=
+ =
ss
VCO inj ss
P
VCO inj P
jitter out
VCO VCO inj input out
A
K
S S
A
K
S S
S
S JTF S JTF S
[HossainJ SSC 2009]
Ring Oscillator Super-Harmonic ILO Example
35
0.5 m Here = =
inj osc
mf f
Potential system application
rate TX forwards clock to
rate RX
[HossainJ SSC 2009]
Super-Harmonic ILO Phase Noise Filtering
36
0.5 m Here = =
inj osc
mf f
( )
2 2
2
2 2
2
2
cos
cos

=
ss
VCO inj ss
jitter out
m
A
K
S S m
A
K
m
S
[HossainJ SSC 2009]
Low frequency phase
noise is actually better
than injection oscillator
by m
2
Ring Oscillator Sub-Harmonic ILO
Example w/ Clock Signal Injection
Forwarding a lower speed clock avoids jitter
amplification over low-pass channel
37
Sub-Harmonic
injection with clock
signal can cause
significant ILO
amplitude variations
and sub-harmonic
spurious tones
[HossainI SSCC 2010]
Ring Oscillator Sub-Harmonic ILO
Example w/ Pulse Train Signal Injection
Forwarding a pulse train signal reduces
amplitude variations and ILO spurious tones
38
Adjusting pulse
width, d, changes
effective injection
strength and can
be used to adjust
jitter tracking
bandwidth
[HossainI SSCC 2010]
Effective Injection Strength of Pulse Train
Wider pulse separation (lower frequency sub-
harmonics) reduces effective injection strength
39
[HossainI SSCC 2010]
Adjusting J itter Tracking Bandwidth
w/ Pulse Train Signal
40
Wider pulse separation (lower frequency sub-harmonics)
reduces effective injection strength and results in lower
jitter tracking bandwidth
Reducing pulse width, d, for a given spacing reduces
effective injection strength and results in lower jitter
tracking bandwidth
[HossainI SSCC 2010]
Optimum J itter Tracking for 200MHz jitter

41
Controllable J TB over
70 - 800MHz is
desired
In 10Gb/s system,
UI = 100ps
J itter Frequency = 200MHz
Objective: Implement
optimal J TB that yields
minimum differential jitter
Understanding of J itter Reduction using
Bandpass Filtering

42
fc fL fH f fc fL fH f

43
Understanding of J itter Reduction using
Bandpass Filtering

44
Understanding of J itter Reduction using
Bandpass Filtering
Analysis of Bandpass J itter Filtering Based on J IR
and J TF
45
Transmitted jitter exhibits low-pass transfer
characteristic through band-pass channel
Received high frequency uncorrelated jitter can be
reduced by a bandpass filter
15 20 25 30 35 40
-2
0
2
4
6
8
x 10
-12
J itter Impluse Reponse of Bandpass System
Clocking Cycle#
N
o
r
m
a
l
i
z
e
d

J
i
t
t
e
r
0 0.5 1 1.5 2 2.5
x 10
9
-25
-20
-15
-10
-5
0
J itter Transfer of Bandpass System
Freq(Hz)
J
i
t
t
e
r

A
m
p
l
i
f
i
c
a
t
i
o
n

F
a
c
t
o
r
Optimum J itter Tracking with Bandpass
Filtering
Higher Q of bandpass filtering, smaller bandwidth, higher jitter
filtering
46
fc fL fH
Q1
Q2
Q3
Q1 < Q2 < Q3
f
Optimum J itter Tracking with Bandpass
Filtering
Apply J IR and J TF analysis to quantify the impact of Q on J TB of
5GHz clock, UI = 100ps
47
Q tuning range over
3 -30 provides J TB
range over 97 790
MHz
To achieve J TB of
70MHz to optimize
jitter tracking with
10UI clock skew,
higher Q is required.
Bandpass Filter for Forwarded-Clocks
48
[Hollis AI CSP 2008]
Bandpass Filter J itter Filtering
Bandpass filter is effective in filtering high-frequency jitter
Low-maximum Q of the filter (Q=2.6) limits tuning to
low-frequency jitter tracking bandwidths
Limited by the passive inductor Q
49
Next Time
Clock Distribution Techniques
50