GATE DRIVERS

Using Monolithic High

Voltage Gate Drivers

THE POWER MANAGEMENT LEADER

By A. Merello, A. Rugginenti and M. Grasso, International Rectifier

INTRODUCTION
The purpose of this paper is to highlight the most common
subjects driving a half bridge power stage in motor drive applications (with monolithic IC gate driver) and to suggest appropriate solutions to solve the issues.
In the following sections different topics are discussed: the
sizing of some fundamental components, as bootstrap circuit
and on/off gate resistors; the half bridge parasitic elements
are presented with their effects and some possible solutions
are proposed. In the end section some layout tips are presented.
All the situations and the solutions proposed are, unless
otherwise specified, for a typical IR monolithic gate driver
with floating bootstrap supply.

BOOTSTRAP CIRCUIT

time since they are limited by the requirement to refresh the

charge in the bootstrap capacitor.
Proper capacitor choice can reduce drastically these limitations.
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to establish
the minimum voltage drop (VBS) that we have to guarantee
when the high side IGBT is on. If VGEmin is the minimum gate
emitter voltage to maintain, the voltage drop must be:
VBS VCC VF VGEmin VCEon
under the condition:
VGEmin > VBSUV

DT04-4 revA

where V is the IC voltage supply, VF is bootstrap diode

The bootstrap supply is formed by a diode and a capacitor
Using monolithic high voltage gate drivers CC
forward voltage, VCEon is emittercollector voltage of low side
connected as in figure 1.
IGBT
and VBSUV- is the high-side supply undervoltage negative
BOOTSTRAP CIRCUIT
going threshold.
This method has the advantage of being simple and low
The bootstrap supply is formed by a diode and a capacitor connected as in figure 1.
Now we must consider the influencing factors contributing
cost but may force some limitations on duty-cycle and onVBS to decrease:
bootstrap
resistor

bootstrap
diode
DC+

Rboot

VCC

VF

VB

VBS

bootstrap
capacitor

VGE
ILOAD

VS

VCC

VCEon
VFP

DC-

Figure 1: bootstrap supply schematic

motor

IGBT turn on required Gate charge (QG);

IGBT gate-source leakage current (ILK_GE);
Floating section quiescent current (IQBS);
Floating section leakage current (ILK)
Bootstrap diode leakage current (ILK_DIODE);
Desat diode bias when on (IDS- )
Charge required by the internal level shifters (QLS);
Bootstrap capacitor leakage current (ILK_CAP);
High side on time (THON).
ILK_CAP is only relevant when using an electrolytic capacitor
and can be ignored if other types of capacitors are used. It
is strongly recommend using at least one low ESR ceramic

This method has the advantage of being simple and low cost but may force some limitations on
Foron-time
more information
in North
Americabycall
+1 requirement
310 252 7105, in
+49charge
6102 884in311,
duty-cycle and
since they
are limited
the
toEurope
refreshcall
the
theor visit us at www.irf.com
bootstrap capacitor.
Proper capacitor choice can reduce drastically these limitations.

Bootstrap capacitor sizing

DT04-04

Using monolithic high voltage gate drivers

Using

Bootstrap diode leakage current (ILK_DIODE);

Desat diode bias when on (IDS- )
Charge required
by Voltage
the internal Gate
level shifters
(QLS);
Monolithic
High
Drivers
Bootstrap capacitor leakage current (ILK_CAP);
High side on time (THON).

ILK_CAP is only
relevant when
using anand
electrolytic
capacitor
and may
can be ignored
if otherformulas.
types of
capacitor
(paralleling
electrolytic
low ESR
ceramic
the above
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
result
in an efficient solution).
(paralleling electrolytic and low ESR ceramic may result in an efficient solution).
2. This kind of bootstrap sizing approach does not take into
Then
account neither the duty cycle of the PWM, nor the funda
Thenwe
wehave:
have:
mental frequency
QTOT = QG + QLS + (ILK _ GE + IQBS + ILK + ILK _ DIODE + ILK _ CAP + IDS ) THON
DT04-4
revA of the current. It considers only the
amount of charge that is needed when the high voltage side
QTOT = QG +QLS + (ILK _GE + IQBS + ILK + ILK _DIODE + ILK _CAP + IDS ) THON
The
size
of bootstrap
capacitor
is: Using
gatedriver
drivers
of the
is floating and IGBT gate is driven once.
Theminimum
minimum
size
of bootstrap
capacitor
is: monolithic high voltage
Considerations
on PWM duty cycle, kind of modulation (six Bootstrap
diode leakage current (ILK_DIODE);
QTOT
CBOOT
min =diode bias when on (IDS- )
Desat
step, 12-step, sine-wave) must be considered with their own
VBS
Charge required
by the internal level shifters (QLS);
peculiarity to achieve best bootstrap circuit sizing.
Bootstrap capacitor leakage current (ILK_CAP);
Anexample
follows:
).
High
side
on
time
(T
HON
An example follows:
ILK_CAP
is only
relevant
when
using
an electrolytic capacitor
and
can behalf-bridge
ignoredConsiderations
if gate
otherdriver
types of about bootstrap circuit
a) using
a 25A
@ 125C
IGBT
(IRGP30B120KD)
and a high
voltage
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
(IR2214):
a) using aelectrolytic
25A @ 125C
IGBT
(IRGP30B120KD)
high volt(paralleling
and low
ESR
ceramic may resultand
in anaefficient
solution).
a. Voltage ripple
age
half-bridge
gate
driver
(IR2214):
Then
= 800 A
(Datasheet IR2214);
Iwe
QBShave:
(Datasheet IR2214);
ILK = 50 A
=
20
nC;

Q
LS
IQBS = 800 A (Datasheet IR2214);
(Datasheet IRGP30B120KD);
QG = 160 nC
The minimum
size of bootstrap capacitor
is:
= 50= A
IR2214);
100(Datasheet
nA
(Datasheet IRGP30B120KD);
ILK
ILK_GE
=nC;
100QA
(with reverseIRGP30B120KD);
recovery time <100 ns);
QILK_DIODE
= 20
= 160 nC (Datasheet
QTOT
G
CBOOT LS
min =
=V0BS
(neglected for ceramic capacitor);
ILK_CAP

ILK_GE = 100 nA (Datasheet IRGP30B120KD);

(Datasheet IR2214);
IDS- = 150 A
= 100
An example
100
s.A (with reverse recovery time <100 ns);
ILK_DIODE
THON = follows:
QTOT = QG + QLS + (I LK _ GE + IQBS + ILK + ILK _ DIODE + I LK _ CAP + IDS ) THON

= 0 (neglected for ceramic capacitor);

Three different situations can occur in the bootstrap capacitor charging (see figure 1):
- ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon

LK_CAP
a) using
And: a 25A @ 125C IGBT (IRGP30B120KD) and a high voltage half-bridge gate driver
(IR2214):
I - = 150 A (Datasheet IR2214);
V =V V
DS

100
= A
15s.
V
CC
=V=
800
(Datasheet IR2214);
IT
QBS
HON
1V
50
A
(Datasheet IR2214);
ILK = V
F=
nC;
QLS =V20
CEonmax = 3.1 V
And:
(Datasheet IRGP30B120KD);
QG =V160 nC
GEmin = 10.5 V
(Datasheet IRGP30B120KD);
ILK_GE = 100 nA
(with reverse recovery time <100 ns);
ILK_DIODE = 100 A
the
maximum
voltage
drop
V
BS becomes
(neglected
for ceramic capacitor);
IV
= =150 V
LK_CAP
CC
(Datasheet IR2214);
IDS- = 150 A
VHON
==1CC100
VVFs.VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V
VTBS
F V

V
And: CEonmax

CC

VCEon

In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing.
When the IGBT is turned off the Vs node is pushed up by
the load current until the high side freewheeling diode gets
forwarded biased

= 3.1 V

And
Vthe bootstrap
= 10.5 Vcapacitor is:
GEmin

VCC = 15 V
V nC

V = 1290
C VF = 3.1 V= 725 nF
BOOT
CEonmax0.4 V
the
maximum
voltage drop

VGEmin = 10.5 V

VBS becomes

NOTES:
the
maximum voltage drop VBS becomes

VBS VCC VF VGEmin VCEon=15V 1V 10.5V 3.1V = 0.4V

VBS VCC VF VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V

And
the bootstrap capacitor is:
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And
the bootstrap capacitor is:
CBOOT

BS

290 nC
= 725 nF
0. 4 V

NOTES:

Notes:
www.irf.com

1. Here above VCC has been chosen to be 15V. Some IGBTs

may require higher supply to properly work with the bootstrap technique. Also Vcc variations must be accounted in

- ILOAD = 0; the IGBT is not loaded while being on and VCE can
be neglected
VBS =VCC VF
- ILOAD > 0; the load current flows through the freewheeling
diode
3
VBS =VCC VF +VFP
In this case we have the highest value for VBS. Turning on the
high side IGBT, ILOAD flows into it and VS is pulled up.
3

To minimize the risk of undervoltage, bootstrap capacitor

should be sized according to the ILOAD<0 case.

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DT04-04

d. off
Bootstrap
capacitor sizing. When the IGBT is turned
the Vs Diode
node is pushed up by the load current until
The
diode
must have a BV > DC+ and a fast recovery time (trr < 100 ns) to minimize the amou
the high side freewheeling diode get forwarded biased
of charge fed back from the bootstrap capacitor to VCC supply.

 ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected

Using Monolithic High Voltage Gate Drivers GATE RESISTANCES

VBS = VCC VF

The switching speed of the output transistor can be controlled by properly size the resisto
controlling the turn-on and turn-off gate current. The following section provides some basic rule
0; the load current flows through
the freewheeling
ILOAD >Resistor
b. 
Bootstrap
Qgc and diode
Qtoge obtain
indicatethethedesired
gate toswitching
collector time
and gate
to emitter
for sizing the resistors
and speed
by introducing th
equivalent outputcharge
resistance
of the gate driver (RDRp and RDRn respectively of p and n channel).
respectively.
VBS = VCC VF + VFP
The examples always use IGBT power transistor. Figure 2 shows the nomenclature used in th
A resistor
(Rboot) is placed in series with bootstrap
diode (see
Sizing
the turn-on
resistor
indicates
the plateau voltage, Qgc and Qge indicate the ga
following
paragraphs.
In addition,
Vge* gate
to collector
and gate to emitter charge respectively.
figure 1) so to limit the current when the bootstrap
capacitor

In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it
is initially
charged.
The choice of bootstrap resistor is strictly
and V
S is pulled up.
I
C
related to VBS time-constant. The minimum on time for chargthe risk of
undervoltage,
capacitor should be sized according to the
ingTo
theminimize
bootstrap capacitor
or for
refreshing its bootstrap
charge must
I
LOAD<0 case.
V
be verified against this time-constant.
C

RES

GE

b. Bootstrap Resistor
t ,Q
t ,Q
c.
Capacitor
A Bootstrap
resistor (R
boot) is placed in series with bootstrap diode (see figure 1) so to limit the current when
V
the bootstrap capacitor is initially charged. The choice of bootstrap resistor isdV/dt
strictly related to
time-constant.
The
minimum
on
time
for
charging
the
bootstrap
capacitor
or
for refreshing its
V
ForBShigh THON designs where is used an electrolytic tank caI
charge must be verified against this time-constant.
90%
pacitor, its ESR must be considered. This parasitic resistance
C
V
V *
forms
voltage divider
with Rboot generating a voltage step on
c. aBootstrap
Capacitor
at the
firstTcharge
of bootstrap
Theelectrolytic
voltage steptank capacitor, its ESR must be considered.
VBSFor
wherecapacitor.
is used an
high
HON designs
10%
10%
step on VBS at the
parasitic
resistance
with Rboot generating a voltage
andThis
the related
speed
(dVBS/dt)forms
shouldabevoltage
limited.divider
As a general
first
charge
of
bootstrap
capacitor.
The
voltage
step
and
the
related
speed
(dV
BS/dt) should be
rule, ESR should meet the following constraint:
limited. As a general rule, ESR should meet the following constraint:
1

GE

GC

CE

RES

CRESon

GE

ge

CRESoff

t,Q

tSW

tDon

ESR
VCC 3 V
ESR + RBOOT

tR

Figure 2: Nomenclature

Sizing the turn-on gate resistor

Parallel combination of small ceramic and largeGate

electrolytic
resitances may be chosen in order to fix either the switching-time or the output voltage
slope.
Hereafter
presented
both the
capacitors
is
normally
the
best
compromise,
the
first
acting
as are
Gate
resitances
maymethods.
be chosen in order 4to fix either the
www.irf.com
fast charge tank for the gate charge only and limiting the dVBS/ switching-time or the output voltage slope. Hereafter are preSwitching-time
dt by reducing the equivalent resistance, while the second sented both the methods.
keeps the VBS voltage drop inside the desired VFor
. the matters of the calculation included hereafter, the switching time tsw is defined as the tim
BS
spent to reach theSwitching-time
end of the plateau voltage (a total Qgc + Qge has been provided to the IGB
d. Bootstrap Diode
For the matters of the calculation included hereafter, the
www.irf.com
The diode must have a BV > DC+ and a fast recovery time switching time tsw is defined as the time spent to reach the
(trr < 100 ns) to minimize the amount of charge fed back from end of the plateau voltage (a total Qgc + Qge has been proUsing mono
vided to the IGBT gate). To obtain the desired switching time
the bootstrap capacitor to VCC supply.
the gate
resistance
can the
be sized
starting
from Qge
andthe
Qgc,
gate).
To obtain
desired
switching
time
gate resistanc
*
Vcc, Vge*
GATE RESISTANCES
Vcc,figure
Vge 3):
(see figure 3):
Qgc, (see
The switching speed of the output transistor can be controlled by properly size the resistors controlling the turn-on
and turn-off gate current. The following section provides
some basic rules for sizing the resistors to obtain the desired
switching time and speed by introducing the equivalent output
resistance of the gate driver (RDRp and RDRn respectively of
p and n channel). The examples always use IGBT power transistor. Figure 2 shows the nomenclature used in the following
paragraphs. In addition, Vge* indicates the plateau voltage,

I avg =

Qgc + Qge

and
RTOT =

t sw
*
Vcc Vge

Iavg

where RTOT = R DRp + RGon , RGon = gate on-resistor and RD

(from the gate driver datasheet)

For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com

Vcc/Vb

DT04-04

RDRp

Iavg
CRES

Using monolithic high voltage gate drivers

+ Qge

Using monolithic high voltage gate drivers

gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and
DT04-4
Qgc, Vcc, Vge* (see figure 3):
Using
Monolithic
High
Gate Drivers
gate).
To obtain
the Voltage
desired switching
time the gate resistance can be sized starting from Qge and
*
Using monolithic high voltage gate
V
Qgc, Vcc,
*
ge (see figure 3):
Qgc + Qge
Vcc Vge
I avg =
Iavg
t swQ
gc +
where Q
TOT
DRpgeGon R = R + R , RGon
= gatethe
on-resistor
and gate
external
events.
Sizing
turn-off
resistor
Iand
avg =
RGon= ,driver
RGon
= gate on-resistor
and (from
RDRp the
= driver
equivalent
t swequivalent
RDRp
on-resistance
gate driver
In on-resistance
this case, dV/dt of the output node induces a parasitic
TOT = R DRp +
and
when
the IGBT in off
The worst case in sizing current
the turn-off
resistor
datasheet)
through
CRESoffRflowing
RGoffthe
andcollector
RDRn (seeof
figure
gate driver datasheet)
Goff is in
*
Vcc Vge
forced
to
commutate
by
external
events.
4)1.
RTOT =
Using
monolith
*
Using
monolith
flowing
output
nodedrop
induces
a parasitic
through
CRESoff
Vge
VccIavg
If the voltage
at the gate
exceedscurrent
the threshold
voltage
IavgIn this case, dV/dt of the
1
Vcc/Vb
RTOT =
(see
figure
4)
.
and
R
DRn
Iavg= R
of the
IGBT,= the
device
may self turn
on causing large oscillaRGon = gate on-resistor and
RDRp
driver
equivalent
on-resistance
where RTOT
DRp + RGon ,C
IfRES
the voltage drop at the gate
exceeds
the
threshold
voltage
of the IGBT, the device may
Sizing
the
turn-off
gate
resistor
Sizing
the
turn-off
gate
resistor
and relevant
cross
RTOT
= driver
R DRp +datasheet)
RGon , Ron
= gate on-resistor
andtion
Rand
driver equivalent
on-resistance
where
(from the
gate
Goncausing
DRp =relevant
large oscillation
crossconduction.
conduction.
RDRp
(from the gate driver datasheet)
is when
when the
the co
co
Theworst
worstcase
caseininsizing
sizingthe
theturn-off
turn-off resistor
resistor RRGoff
Goff is
The
forced
to
commutate
by
external
events.
I
avg forced to commutate by external events.
Vcc/Vb
thiscase,
case,dV/dt
dV/dt of
of the
the output
output node
node induces
induces
parasitic curren
curren
dV/dt
InInthis
aa parasitic
I
avg
HS Turning
ON
RGon
Vcc/Vb
CRES
11.
(see
figure
4)
and
R
DRn
and RDRn (see figure 4) .
CRES IfIfthe
thevoltage
voltagedrop
dropat
atthe
theCgate
gateexceeds
exceedsthe
thethreshold
thresholdvoltage
voltage of
of th
th
RESoff
RDRp
oncausing
causinglarge
largeoscillation
oscillationand
andrelevant
relevantcross
crossconduction.
conduction.
COM/Vs
on
RDRp
RGoff
t sw

Figure 3: RGon sizing

RGon

RGon

ON

OFF
RDRn

CIES

HSTurning
TurningON
ON
HS

eports the gate resistance size for two commonly used IGBTs (calculation made using
RESoff
CCRESoff
COM/Vs
atasheet values and assuming Vcc=15V).
Figure 4: RGoff sizing: current path when Low Side is off and
COM/Vs
Table 1 reports the gate resistance size for two commonly
Goff
RRGoff
High Side turns on
oltage slopeused IGBTs (calculation made using typical datasheet
sizing:
current path when Low Side is off and High Side turns
Figure3:
4:RRGon
OFF on
values
Goffsizing
Figure
OFF
ON
sizing
Figure
3:
R
ON
Gon
IES
and assuming Vcc=15V).
CCIES
DRn
RRDRn
can1be
sized to
output
slopesize
(dV
/dt).
gate resistor RGon
Hereafter
isfor
described
howHereafter
toused
sizeisIGBTs
the
turn-off
resistor
when
the
output
dV/dt
is caused
OUT
Table
reports
thecontrol
gate resistance
two commonly
(calculation
made
using
described
how tomade
size the
turn-off resistor when
Table
1
reports
the
gate
resistance
size
for
two
commonly
used
IGBTs
(calculation
using
e output voltage
has
a
non-linear
behaviour,
the
maximum
output
slope
can
be
companion
IGBT
turning-on
(as
shown
in
figure
4).
typical datasheet values and assuming Vcc=15V).
the output dV/dt is caused by the companion IGBT turning-on
Output voltage
slope
typical
datasheet
values and assuming
Vcc=15V).
ated by:
Other dV/dt
cases may be
present and must be taken into account. As an example, th
(as
shown
in figure(high
4). frequency spikes).
generated
by
long
motor
cable
coupling
Output voltage slope
sizing:current
current
path
wheninto
LowSide
Side isis off
off
Figure
4:
Goffsizing:
path
Low
Figure
RRGoff
Output
slope
Iavg
Other dV/dt
cases
may
be present
and must
betowhen
taken
Turn-on voltage
gate resistor
RGon can be
controlthe
output
Forsized
this to
reason
off-resistance
must
be 4:
properly
sized according
the application
wors
account.
As OUT
an
example,
thehow
dV/dttogenerated
by
long motor
slope
(dVOUTgate
/dt). resistor RGon can be sized to control output
CRESoff
slope
(dV
/dt).
Turn-on
Hereafter
is described
described
size the
the turn-off
turn-off
resistor when
when the
th
Hereafter
is
how to
size
resistor
can The
be sized
to control
outputrelates
slope
(dV
/dt).
Turn-on gate resistor RGon
OUT
following
equation
the
IGBT
gate
threshold
voltage
to
the
collector
dV/dt:
coupling
(high
frequency
spikes).
While the
output
voltage
has ahas
non-linear
behaviour,
the cable
While
the
output
voltage
a
non-linear
behaviour,
the
maximum
output
slope
can
be
companion
IGBT
turning-on
(as
shown
in
figure
4).
companion
IGBT
turning-on
(as
shown
in
figure
4).
While the output voltage has a non-linear behaviour, the maximum output slope can be
the expression
yielding
Iavg and
approximated
by:rearranging:
Other
dV/dt
cases
may be
be present
present
and
must
beactaken into
into acc
acc
For thisdV/dt
reasoncases
the off-resistance
must beand
properly
sized
maximum
output
slope
can be approximated by:
Other
may
must
be
taken
approximated
by:
dV
generated
by
long
motor
cable
coupling
(high
frequency
spikes).
outcable
generated
by
long
motor
coupling
(high
frequency
spikes).
cording
to
the
application
worst
case.
Vth (RGoff + RDRn ) I = (RGoff + RDRn ) CRESoff
*
Forthis
thisreason
reasonthe
theoff-resistance
off-resistance
mustbe
beproperly
properlysized
sized accordin
accordin
dt
For
must
dVout
Vcc Vge
avg
IIavg
dV
out =
=
dt
CRESoff
dV
The following
relates
the IGBT
gate threshold
volt- voltage to
dt
C
RESoff
CRESoff out
The
followingequation
equation
relates
theIGBT
IGBT
gatethreshold
threshold
following
equation
relates
the
gate
voltage to
Rearranging the equation The
yields:
dt
age to the collector dV/dt:
andrearranging:
rearranging:
inserting
theexpression
expression
yielding
Iavgand
inserting
the
expression
yielding
inserting the
yielding
IavgIavg
and
rearranging:
dVout
dV
out
Vthout/dt=5V/nsVwhen
two
ample, table 2 shows the sizing of gate resistance
to
get
dV
(using
(RGoff
RGoff
RDRn
CRESoff
RRDRn
Goff ++
DRn)) I I ==(R
Goff ++R
DRn)) C
RESoff
RGoff
RDRnVthth(R
dt
dt
dV
*
GBTs, typical datasheet values and
VccVVgege* assuming Vcc=15V.
CRESoff
Vcc
=
RTOT
=
dt
TOT
dVout
dV
Rearranging
the
equation
yields:
Rearranging
the
equation
yields:
out
Rearranging the
equation
yields:
CRESoff

RESoff
dtdt
As an example, table 3 reports RGoff for two popular IGBT to withstand dVout/dt = 5V/ns.
VVthth
RDRn
dV /dt=5V/ns
RRto
get
R
Goff
DRn
Goff
when
using
two two
As an
the
ofofgate
resistance
get
when
using
an example,
example,table
table22shows
showsNOTES:
thesizing
sizing
gate
resistance
to
dV
out
dV intended
out/dt=5V/ns
dV
The
above-described
equations
are
to
be an
approximated way for t

C
As
an
example,
table
2
shows
the
sizing
of
gate
resistance
C

RESoff
popular
assuming
Vcc=15V.
popular IGBTs,
IGBTs,typical
typicaldatasheet
datasheetvalues
valuesand
and
assuming
Vcc=15V. RESoff
dtdt take into account more precise device m
resistances
sizing.
More
accurate
sizing
may
to get dVout/dt=5V/ns when using two popular IGBTs, typical
om
6 the PCB and power section layout and
and parasitic component dependent on
Asan
an
example,
table
3 reports
RGoff
for
two
IGBT to
datasheet values and assuming Vcc=15V.
forpopular
twopopular
popular
IGBT to
to withs
withs
As
an
example,
table
reports
two
IGBT
As
example,
table
33reports
RRGoff
Gofffor
connections.
withstand
dV
/dt
=
5V/ns.
out
Another way to size the gate resistors is following power dissipation constraints. This wa
NOTES: The
The above-described
above-described equations
equations are
are intended
intended to
to be
be an
an
NOTES:
Sizing the turn-off gate resistor investigated here.
resistances
sizing.
More
accurate
sizing
may
take
into
account
resistances
sizing.
More
accurate
sizing
may
take
into
account
NOTES: The above-described equations are intended to be
and parasitic
parasitic component
component dependent
dependent on
on the
the PCB
PCB and
and pow
pow
and
The worst case in sizing the turn-off resistor RGoff is when an approximated way for the gate resistances
www.irf.com
6 6 sizing. More
connections.
connections.
www.irf.com
the collector of the IGBT in off state is forced to commutate by accurate
takethe
intogate
account
more is
precise
device
Anothersizing
waymay
size
the
gate
resistors
is following
following
power dissipa
dissipa
Another
way
totosize
resistors
power
1
investigatedhere.
here.
investigated

This is true under the assumption that gate voltage remains fixed during dV/dt. The resu
is884
at 311,
least
twousorder
of magnitude
greater than C
reasonable
CIES
RES),
For more information in North America call +1 310 252 7105, inwhenever
Europe cal l +49
6102
or visit
at www.irf.com

DT04-04
www.irf.com

11

This
Thisisistrue
trueunder
under the
theassumption
assumptionthat
thatgate
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voltageremains
remains fixe
fixe

DT04-4 revA
Using Monolithic High Voltage Gate Drivers

Table 1: tsw driven RGon sizing (for RDRp = 7 )

IGBT

Qge

Qgc

Vge*

tsw

Iavg

Rtot

RGon std commercial value

Tsw

IRGP30B120K(D)
IRG4PH30K(D)

19nC
10nC

82nC
20nC

9V
9V

400ns
200ns

0.25A
0.15A

24
40

RTOT - RDRp = 17 18
RTOT - RDRp = 33

420ns
200ns

Table 2: dVOUT/dt driven RGon sizing (for RDRp = 7 )

IGBT

Qge

Qgc

Vge*

CRESoff

Rtot

RGon std commercial value

dVout/dt

IRGP30B120K(D)
IRG4PH30K(D)

19nC
10nc

82nC
20nC

9V
9V

85pF
14pF

14
85

RTOT - RDRp = 7 8.2

RTOT - RDRp = 78 82

4.5V/ns
5V/ns

Table 3: RGoff sizing

IGBT

Vth(min)Using
CRESoff
RGoffhigh
monolithic

IRGP30B120K(D)
IRG4PH30K(D)

4
3

DT04-4 revA

voltage gate drivers

RGoff 4
RGoff 35

85pF
14pF

ble 1: tsw driven

RGon sizing
(for RDRp = EFFECTS
7 )
PARASITIC
ELEMENT

GBT

Using monolithic high voltage gate drivers

Qge andQgc
Vge*
tsw dependent
Iavg
Rtot
Tsw
RGon
modelling
parasitic
component
on
the PCB
and std
ercommercial
stage it is value
very important
to know the effects of inductive
In figure 5 a single-phase motor drive power stage and its driver is shown. Some of the

GP30B120K(D)
19nC
82nC
9V
400ns
0.25A
24
RTOT - RDRp
= 17 elements.
18 In420ns
power
section
layout
and
related
connections.
parasitic
normal operation mode the fast voltage
characteristics
of the
driver
and
the power stage will be analyzed.
G4PH30K(D)
10nC
20nC
9V
200ns
0.15A
RTOT - RDRp = 33
40
200ns

Another way to size the gate resistors is following power variations, induced by a fast current change, may influence
L
R
DC+ (high voltage supply)
dissipation
This(for
wayRis
not investigated here.
the gate driver performances.
ble 2: dVOUT/dt drivenconstraints.
RGon sizing
DRp = 7 )
In presence
high and low power signals both referenced
GBT
Qge
Qgc
Vge* CRESoff Rtot
RGon std commercial
value ofdVout/dt
1
This
is
true
under
the
assumption
that
gate
voltage
remains
to
the
same
ground,
it is important to avoid ground loops on
Q
GP30B120K(D)
19nC 82nC 9V
85pF
14
RTOT - RDRp = 7 8.2
D V 4.5V/ns
result14pF
is reasonable
is= 78board
planes close to the switching portions of the
G4PH30K(D) fixed during
10nc dV/dt.
20nC The9V
V
85whenever
RTOT -CIES
RDRp
or
82 ground

5V/ns
at least two order of magnitude greater than CRES).
board.
This
solution
reduces the noise coupled to the local
high side
V
L
ble 3: RGoff sizing
driver
ground of the driver. Moreover it is suggested to make star
C
low
V
LOAD
GBT
Vth(min) ELEMENT
CRESoff RGoff
PARASITIC
EFFECTSvoltage
connections between ground pins and board ground for all
supply
GP30B120K(D)
4
85pF
RGoff 4
V
gate drivers
(see layout tips).
L
low side
G4PH30K(D)
3
14pF
RGoff 35
driver
In figure 5 a single-phase motor drive power stage and
its
DT04-4 revA
ARASITIC ELEMENT EFFECTS
driver is shown. Some of the characteristics of the driver
and
COM below Ground (Vss-COM)
GATE DRIVER
Q
V
D
Using monolithic high voltage gate drivers
the power stage
will drive
be analyzed.
properly
the powfigure 5 a single-phase
motor
power To
stage
and drive
its driver
is shown. Some of the
COM
aracteristics of the driver and the power stage will be analyzed.
Low side IGBT is considered to explain COM below Vss
L
R event.
Figure
6 shows one of the possible configurations of
COM
below
Ground
(Vss-COM)
L
R
DC+ (high voltage supply)
the parasitic
elements
in the
bridge
GND
Low side IGBT
is considered
to explain
COMhalf
below
Vss configuration
event. Figure 6 (here
shows one of the
DC+

DC+

FDH

FDL

CC

VCC

OUT

SS

DC+

DC-

DC+

DC-

possible configurations of the parasitic elements

Figure 5: Parasitic elements
in theis power
sense shunt
included stage
for completeness).
QH

DH

in the half bridge configuration (here emitter

VFDH

To properly drive the power stage it is Vvery important to know the effects of inductive parasitic
elements. In normal operation
high side the fast Lvoltage variations, induced by a fast current change,
V mode
driver
may influence the low
gate driver
performances.
C
V
LOAD
voltage
In presence of high
and low power signals
both referenced
to the same ground,
it is important to
V
supply
avoid ground loops on boardV or ground planes
close
to
the
switching
portions
of
the board. This
L
R
low side to the local ground of the driver. Moreover
C
solution reduces the noise coupled
it
is
suggested to
driver
make star connections between ground pins and board ground for all gate drivers (see layout
V
COM
GATE DRIVER
tips).
Q
V
D
S

CC

VOUT

LL

VCC

ILOAD

OUT

CC

SS

GOFF

VCC

ON

SS

FDL

QL

DL

VFDL

VE

GATE DRIVER

COM

LDC-

VG

RSENSE

RDC-

GND

LDC-

GND

RDC-

Figure 6: Parasitic elements during low-side turn-off

Figure 5: Parasitic elements in the power stage

Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold

properly drivewww.irf.com
the power stage it is very important to know the arrow).
effectsAsofthe
inductive
parasitic
power device
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in the parasitic inductance (LDC-)
changes
rapidly
and
the
induced
pushes COM below ground. The amount
ments. In normal
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the
fast
voltage
variations,
induced
by
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fast
current
change,
For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us voltage
at www.irf.com
DT04-04of voltage
flyback is governed by the well known law:
y influence the gate driver performances.
dI L
presence of high and low power signals both referenced to the same
to
= LDC it is important
.
VL ground,
dt board. This
oid ground loops on board or ground planes close to the switching portions of the
This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of
ution reduces the noise coupled to the local ground of the driver.load
Moreover
current. it is suggested to
DC

dc

RGOFF

CVCC

VG

QL

ON

Using Monolithic High Voltage Gate Drivers

VSS

DL

VFDL

VE

COM

GATE DRIVER

RSENSE

NOTES: IGBT short circuit desaturation easily generate high

emitter sense shunt is included for completeness).
collector
dV/dt. IGBT gate is pulled above the local supply by
Consider to turn off
(dotted
arrow)
the
low
side
IGBT
when
GND
LDCR
load current is flowing through it (bold arrow). As the power the
DC-gate-collector stray capacitance.
In some cases (usually when turn-on resistor is low) a fast
device turns off the current flowing in the parasitic inductance
Figure 6: Parasitic elements during low-side turn-off
pro(LDC-) changes rapidly and the induced voltage pushes COM diode is needed between IGBT gate and local supply to DT04-4
revA
tect
the
driver
output
(figure
8).
below
ground.
Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold
Using
monolithic
gate drivers
As an alternative
solution a zener
clamp
can
be
beThearrow).
amountAs
of the
voltage
flyback
is governed
the current
well
) voltage
power
device
turns offby the
flowing
in the parasitic
inductance
(Lhigh
DC-placed
changes
rapidly and the induced voltage pushes COM below ground. The amount of voltage
known
law:
flyback is governed by the well known law:
DC+

dI LDC
dt

.
DG

DH

RT

VLdc = LDC

R
T

Pn

SH
O

ONp

SH
O

This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of
load
current.
This
equation
relates COM undershoot (strictly dependent
DT04-4 revA
For
this
first
solution
to turn off more softly the IGBT, by increasing the low side turn
on inductancereason,
voltage) the
to the
slope
of loadiscurrent.
VOUT
Using monolithic
high
voltage gate drivers
off resistor (respecting the superior limit, see sizing the turn-off gate resistor section),
to limit
the
For this reason, the first solution is to turn off more softly the
dIL/dt.
R
CGC DC+
D
IGBT, by increasing the low side turn off resistor (respecting
VCC
RGATE
the superior
limit, see
sizing
gate when
resistorinsection),
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This solution
may
bethe
notturn-off
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These
IGBT.
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D
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V
This solution may be not sufficient when in presence of a
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Vcc
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VG
phase-DC+
shortinducing
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In that case the solution shown in figure 7 prevents COM pin to follow IGBT emitter filtering
the
These kind of short circuits are usually broken turning off
under-Vss spike.
R
C
D
the low side IGBT. Short circuit detection may react when curV
R
(ON) desaturation
Figure
8:
Driver
output
protection
in
caseQof IGBT
rent has exceeded several times the rated current for normal
V
operation inducing faster current change at turn-off. As an alternative solution a zener clamp can be placed between IGBT gate and emitter. It should
V
Vcc
In that case the solution shown in figure 7 prevents COM
pinDT04-4
be sized
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revA
The advantage
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driver output,
sinking
the currenttogenerated by
tween
IGBT
gate
and to
emitter.
should
be sized
accordingly
to follow IGBT emitter filtering the under-Vss spike.
the collector dV/dt, and to keep IGBT gate-emitter voltage under control.
Using monolithic
voltage
gate
IGBTdrivers
gate-emitter
absolute
maximum
ratings.
RCOM should be taken into account
when sizinghigh
the turn-off
This is particularly
important DT04-4
during
IGBTrevA
turn-off
after short
circuit detection, while IGBT emitter
Figure
8: Driver
output protection
in
case
of IGBT
to DCstray
, see
figure
9). desaturation
spikes under The
VSS due
advantage
of inductance
the zener(LisDC-both
to
protect
the driver outUsing monolithic
high
voltage
gate
drivers
As an alternative
solution
a
zener
clamp
can
be
placed
between
IGBT
gatedV/dt,
and emitter.
put, sinking the current generated by the collector
and It should
be sized accordingly to IGBT gate-emitter absolute maximum ratings.
The advantage
of the
zener
is both to protect
the driver
output,
sinking the current generated by
to keep
IGBT
gate-emitter
voltage
under
control.
DC+
the collector dV/dt, and to keep IGBT gate-emitter
Desaturation voltage under control.
C
Vcc
This isimportant
particularly
during
IGBT
turn-off
after
short
This is particularly
duringimportant
IGBT turn-off
after short
circuit
detection,
while
IGBT emitter
and
www.irf.com
9
(LDC, see figure 9).
spikes under VSS due to DC- stray inductance
DC+ recirculation
during
C
circuit
detection,
while
IGBT
emitter
spikes
under
VSS
due
to
R
turn-off
C
Vcc
OUT

CC

ONp

Pn

GC

GATE

COM

Vcc

GOFF

ON

Vss

COM

CVcc

gate-collector

RGOFF

Desaturationcoupling
and
DC+ recirculation during
VCC turn-off

COM
ON

GATE DRIVER

Vss

COM

RCOM

GATE DRIVER

Figure 7: CCOM and RCOM added

RCOM

gate-collector
coupling

CVCC
VCC

Figure 7: CCOM and RCOM added

VOUT

VG

ON

RCOM should be taken into account when sizing the turn-off resistance (that becomes RGOFF +
VSS
COM
C
RCOM).
RGOFF +
RCOM should be taken into account when sizing the turn-off resistance (that becomes
GATE DRIVER
sizingRestablishes
the timeRGOFF
constant
of COM pin that can be set to some hundred
RCOM and CCOM
resistance
(that
+ RCOM).
). becomes
COM
COM
of ns.
RCOM and CCOM sizing establishes the time constant of COM pin that can be set to someV hundred
VCC

ON

RCOMof and
CCOM sizing establishes the time constant of
ns.
COM pin that can be set to some
hundred of ns.
C
To avoid noise coupling to VCC size the rule COM << 1 as requiredC by the application.
GND
To avoid
noisenoise
coupling
to C
VCC
size
thethe
rule
size
rule COM << 1 asasrequired by the application.
To avoid
coupling
to
VCC
VCC
CVCC
GND
required by the application.

OUT
DC+

SS

VG

TURNING
OFF

VE
TURNING
OFF

VE

GATE DRIVER

LDCLDC-

NOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulledFigure 9: zener protection for IGBT gate-emitter
IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulled
above the local supplyNOTES:
by the gate-collector
stray capacitance.
Figure 9: zener protection for IGBT gate-emitter
above the local supply by the gate-collector stray capacitance.
In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate
In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate
and local supply to protect
the driver
(figure
and local
supplyoutput
to protect
the8).
driver output (figure 8).
For more information in North America call +1 310 252 7105, in Europewww.irf.com
cal l +49 6102 884 311, or visit us at www.irf.com
www.irf.com

LDC- flyback
LDC- flyback

DN04-04

11

11

DT04-4 revA

Using Monolithic High Voltage Gate Drivers

DC- stray inductance (LDC-, see figure 9).

Using monolithic high voltage gate drivers

Using monolithic
DT04-4
revA
DT04-4
revA
Using monolithic hig
DC+

Using monolithic
monolithic high
high voltage
voltage gate
gate drivers
drivers
Using

VS below Ground (Vs-COM/VSS)

DC+
DC+

DT04-4V revA
S

A well known event that triggers Vs to go below Vss or COM

high side
V
L
I
Using monolithic
high voltage
gate drivers
driver
DT04-4
revA
VSSforward
belowbiasing
Ground
(Vs-COM/VSS)
is the
of the(Vs-COM/VSS)
low side
V
below
Ground
high side
V high
V
side
V LOAD
freewheeling diode. This usually happens when current
driver
driver
A well
well known
known
event
that
triggers
Vs
to
go
below
Vss
or
COM
is
the
forward
biasing
of
the
low
side
A
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that
triggers
Vs
to
go
below
Vss
or
COM
is
the
forward
biasing
of
the
low
side
I
monolithic
high voltage gate drivers
V DT04-4 revA
flows out of theUsing
half-bridge
towards the
L
freewheeling diode.
diode. This
This usually
usually happens
happens when
when current
current flows
flows out
out of
of the
the half-bridge
half-bridge
towards
the
VSS
low side towards
freewheeling
the
driver
load.
load.
load.
V V
Using monolithic high voltage
gate drivers
In
state
VsVs
is clamped
below
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of
about:
Insteady
steady
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Vs
is clamped
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VSS
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lowlow
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SS

SS

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load.
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below
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And
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hat triggers Vs And
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InVsteady
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This usually happens
when current flows out of the half-bridge towards the

LDC-

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V
VV

COM == VV
VCOM
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LH

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LL LL

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IL

IL

driver
DL VFDLdriver

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steady
steady
Swell known event that
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ASsteady
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S
SS
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LH

SS

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steady
) below
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I LOAD Vss or COM is the forward biasing of the low side GATE DRIVER
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known
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SS
DC
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d (Vs-COM/VSS)
R
freewheeling diode. This usually happens when current flows out of the half-bridge towards
the
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VS

LDCL

RDCR

DC-

DFDL
V
DL V
L

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R

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DC-

under Vss
10: Elements
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s going
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forward
biasing
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side
) Ibelow
+Vs
RDCto go
GND
LOAD
GND
freewheeling diode. This usually happens when current flows out of the half-bridge
towards the
is positive
positive
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towards
the load.
load. Resistor between Vs and Vout
where
LOAD
load. IIILOAD
flowing
towards
the
where
is is
positive
flowing
towards
the load.
where
under V
Figure
10:
VsVgoing
LOAD COM:
And
below
Figure
10:Elements
Elementscausing
causing
s going unde
)
maximum
I LOADstate voltage
and VVssss or
orWhile
COMthe
can
be found
found
in the
the
datasheet
The
voltage
difference
between
Vss and
In steady
Vs
is clamped
below
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DC
COM
can
be
in
datasheet
maximum
difference
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V
above
mentioned
solution
may
work
in
normal
The
maximum
difference
between
and
VWhile
or the aboveoperating
mentioned conditions.
solution may work in normal operating conditions, it can be not
s
ss
absolute
maximum
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and
recommended
looking
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absolute
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recommended
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looking
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Resistor
between
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and
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steady
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as
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ground
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not sufficient,
an example,
Resistor
between
Vs
andbe
Vout
COM
can
be
found
in
the
datasheet
looking
for
V
absolute
VVS steadyCOM
=VVFDL (R
S
)
V
=
+
R

I
side
IGBT
is
on.
Once
the
high
side
IGBT
has
been
turned
off,
the
high
amount
of current that
S
SS may appear
FDL
SENSE commutation,
DC
LOADjust before
when
short circuit between
phaseclamping,
and ground occurs while
Major
issues
during
theafreewheeling
freewheeling
diode the
starts
clamping,
maximum
ratings
and recommended
operating
conditions.
Major
issues
may
appear during
commutation,
just
the
diode
starts
wasbefore
flowing
through
it starts
flowing
through
low-side
freewheeling
diode.in normal operating
While
the
above
mentioned
solution
may
work
-,
and
maythe
acthigh
pushing
In this
thisissues
case the
the
inductive
parasitic
elements
shown
in figure
figure
10the
(Ldcdcabove
While
solution
may
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normal operati
the
IGBT
ismentioned
on.
side
IGBT
hasinbeen
Major
may
appear
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LLLLexample,
and
LLHHOnce
)) may
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In
inductive
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(L
positive
flowing
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Icase
dI highside
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as-, an
whenact
a short
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And below
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FDL
down
Vs
below
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even
more
than
as
above
mentioned
for
steady
state
condition.
may
even
pull
VB
(the
floating
stage
supply)
below
ground
by
means
of the
The
high
sufficient,
as
an
example,
when
a
short
circuit
between
phase
and g
down
Vs below
Vssstarts
even
more than
as above
for steady
condition.
turned
off,can
the
high
of current
thatIGBT
was flowing
through
and Vss or
be amount
found
in
the
The
maximum
voltage
difference
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Vsmentioned
the
freewheeling
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side
IGBT
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on.
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the
highdatasheet
side
has been
turned off, the h
dt COM
The
derivative
terms
of
the
following
equation
may
be
the
highest
contribute
during
commutation
side
IGBT
is
on.
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the
high
side
IGBT
has
been
turned
off,
the
The
derivative
terms ofparasitic
the following
equation
be the
highest
contribute
commutation
maximum
ratings
and recommended
operating
conditions.
looking
for V
was
flowing
through
it during
starts
flowing
through the diode.
low-side freewheeling
d
itcapacitor.
starts
flowing
through
the low-side
freewheeling
S absolute
steady
In
this
case
the
inductive
elements
shown
inmay
figure
bootstrap was
This happens
when:
e flowing towards
the
load.
transient:
flowing
through
it
starts
flowing
through
the
low-side
freewheelin
V

COM
=

V
transient:
S
FDL
The high dI may even pull VB (the floating stage supply)
(Ldc-Vss:
,Vss:
LL and
) mayssact
down
belowinVssthe
even
or pushing
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datasheet
ge difference10between
Vs Land
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HmayVappear
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even starts
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For
Major
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during commutation,
justV tran
before
the
freewheeling
clamping,

V
<
Vhigh
even pull VB (the floating stage supply) belo
The
te maximum more
ratings
and
operating
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S
SS
CCdI
dtLmay
than
as recommended
above
mentioned
for steady
statethe
condition.
dI
-,
and
L
)
may
act
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Inwhere
this
case
the
inductive
parasitic
elements
shown
in
figure
10
(L
is
positive
flowing
towards
load.
I
tran
dI
dI
L
H
dc
L
H
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tran V
L capacitor.
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L )steady
=terms
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+below

bootstrap
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VV
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the
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SS =
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DCV+
Hmeans
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following
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the
down
Vs
even
more
as
state
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orLL )COM
can
in
the
datasheet
The
maximum
voltage
SS derivative
SS
FDL
SENSE
DC
LL V
s and
ssbootstrap
dt we
dt
capacitor.
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happens
should
be noted that
are considering
frequencywhen:
events, so that the bootstrap diode may
pear during commutation, just before the freewheeling diode starts
clamping,
dt
dt
pens
when:
The
derivative
of
the
following
equation
may be the
highest
contribute
during commutation
absolute
maximum
ratings
and recommended
operating
conditions.
looking
for VS terms
contribute
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COM:
tran turned off.
LL and LH) mayreasonably
act pushing
ctive parasitichighest
elements
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in figure
10 (Ldc-,transient:
For
COM:
Vkeep
VSS < VCC
transient:
S
tran
Vss:
even more thanFor
astran
above mentioned for steady
condition.
dIstate
dIHH just before
V for monolithic
freewheeling
VSS < ICs
VisCCcaused
dI
dI
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Vss:
tran
Major
mayV
diode
clamping,
LLcommutation,
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by starts
the amount
of current stolen from VB pin (via Cboot
V
COM
issues
Vappear
LLduring
LLHH during
S
FDL highest
L contribute
COM
of the followingV
equation
may==be
the
commutation
S
FDL
L
-,
L
and
L
)
may
act
pushing
Intran
this case the inductive parasitic
elements
shown
in
figure
10
(L
dt
dt
be placed between
coupling
with
VS).
In
order
to
minimize
this
current
a
resistor
(Rhigh
It
should
be
noted
that
we
are
considering
frequency
events,VS
so th
dc
L dI
H
VS) can
dI
dt
dt
L be noted that
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Itshown
should
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)
(
)
Vdown
V
V
R
R
I
L
L
L

and
Vout
as
in
figure
11.
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should
be
noted
that
we
are
considering
high
frequency
events,
so
Vs
below
Vss
even
more
than
as
above
mentioned
for
steady
state
condition.
reasonably
keep
turned
off.
S
SS
FDL
SENSE
DC
L
DC
L
H
dtsoinductances
dt
events,
that
the
bootstrap
diode maythe
reasonably keep
reasonably
keep
turned
off.
The
derivative
terms
of
the
following
equation
may
be
the
highest
contribute
during
commutation
In
order
to
reduce
the
slope
of
current
flowing
in
the
parasitic
so
to
minimize
In order to reduce the slope of current flowing Suggested
in the parasitic
inductances
soof to
minimize the
in the
rangeconstraints
some
valuesdamage
for RVS are
For
COM: terms, RGOFF can
dI Lbe increased,
dI H respecting
Real
for
monolithic
ICsOhms.
is caused
by the amount of current sto
transient:
turned
off.
previously
discussed
(RGOFF
derivative
GOFF
can
be
increased,
respecting
previously
discussed
constraints
(R
terms,
R
GOFF
)
(
)
L
L
L
I
(R SENSE + Rderivative

Vss:
DC
L
DC
L
H
coupling
with
VS).
In
order
to
minimize
this
current
a resistor
(RVS) c
dI
dI
Real
damage
for
monolithic
ICs
is
caused
by
theamount
amount
of current
For
sizing
section)
.
tran
L
H
Real damage for monolithic ICs is caused by
the
NOTES: and
section)

LH dt
Vsizing
COM =. VFDL LLdt
S
Vout
as shown
in
figure
11.
coupling
with
VS).
In
order
to
minimize
this
current
a
resistor
(R
dI
dI
in Lstolen
series tofrom
the bootstrap
resistor
andcoupling
must be with
considered
1. Rof
dt
dt
Cboot
VS). Inin sizing the VS
H pin (via
VS works
)
V Stran V SS = V FDL (R SENSE + R DC ) I L (L DC bootstrap
Lcurrent
L(RHBOOT *=inVB
+and
resistance
Vout
asshown
figure
11.
L
R
+R
).
VS
dI L For COM:
dI
) can
be Ohms.
placed
order
to dt
minimize
this
current
(RVSof
the
range
some
Suggested
values
fordt
RBOOT
VS areainresistor
InLHorder
Hto reduce the slope of current flowing in the
2. Itparasitic
is also important
to notice thatso
theto
current
developed
across RVS during initial bootstrap
DL LL
inductances
minimize
the
For COM:
between
VS
and
Vout
as
shown
in
figure
11.
dt derivative
dt terms, R
are
in
the
range
of
some
Ohms.
Suggested
values
for
R
charge may be such
that a relevant
high side IGBT
VS voltage is developed between the
discussed
constraints
(RGOFF
GOFF can be increased, respecting previously
NOTES:
dI
dI
emitter
and
the
VS
pin.
This
voltage
may
be
brought
to
the
high
side
output
Suggested values for RVS are in the range of some Ohms. (usually HO)
tran section) .
L
H
sizing
VS flowing
COMin =the
Vparasitic
LH so to minimize
in series
1.
RVS works
through
the HO-VS
ESD protection
diode.to the bootstrap resistor and must be
FDL LL inductances
NOTES:
he slope of current
the
dt
dt
*= Rbootstrap
bootstrap
resistance
BOOT
BOOT+RVS).resistor and must
the
1. RVS works in series(Rto
OFF can be increased, respecting previously discussed constraints (RGOFF
NOTES:
2. bootstrap
It is also important
to
notice
that
current developed across
resistance (RBOOT*= Rthe
BOOT+RVS).
In order to reduce the slope of current flowing in the parasiticcharge
inductances
so
to minimize
the
may
be
such
that
a
relevant
voltage is developed be
In order to reduce the slope of current flowing in the para2. It is also important to notice that the current developed acro
discussed
constraints
derivative terms, RGOFF can be increased, respecting previously
emitter
and the VS
pin. This (R
voltage
GOFF may be brought to the hig
charge
may be
such
that aresistor
relevant
1. RVS works
in series
to the
bootstrap
andvoltage
must is developed
siticsizing
inductances
so. to minimize the derivative terms, RGOFFwww.irf.com
can
through the HO-VS ESD protection diode.
section)
13
emitter
and
the
VS
pin.
This
voltage
may
be considered in sizing the bootstrap resistance (RBOOTbe
*= brought to the
be increased, respecting previously discussed constraints
through the HO-VS ESD protection diode.
RBOOT+RVS).
(R sizing section).

clamped

GOFF

Resistor between Vs and Vout

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DN04-04

12
12

Using Monolithic High Voltage Gate Drivers

2. It is also important to notice that the current developed

across RVS during initial bootstrap charge may be such that
a relevant voltage is developed between the high side IGBT
emitter and the VS pin. This voltage may be brought to the
DT04-4 revA
high side output (usually HO) through the HO-VS ESD protection diode. In this case it must be verified that IGBT gate
Using(gate
monolithic
high
voltage gate drivers
doesnt turn on at bootstrap start-up
resistor and
gateemitter capacitance help to filter out this pulse). This may
In this casecause
it must
be verified
that IGBT
gate doesnt
a short
shoot-through
at inverter
output.turn on at bootstrap start-up (gate
resistor and gate-emitter capacitance help to filter out this pulse). This may cause a short
shoot-through at inverter output.
3. RVS
also part
in turn-on
(RGON
+RVS) an
turn-offsizing
resis-(RGOFF+RVS) as shown
parttakes
in turn-on
(RGON
+RVS) an
turn-off
resistor
3. RVS takes also
in figure 12.tor sizing (RGOFF+RVS) as shown in figure 12.
Rboot

Dboot

DC+

VB

VCC
ON

Cboot

RGON
QH

VSS

DH

RGOFF

OFF

VS

RVS

GATE DRIVER

VOUT

QH

DH

Figure 11: RVS connection

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DN04-04

DT04-4 revA
DT04-4
revA
Using monolithic high voltage
gate drivers

Using Monolithic High Voltage Gate Drivers

RBOOT

Dboot VCC

RBOOT

Dboot

VB
VSS
VB

VCC

CVCC

VCC

DC+
VB

Cboot

VSS

CVCC

RGOFF

OFF

OFF

VSS

OFF

QH

Cboot

RGOFF
RGOFF

QH

QH

GATE DRIVER

DH

RVS
QH

DH

RVS
RVS
RVS

RBOOT

CVCC

VCC

CVCC
VOUT

Cboot

ON

Cboot

GATE DRIVER
VS

VS DRIVER
GATE

VSS
VS
GATE DRIVER
GATE DRIVER

QH

RGON

VSCboot

Figure
12: Gate turn-on and turn-off with RVS
V
OUT

DC+

Cboot

VB

VB
VSS
VB
VSS

CVCC

VB

VCC

ON

DC+

ON

ON

VSS

VOUT
VOUT

CVCC

DH

VS
GATE
DRIVER

VSS
VS
GATE DRIVER

Dboot VCC
Dboot

DH

DC+

Dboot

RBOOT

VCC

RGOFF

VS Cboot

VS

DC+

Cboot

GATEOFF
DRIVER

CVCC

boot

RBOOT

DC+

VB

VCC

DC+
Using monolithic
high
voltage gate drivers
D
R
Using monolithic high voltage gate drivers
BOOT

Dboot

RBOOT

CVCC

DC+

Dboot

RBOOT

DT04-4 revA
DT04-4
revA
Using monolithic high voltage gate
drivers

RGON

QH

RGON
RVSQH

DH

QH

DH

RGON
RVS

DH

DH
VOUT

VOUT

RVS

VOUT

RVS

VOUT

Figure 12: Gate turn-on and turn-off with RVS

only the HV diode is used.
Clamping diode for Vs
Clamping diode forFigure
Vs 12: Gate turn-on and turn-off with RVS
The clamp
Figure 12: Gate turn-on and turn-off
with must
RVS be connected to COM pin (just in some cases
to
Vss
pin)
according
to device
Thissuch
information
In the previous
paragraph
it
has
been
supposed
that
D
Clamping
diode
for
Vs
switched
off datasheet.
considering
In the previous paragraph it has been supposed
that DBOOT keeps
BOOT
Clamping
diode
for
Vs
keeps switched
offacting
considering
such
events acting at high fre- can be usually found under the absolute maximum ratings.
events
at high
frequency.
Clamping
for
follows
VOUT, switched
VB can be
to VCC by
the
thisVs
assumption
is not
verified,
whilethat
VS D
off tied
considering
such
thediode
previous
paragraph
it has
been
supposed
quency. InWhenever
BOOT keeps
and
V
should
be
kept
inside
the
absolute
boostrap
diode.
In
this
case
the
difference
between
V
events
acting
at
high
frequency.
keeps
switched
off
considering
such
In
the
previous
paragraph
it
has
been
supposed
that
D
B
S
BOOT
Whenever this assumption is not verified, while VS follows
PCB LAYOUT TIPS
keeps Vswitched
off considering
In
theWhenever
previous
it has
been
supposed
that DV
maximum
specification
(see
datasheet):
be tied to Vsuch
this
assumption
isICnot
verified, while
BOOT
events
acting atparagraph
high
frequency.
S follows
OUT, VB can
CC by the
VOUTevents
, VB canacting
be tiedattohigh
VCC by
the
boostrap
diode.
In
this
case
frequency.
and
V
should
be
kept
inside
the
absolute
boostrap
diode.
In
this
case
the
difference
between
V
Whenever this assumption is not verified, while VS followsB VOUT, SVB can be tied to VCC by the
theWhenever
difference
between
V
and
V
should
be
kept
inside
the
Distance
from
high
to
low
voltage
follows
V
,
V
can
be
tied
to
V
by
the
this
assumption
is
not
verified,
while
V
maximum
specification
(see
IC
datasheet):
S
OUT
B
CC
B
S
and
V
should
be
kept
inside
the
absolute
boostrap
diode.
In
this
case
the
difference
between
V
VB VS < VVBS _ abs max
B
S
boostrap
diode.
In this case
the
difference
absolute
maximum
specification
(see
datasheet):between VB and VS should be kept inside the absolute
maximum
specification
(see
IC IC
datasheet):
maximum
specification
(see IC datasheet):
minimize
noise coupled
between
VInB order
VS <toVVBS
_ absin
maxspecification, a clamp device To
andsignals
VS asreferred
keep
should
be the
positioned
between
VSS the
VB Vshown
to
ground
and
those
floating
its
strongly
recommended
to
S < VVBS
_
abs
max
in figure 13, where a zener diode and a 600V diode are placed.
VB VInS order
< VVBSto_ abskeep
max in specification, a clamp deviceplace
components
tied to between
floating voltage
in the
VShigh
as voltage
should
be positioned
VSS and
Zener
voltage
must
be asized
the
rule:
shown
in
13, where
a zener
diode
and
ashould
600V
are placed.
and
V
as
order
keep
in specification,
afollowing
clamp
device
be
V
SS
Scomponents
InInorder
to to
keep
infigure
specification,
clamp
device
should
be
sidediode
of positioned
device
(VB, Vbetween
side)
while
the
other
in the
S
In
orderinto
keep13,
in where
specification,
adiode
clamp
device
should
be
positioned
between
VSS and VS as
shown
figure
a
zener
and
a
600V
diode
are
placed.
positioned between VSS and VS as shown in figure 13, where a opposite side.
shownZener
figure
13, where
a zener
andthe
a 600V
voltage
mustVbe
sized diode
following
rule: diode are placed.
Vinand
V600V
Z a
VB _ absdiode
max are
CC
zener
diodevoltage
placed.
Zener
must be sized
following the rule:
Zener
be sized
the rule:
Ground plane
Zenervoltage
must
besized
following
the rule:
Vvoltage
Vmust
Vfollowing
VBof
_ abs
maxcases
CCthe use of a zener is not necessary, and only the HV diode is used.
InZ most
the

VZ VVB _ abs max VCC

VZ In
VThe
VCC
plane
not
placed
under or
VB
_ abs
max
clamp
bethe
connected
COM
(just inGround
some
cases
to Vss
pin)
according
to nearby
devicethe high
most
of themust
cases
use of a to
zener
is pin
not necessary,
and
onlymust
the
HVbe
diode
is used.

floating
tomaximum
minimize
noise
coupling.
Thisthe
information
can be
found voltage
under
the
absolute
ratings.
In mostdatasheet.
of the cases
use of a zener
is usually
not necessary,
and only
the side
HV diode
is used.
In
most
of
the
cases
the
use
of
a
zener
is
not
necessary,
and
only
the
HV
diode
is
used.
The
clamp
must
be
connected
to
COM
pin
(just
in
some
cases
to
Vss
pin)
according
to device
In most of the cases the use of a zener is not necessary, and
datasheet.
informationtocan
be usually
under
the absolute
maximum
ratings.
The clamp
must This
be connected
COM
pin (justfound
in some
cases
to Vss pin)
according
to device
The
clamp This
mustinformation
be connected
pinfound
(just under
in some
to Vss
pin) according
datasheet.
can to
beCOM
usually
thecases
absolute
maximum
ratings. to device
datasheet. This information can be usually found under the absolute maximum ratings.

15

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15
15

15

DN04-04

DT04-4 revA

Using Monolithic High Voltage

Gate Drivers
Using monolithic high voltage gate drivers

RBOOT

VB

VCC

Using
monolithic
high voltage
a voltage across the gate-emitter
increasing
the possibility
of
self turn-on effect. For this reason is strongly recommended to
place the gate resistances close together and to minimize the
IGC
loop area (see figure 14).

DC+

Dboot

ON

DT04-

VB/ VCC

Cboot

gate
resistance

CGC

Routing and placement example

CVCC
QH

DH

gate

HOP/LOP
HON/LON

We consider, as example, the IR2214 a high voltage and high

output current gate driver, seeGate
the lead
Drive assignments in figure
Loop
GATE DRIVER
VGE
15.
RVS
Figure 16 shows one of the possible layout solutions using a
VOUT
VS/COM
3 layer PCB. This example takes into account all the previous
considerations. Placement and routing for supply capacitors
Figure
14:
gate
loop side minimize
and gate resistances
in the
high
anddrive
low voltage
Figure 13: Clamping structure with zener diode
respectively supply path and gate drive loop. The bootstrap
diode is placed
under the device to have the cathode as close
Routing and placement
example
B LAYOUT TIPS
as possible to bootstrap capacitor and the anode far from high
Supply capacitors
We consider, as example,
voltage and high output current gate driver
voltagethe
andIR2214
close to aVCChigh
.
ance from high to low voltage
lead
assignments
in
figure
15.
If the output stages are able to quickly turn on IGBT with
minimize the noise coupled between the signals referred to ground and those floating its
high
value
of current,
the supply
must in
bethe
placed
gly recommended to
place
components
tied to capacitors
floating voltage
high as
voltage side of HIN
1
DSH
24
while as
thepossible
other components
in
the
opposite
side.
ce (VB, VS side)close
to the device pins (VCC and VSS for the ground
VB
LIN
N.C.
FLT_CLR
tied supply, VB and VS for the floating supply) in order to miniund plane
SY_FLT
HOP
mize parasitic inductance/resistance.
VSS or COM
(see comments)

RGON

VS

FAULT/SD

nd plane must not be placed under or nearby the high voltage floating side to minimize noise
ling.

HON

SSOP24
Gate drive loops
SSDL
SSDH
N.C.
COM
ply capacitors
N.C.
LON
Current loops behave like an antenna able to receive and
N.C.
e output stages are able to quickly turn on IGBT with high value of current, the supply LOP
EM
noise.
In order to
to the
reduce
EMpins
coupling
andVSS
im-for the ground VCC
N.C.
citors must betransmit
placed as
close
as possible
device
(VCC and
VS for the
in order
to minimize
parasiticgate
inductance/resistance.
supply, VB and prove
12
N.C.
DSL
13
the floating
power supply)
switch turn
on/off
performances,
drive
loops must be reduced as much as possible. Figure 14 shows
e drive loops
the high and low side gate loops.
Figure 15: IR2214 lead assignments
ent loops behaveMoreover,
like an antenna
able
receive
andinside
transmit
order to reduce
current
cantobe
injected
the EM
gatenoise.
drive In
loop
DT04-4
revA
coupling and improve the power switch turn on/off performances, gate drive loops must be
Figure 16 The
shows one of the possible layout solutions using a 3 layer PCB. This exam
the IGBT
collector-to-gate
capacitance.
ced as much asvia
possible.
Figure
14 shows the parasitic
high and low
side gate loops.parinto
account
allcollector-to-gate
thegate
previous
over, current asitic
can be
injected inside ofthe
loop via high
thetoIGBT
auto-inductance
thegate
gatedrive
loop
contributes
develop
Using
monolithic
voltage
driversconsiderations. Placement and routing for supply capac
gate
resistances
in
the
higha and low voltage side minimize respectively supply path
sitic capacitance. The parasitic auto-inductance of the gate loop contributes to develop
loop.
The
is placed under the device to have the cathode as
ge across the gate-emitter increasing the possibility of selfdrive
turn-on
effect.
For bootstrap
this reason diode
is
gly recommended to place the gate resistances close together
and toto
minimize
the loop
area and the anode far from high voltage and close to VCC.
possible
bootstrap
capacitor
IGC

figure 14).

irf.com

VB/ VCC

gate
resistance

VSS

VS

CGC

HOP/LOP
HON/LON

16
Gate Drive
Loop

VGE

VS/COM

Figure 14: gate drive loop

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uting and For
placement
example

consider, as example, the IR2214 a high voltage and highwww.irf.com

output current gate driver, see the
d assignments in figure 15.

DN04-04

DT04-4 revA
Using Monolithic High Voltage Gate Drivers

VGH

R2

D2

R3

Using monolithic high voltage gate drivers

DC+

R4

C1

VEH

VGL

D3

R5
R6

D1

IR2214

VCC

Phase

R1

C2

VEL

R7

Figure 16(a): TOP

Figure 16(b): BOTTOM

Referred to figure 16:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
Figure 16(c): Ground plane

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For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com

18
DN04-04