Transient Analysis of a Z-source Inverter with an Asymmetrical

Impedance Network
Jafar Adabi Firouzjaee
Department of Power
Mazandaran University
Babol, Mazandaran Iran
j.adabi@stu.nit.ac.ir

Abstract
This paper presents an analysis of a Z-source inverter
with symmetrical and asymmetrical Z-networks in order
to evaluate dynamic and transient performance of the
system. Large variations of inductors current during
switching time create problems in the Z-source such as
saturation of inductors and voltage distortion which
increase the total harmonic distortion of output voltage
and decrease the reliability of the system. This paper also
analyses the performance of the Z-source inverter with
and without lossy components. Simulation results confirm
that a system without losses is unstable due to tolerances
of capacitors and inductors. Resistors in series with the
inductors stabilize the system response and increase the
damping ratio. On the other hand, the resistors in this
system increase the losses and decrease the system
efficiency which shows limitations of the Z-network
applications. MATLAB simulations have been performed
to analyse these issues.

1. Introduction

Firuz Zare
School of Engineering Systems
Queensland University of Technology
Brisbane, QLD 4001
f.zare@qut.edu.au

the power source. The unique feature of the Z-source

inverter is that its output voltage can theoretically be
changed between zero and infinity. The main circuit of the
Z-source and its operating principle has been described in
[2].
A comparison between three types of inverters: traditional
PWM inverter, dc/dc boosted PWM inverter and Z-source
inverter for fuel cell vehicles are investigated in [3]. The
control methods, to obtain a maximum voltage gain and to
minimize the voltage stress across the inverter for any
desired voltage gain have been described in [4, 5].
Application of Z-source inverter for adjustable speed
drives by controlling the boost factor is presented in [7].
This paper presents a transient analysis of symmetrical
and asymmetrical Z-source inverters with and without
lossy components.

2. Circuit topology and operating states of a

three-phase ZSI
Fig.2 shows the topology of the three phase Z-source
inverter where the impedance network is placed between
the power source and the inverter.

Traditional voltage source inverter (VSI) and current

source inverter (CSI) are commonly used in many power
electronic applications. Recently, a Z-source inverter is
introduced as a new topology of power electronic
converters [2]. The ZSI is a buck-boost inverter that has
special features which can not be observed in the
traditional inverters.

Fig.2: A three phase Z-source converter

Fig 1: General structure of Z-source converter

Fig.1 shows a general representation of Z-source inverter

where impedance network placed between a converter and
a power source. A two-port impedance network which
consists of inductors L1 and L2 and capacitors C1 and C2
connected in a special configuration to provide an
impedance source (Z-source), coupling the converter to

As shown in table. I, a three phase Z-source inverter has

nine possible switching states: six active states (vectors)
when the dc voltage is impressed across the load, two zero
states (vectors) when the load terminals are shorted
through either the lower or the upper three switches and
one shoot through state (vector) when the load terminals
are shorted through both the upper and the lower switches
of any one leg or two legs or all three legs. These
switching states and their combinations introduce a new
PWM method for the Z-source inverter [2, 4].

Table. I: switching states of a three phase ZSI

Switching
S1 S4 S3 S6 S5
states
Active states
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
1
0
0
1
1
Zero states
1
0
0
1
0
1
0
1
0
1
1
1
S3 s3 S5
Shoot through S1
1
S5
s1 1
states
S1 s1 S3 s3 1
1
1
1
1
S5

1
0
1
0
0
0
1
0
s5
s5
1

s5
1

s3
1

S3

S1

s1
1

S2

V L1 = VC1 , V L 2 = VC 2
(1)
Assuming a symmetrical impedance network (C1= C2=C
and L1=L2=L), it can be observed that V L1 = V L 2 = V L
and I L1 = I L 2 = I L , the dc-link voltage across inverter
bridge during shoot through interval ( T0 ) is:
vi = 0
(2)
Fig.3.b shows ZSI in traditional active and null states and
due to symmetrical Z-network, inductors current ( I L1 , I L 2 )
and capacitors current ( I C1 , I C 2 ) are equal. The diode D at
the input side conducts and the voltage across the
inductors is:
V L = Vdc VC
(3)
The dc-link voltage across inverter bridge during non
shoot through interval ( T1 ) is:
vi = VC V L = 2VC Vdc
(4)
Therefore the average dc-link voltage across inverter
bridge during one switching cycle ( T ) is:
T .0 + T0 .(2VC V dc )
T1
Vi = 0
V dc
(5)
=
T
T1 T0
By applying T1 = T T0 in Eq.5:
T0
T V = 1 D0 V
Vi =
(6)
T0 dc 1 2 D0 dc
1 2
T
Where D0 is the shoot through duty cycle and Vdc is the
input voltage source.
1

3. Transient Analysis of Z-source Inverters

(a)

For transient analysis, impedance network is considered in

two states: without losses (with pure capacitors and
inductors) and with losses (resistors in series with
inductors). Load variations are studied to analyse the
dynamic response of the system including the inductors
current, and the capacitors voltage. For this purpose when
the system reaches to the steady state, a resistor (or an
inductor) is connected in parallel with the load and after a
proper time it is switched off. At first stage, a symmetrical
impedance network is analysed with C1=C2=C and
L1=L2=L. and with and without losses. But, in reality the
maximum tolerance of the capacitors and inductors are
defined 20% and in a worse case, the Z-source impedance
has C1=1.2C, C2=0.8C and L1=1.2L, L2=0.8L. This shows
an asymmetrical configuration of the Z-source inverter
which has been analysed in two sections.

3.1. Transient analysis

impedance network
3.1.1. Without losses
(b)
Fig.3: Operating modes of a Z-source inverter (a) shoot
through zero state (b) non shoot through states
Fig.3.a shows a shoot through switching state of the Zsource inverter where two switches of one leg or two legs
or all three legs are turned on simultaneously. In this state,
the diode D at input side is reverse biased and the
capacitors, C1 and C2 charge the inductors, L1 and L2
and the voltage across the inductors are:

with

symmetrical

Fig.4 shows a one-phase-leg dc-dc Z-source without

losses. A case study using the proposed system with the
following parameters has been performed. The input dc
voltage source is 500 volts and the inductors are
L1=L2=160 H and the capacitors are C1=C2=1mF.
Modulation index is 50% and switching frequency is 10
kHz. Load resistance, Rload1 and inductance, Lload are 3
Ohms and 1 mH, respectively.

3.1.2. With losses

As shown in Fig.7, Z-network losses are modelled with
resistors (R1=R2=0.1) in series with inductors (L1, L2).

Fig.4: Circuit diagram of Z-source converter without

losses
Fig.5 and Fig.6 show the inductor current and the
capacitor voltage of the impedance network, where
Rload2=3 is connected in parallel with Rload1 at t=0.06s
and disconnected at t=0.14s.

Fig.7: Circuit diagram of Z-source converter with losses

Fig.8 and Fig.9 show the inductor current and the
capacitor voltage of a symmetrical Z-network with losses
when Rload2=3 is connected in parallel with Rload1 at
t=0.06 s and it is disconnected at t=0.14s.

Fig.5. Inductor current in symmetrical impedance network

without loss
Fig.8. Inductor current in symmetrical impedance network
with losses

Fig.6. Capacitor voltage in symmetrical impedance

network without loss
These two figures show dynamic response of the system
and oscillations between the capacitors and the inductors
when a step change is happened in the load. Fig.3 and
Fig.4 show that the peak of inductor current in transient is
higher than the inductor current in steady state which may
saturate the inductors. Also the peak of capacitors voltage
in transient state is higher than capacitor voltage in steady
state which increases the voltage rating of the capacitors.

Fig.9. Capacitor voltage in symmetrical impedance

network with losses
Comparing Fig.5 and Fig.6 with Fig.8 and Fig.9, the
results show that the transient time of a symmetrical
impedance network without losses is almost four times of
a symmetrical system with losses and the peak of
inductors current decrease in the system with losses while
its efficiency is decreased.

3.2. Transient Analysis

Impedance Network

with

Asymmetrical

Because of 20% tolerance in capacitors (C1=1.2C,

C2=0.8C) and inductors (L1=1.2L, L2=0.8L) the
impedance network becomes asymmetric and to analyse
the system responses under this condition, simulations
have been performed and the results are discussed as
follows.

3.2.1. Without losses

In order to analyse a Z-impedance with different capacitor
and inductor values, two different impedance networks
have been considered for the asymmetrical network
without losses:
C1=1.2mF, C2=0.8mF, L1=L2=160 H, Fig.10 and
Fig.11 show that L1 current and C2 voltage with
symmetrical inductors and asymmetrical capacitors,
without losses.
L1=192 H, L2=128 H, C1=C2=1 mF, Fig.10 and
Fig.12 and fig.13 show L1 current and C2 voltage with
symmetrical capacitors and asymmetrical inductors,
without losses.

Fig.12. Inductor L1 current in impedance network without

losses, L1=192 H, L2=128 H, C1=C2=1 mF

Fig.13. Capacitor C2 voltage in impedance network

without losses, L1=192 H, L2=128 H, C1=C2=1 mF
Fig.10. Inductor L1 current in impedance network without
losses, C1=1.2mF, C2=0.8mF, L1=L2=160 H

As shown in Fig. [10-13], response time of the

asymmetrical system is longer than symmetrical system (3
times). Simulation results show that for an asymmetrical
system without losses, inductors current and capacitors
voltage have large variations during transient time which
may saturate inductors and damage capacitors due to over
voltages.

3.2.2. With losses

Fig.11. Capacitor C2 voltage in impedance network

without losses, C1=1.2mF, C2=0.8mF, L1=L2=160 H

For modelling the losses, resistors R1=R2=0.1 are use in

series with L1 and L2. In order to analyse a Z-impedance
with different capacitor and inductor values, two different
impedance networks have been considered for
asymmetrical analysis with losses:
C1=1.2mF, C2=0.8mF, L1=L2=160 H, R1=R2=0.1,
Fig.14 and Fig.15 show L1 current and C2 voltage with
symmetrical inductors and asymmetrical capacitors with
losses.
L1=192 H, L2=128 H, C1=C2=1 mF, R1=R2=0.1. ,
Fig.16 and Fig.17 show L1 current and C2 voltage with
symmetrical capacitors and asymmetrical inductors with
losses.

Fig.14. Inductor L1 current in impedance network with

losses, C1=1.2mF, C2=0.8mF, L1=L2=160 H,
R1=R2=0.1

Fig. [14-17] show that the dynamic response of the system

is improved by lossy components (which are modelled by
resistors in series with Z-network inductors). According to
the simulation results:
Transient time of an asymmetrical impedance network is
more than a symmetrical impedance network.
An asymmetrical impedance network without losses is
more unstable than a system with losses and transient time
of the system without losses is 6 times more than the
system with losses.
It seems that large variations of inductors current and
capacitor voltage in an asymmetrical impedance network
cause saturation problems which decrease the reliability of
the system.
Variation of load has more influence on inductors
current than capacitors voltage.
Increasing the resistance in series with the inductors
improves dynamic response of the system but decreases
the efficiency of the system.

4. Conclusions

Fig.15. Capacitor C2 voltage in impedance network with

losses, C1=1.2mF, C2=0.8mF, L1=L2=160 H,
R1=R2=0.1

In this paper, performance of a Z-source inverter with

symmetrical and asymmetrical impedance network with
and without losses is analysed. MATLAB simulation
results show that the system without loss is unstable and
use of resistors in series with the Z-network inductors
stabilizes the system and improve the system dynamic
response. On the other hand use of resistors in this power
converter system increases the losses and decreases the
system efficiency. Simulation results for inductors current
and capacitors voltage in asymmetrical impedance
network without losses confirm the large variations of
inductors current and capacitors voltage during transient
time; also peak of inductors current is many times more
than steady state current that may saturate the inductors.
Peak of capacitors voltage during transient time is more
than steady state voltage that increases the voltage rating
of capacitors.

5. References

Fig.16. Inductor L1 current in impedance network with

losses, L1=192 H, L2=128 H, C1=C2=1 mF,
R1=R2=0.1

Fig.17. Capacitor C2 voltage in impedance network with

losses, L1=192 H, L2=128 H, C1=C2=1 mF,
R1=R2=0.1

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