---------------------------------------------------------------------------------- Company:

-- Engineer:
--- Create Date:
14:11:16 06/20/2011
-- Design Name:
-- Module Name:
display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity display is port (
a:in std_logic_vector(3 downto 0);
d:out std_logic_vector(6 downto 0);
e: out std_logic;
f: in std_logic;
g: out std_logic;
h: in std_logic;
i: out std_logic;
j: in std_logic;
k: out std_logic;
l: in std_logic);
end display;
architecture Behavioral of display is
begin
process (A,f,h,j,l)
e <= f;
g <= h;
i <= j;
k <= l;
case a is
when "0000" => d <=
when "0001" => d <=
when "0010" => d <=
when "0011" => d <=
when "0100" => d <=
when "0101" => d <=

begin

"1000000";
"1111001";
"0100100";
"0110000";
"0011001";
"0010010";

when "0110"
when "0111"
when "1000"
when "1001"
when others
end case;

=> d <= "0000010";

=> d <= "1111000";
=> d <= "0000000";
=> d <= "0011000";
=> d <= "1111111";

end process;

end Behavioral;