SERIAL FAULT SIMULATION

ECE 565
DESIGN PROBLEM

Submitted by
Name :Rishub Muthoo
Reg no. :11003988
Section : E2E66
Roll no. :15

Submitted to
Ms. Tapsi Singh

SERIAL FAULT SIMULATION

Serial fault simulation is a simplest fault simulation technique. It consist of two simulation
first one is fault free simulation and second one is with fault simulation. The fault free
simulation result is kept as reference , to match the faulty circuit response with it. Any
violation with this means, there is fault in the circuit.
As per the flow chart given below, first fault collasping is done to reduce the fault list,then
fault free simulation is done and its result is stored. After this for every fault each pattern is
run and respective output is match with the fault free result,if there is any mismatch means
fault is detected.Then proceed to new fault.

For the given xor circuit, there is two fault :

1. on wire two (W1) :- stuck at zero
2. on wire four (W2) :- stuck at one
Here Z is fault free output,Zf is fault due to s-a-0 on W1 and Zg is fault due to s-a-1 on W2.
The program is given below, it simulate first fault free condition then ,faulty condition.

PROGRAM FOR SERIAL FAULT:

module test(z,zf,zg,a,b,c,ff,fw1,fw2,clk);
output reg z,zf,zg;
input a,b,c,fw1,fw2,clk,ff;
reg w1,w2,w3;
reg f1=0;
reg f2=1;
always@(clk)
begin
if(ff)
begin
assign w1 = a & b;
assign w2= ~b;
assign w3 = c & w2;
assign z= w1 ^ w3;
end
else if(fw1)
begin
assign w1 = f1;
assign w2= ~b;
assign w3 = c & w2;
assign zf= w1 ^ w3;
end
else if(fw2)
begin
assign w1 = a & b;
assign w2= f2;

assign w3 = c & w2;

assign zg= w1 ^ w3;
end
end
endmodule

TEST BENCH :
module tb_rishub_v;
// Inputs
reg a;
reg b;
reg c;
reg ff;
reg fw1;
reg fw2;
reg clk;
// Outputs
wire z;
wire zf;
wire zg;
// Instantiate the Unit Under Test (UUT)
test uut (
.z(z),
.zf(zf),
.zg(zg),
.a(a),
.b(b),

.c(c),
.ff(ff),
.fw1(fw1),
.fw2(fw2),
.clk(clk)
);
initial
begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial
begin
// Initialize Inputs
a = 0;b = 0;c = 0;ff = 1;fw1 = 0;fw2 = 0;
#5 a = 1;b = 0;c = 0;ff = 1;fw1 = 0;fw2 = 0;
#5 a = 0;b = 1;c = 1;ff = 1;fw1 = 0;fw2 = 0;
#5 a = 1;b = 1;c = 1;ff = 1;fw1 = 0;fw2 = 0;
#5 a = 1;b = 0;c = 1;ff = 1;fw1 = 0;fw2 = 0;
#5 a = 0;b = 0;c = 0;ff = 0;fw1 = 1;fw2 = 0;
#5 a = 1;b = 0;c = 0;ff = 0;fw1 = 1;fw2 = 0;
#5 a = 0;b = 1;c = 1;ff = 0;fw1 = 1;fw2 = 0;
#5 a = 1;b = 1;c = 1;ff = 0;fw1 = 1;fw2 = 0;
#5 a = 1;b = 0;c = 1;ff = 0;fw1 = 1;fw2 = 0;
#5 a = 0;b = 0;c = 0;ff = 0;fw1 = 0;fw2 = 1;
#5 a = 1;b = 0;c = 0;ff = 0;fw1 = 0;fw2 = 1;
#5 a = 0;b = 1;c = 1;ff = 0;fw1 = 0;fw2 = 1;

#5 a = 1;b = 1;c = 1;ff = 0;fw1 = 0;fw2 = 1;

#5 a = 1;b = 0;c = 1;ff = 0;fw1 = 0;fw2 = 1;
#5 $stop;
end
endmodule

Output:-

INPUT
PATTERN A B
P1
0 0
P2
1 0
P3
0 1
P4
1 1
P5
1 0

C
0
0
1
1
1

W1
0
1
1
1
1

INTERNAL
W2
1
1
0
0
1

W3
0
0
0
0
1

Z
0
1
1
1
0

OUTPUT
Zf
0
0
0
0
1

Zg
0
1
0
0
0