DESIGN AND VLSI

IMPLEMENTATION OF HDLC
CONTROLLER
Group Name:
Clarissa Nadya Arina
Meillyna Dewi Utary
Putri Eva Damayanti
Raesya Nugraha

TT-5C

The HDLC frame is synchronous.

The frames are separated by HDLC flag.
The header of the packet contains an HDLC address and
an HDLC control field.
The length of the address field is normally 0, 8 or 16 bits in
length and may be used allowing for multi-byte addresses.
The control field is 8 or 16 bits and defines the frame type;
Control or Data.
HDLC uses a process called bit stuffing.
At the end of the frame contains a Cyclic Redundancy
Check (CRC).

Design and Implementation

Data

Transmissi
on Host

The HDLC
Protocol Core

FCSs
transmitted.

Sampling of
CLK

Pemancar

Output
Register

Transmitted
Data in Pin
TxD

The host is
available

The Flag
Detection

Bit Port RxD

Penerima

Fig.2 Basic block diagram of CRC-16

SIMULATION OF HDLC CONTROLLER

A. Simulation result for 8-bit data, 8 bit address and crc-16

B. Simulation result of the final O/P at the receiver end for 8

bit data, 8 bit address and 16-bit crc

CONCLUSION
The HDLC controller has the capability to operate in full duplex

and half duplex mode.

The HDLC controller can automatically check frame sequence
generation using cyclic redundancy check, that is CRC-16 and
CRC-32 to ensure error free transmission.
The controller is compatible with all the protocols present at the
physical layer such as, Internet protocol (IP protocol), X.25
protocol & network layer.