me-proven project planning methodology

Library and hard macro sanity check

Floor planning, Macro placement, IO placement, power planning
Timing aware Floorplaing, planning of PLL placement
Placement of core logic, timing driven, congestion driven, OCV aware.
Clock tree synthesis and balancing on clock skew and system latency
Special clock tree planning and implementation, like double width, double space
Reset tree building , based on specification requirement
High fanout synthesis data skew balancing requirements
Routing of special net, analog net, critical nets, timing critical nets.
SI aware planning. and Implementation
Various technology based reliability check, like EM, IR, Antenna Effects, OCV and Jitter
Physical verification checks for design rules, density and LVS