JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

HYDERABAD
IV Year B.Tech.ECE-I SEM

E-CAD & VLSI LAB

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HDL Code to realize all the logic Gates.

Design of 2-4 Decoder
Design of 8-3 Encoder (without and with parity)
Design of 8-1 multiplexer
Design of 4 bit Binary to Gray Converter
Design of Multiplexer/Demultiplexer, Comparator
Design of Full adder using 3 modeling styles
Design of Flip Flops; SR,D,JK,T
Design of 4-bit binary, BCD Counters (Synchronous/Asynchronous reset) or any
Sequence Counter
10. Finite State Machine Design
11. Introduction to Layout Design rules
12. Layout, physical verification, placement & route for complex design, static timing
analysis, IR drop analysis and crosstalk analysis of the following:
Basic Logic Gates
CMOS Inverter
CMOS NOR/NAND Gates
CMOS XOR and MUX Gates
CMOS 1-bit full adder
Static/ Dynamic logic circuit (register cell)
Latch
Pass transistor
13. Layout of any combinational circuit (complex CMOS logic gate)- Learning about
Data paths
14. Introduction to SPICE simulation and coding of NMOS/CMOS circuit
15. SPICE simulation of basic analog circuits: Inverter/Differential amplifier
16. Analog Circuit simulation (AC analysis)- CS&CD amplifier
17. System Level design using PLL