NC State University

ECE Department

ECE 746
VLSI Systems Design

Page 1 of 4
Fall 2003

Final Exam
(December 9, 2003)

Name:
Problem
Points
Score

1
25

2
25

3
25

4
25

(25 points) Problem 1 (Transmission Lines)

(a) (10 points) Choose ZS and ZL such that the voltage swing at the destination is maximized
and the delay at the destination is minimized. Your answers should range from 0 to
for each impedance. Assume that the transmission line has inductance per unit length of
10-6 H/m and capacitance per until length of 410-10 F/m.

(b) (15 points) Assuming that ZL is infinite and ZS is 100 , how long will it take the
destination voltage to settle to within 20% of its final value?

NC State University
ECE Department

ECE 746
VLSI Systems Design

Page 2 of 4
Fall 2003

(25 points) Problem 2 (Sequential Circuits)

SHIFT
MUX
ALU
REG

tp
100 ps
30 ps
100 ps
30 ps

tcd
20 ps
20 ps
20 ps
20 ps

tsu
30 ps

th
-10 ps

(a) (15 points) Assuming = tCLK,REG2 tCLK,REG1, find the maximum and minimum values
for such that the circuit will still work properly. Ignore the input from the left.

(b) (10 points) Find the minimum clock period of this circuit. Assume that the skew is your
answer from part (a) (whichever would cause the circuit to be the slowest). Again, ignore
the input from the left.

NC State University
ECE Department

ECE 746
VLSI Systems Design

Page 3 of 4
Fall 2003

(25 points) Problem 3 (Arithmetic Circuits)

(a) (5 points) The shifter shown

is (circle one)
(i) Barrel shifter
(ii) Logarithmic shifter

(b) (5 points) The shift operation

implemented is (circle one)
(i) circular right shift
(ii) circular left shift
(iii) sign-extending right shift
(iv) sign-extending left shift

(c) (15 points) Find the propagation delay of this circuit, assuming that the X and Y inputs
arrive simultaneously. Assume no distributed RC effects for the long wires. Assume
each driver has an equivalent resistance of 10 k and input capacitance of 50 fF.
Assume each transistor has an equivalent resistance of 10 k, CSB and CDB of 10 fF and
gate capacitance of 20 fF.
HINT: Do not consider the delay through the drivers, but rather only their driving
capability (for X and Y) and their load (for Z).

NC State University
ECE Department

ECE 746
VLSI Systems Design

Page 4 of 4
Fall 2003

(25 points) Problem 4 (Memory)

VDD = 2V
WWL swings 0 to 2V
RWL swings 0 to 2V
BL1 precharged to 2V
BL2 precharged to 2V

Assume VTn=0.5 V, kn=100 A/V2, =0 V-1, VDSAT=0.7 V.

(a) (10 points) Assuming that VX is 1V at the beginning of a read operation, find the initial
(instantaneous) slew rate (in milivolts per nanosecond) for BL2. Assume that all devices
are minimum sized (270 nm/180 nm) and that the capacitance of BL2 is 2 pF. Ignore the
body effect.
HINT: You should only need to consider M3 (not M2).

(b) (15 points) Find the length of M2 needed to ensure that VX is 1V. Ignore the body effect.