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Asic Design Hnp3
Asic Design Hnp3
Asic Design Hnp3
Himanshu Patel
Space Applications Centre (ISRO)
hnpatel@sac.isro.gov.in
Contents
o
o
o
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Introduction
ASIC Design Methodologies
n Full custom
n Standard Cell
n Gate Array ASIC
n Structured ASIC
ASIC Design Flow
n Design Entry
n Functional Verification
n Synthesis
n Design For Test (DFT)
n Place & Route
n Timing Verification
n Formal Verification
n Proto ASIC Test
Mixed Signal ASIC
Challenges for Deep Submicron ASIC
CASE Study : OBC ASIC
Himanshu Patel
ASIC
o ASIC stands for Application Specific
Integrated Circuits.
o It means an integrated circuit designed for
a specific application.
o An application could be a microprocessor,
cell phone, modem, router, etc.
o Nowadays, ASIC has a complete system on
it, often called as System on a Chip (SOC)
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Full-custom
design
Each
primitive logic
function or
transistor is
manually
designed
Standard-cell
based design
Gate-array
based design
Structured
ASIC
Standard
library cells
(NAND,NOR,
XOR,FF etc)
are used for
design
Wafers are
pre-fabricated
with
unconnected
gate arrays
Wafers are
pre-fabricated
with
Standard
library cells
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Structured ASIC
o A Structured ASIC falls between an
Gate Array and a Standard Cellbased ASIC
o The design task involves mapping
the design into a library of building
block cells, and interconnecting
them as necessary.
o Largely Prefabricated
n Components are almost
connected in a variety of
predefined configurations
n Only a few metal layers are
needed for fabrication
n Drastically reduces turnaround
time
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Structured ASIC
Advantages:
o Low NRE cost
o High performance
o Low power consumption
o Less Complex
n Fewer layers to fabricate
Disadvantages:
o Lack of adequate design tools
o Design constrained by pre-fabricated block
available in library
ASIC Design Flow
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Comparison Graph
Full Custom
Cost
Standard Cell
Gate Array
FPGA
Volume
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3. ASIC Fabrication:
o GDS-II to ASIC chip
o Done by foundry
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Verification Flow
Specifications
IP Cores
Design Entry
(RTL Coding)
Functional Verification
(Behavioral Simulation)
No
ASIC
cell Lib.
Functionality
OK ?
Yes
Pre Layout
Timing Simulation
Testbench
coding
DRC
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DRC Error
Specifications
o The chip functionality is described in
Requirement & Specification Document
o The targeted speed, power consumption,
area are also specified
o System Engineer conveys requirement in
plain English to Design team and
Verification team
n Design Team generates RTL code as per specs.
n Verification team generates Test benches/test
cases as per specs
Back
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Design Entry
o Either by Scematic Capture or through
HDLs like VHDL,Verilog etc
o The quality of final chip depends largely on
quality of RTL code
o There are some design guidelines which
should be followed
n
n
n
n
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Testbench
Stimulus
Generator
Unit Under
Test
Output
Monitor
Test
Report
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Functional Verification
o The functionality of RTL code is verified using
testbenchs it is also called behavioral Simulation
o Some of the popular simulators :
n ModelSim
n NCSim
o Code coverage indicates how much portion of RTL
code is covered by testvectors
n Statement coverage
n Expression coverage
n Branch Coverage
n Toggle coverage
o Typically a good testbench achieves more than 95%
code coverage
Back
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o DFT methodology
RTL level
Netlist level
o DFT Advantages:
o DFT Disadvantages:
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MBIST
ASIC Design Flow
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JTAG Insertion
IEEE 1149.1 standard for Boundary Scan test
Back
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Synthesis
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Back
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n Undriven nets
n Naming convention errors
o DRC tool kit is provided by ASIC foundry
Back
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Verification Flow
Testbench
Timing
Constr.
Placement
Pre Layout
N/L
Post Layout
N/L
Formal Verification
Equivalence check
Routing
STA
GDS-II file
Netist
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No
Post Layout
Timing Simulations
Timing
OK ?
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Scan In
Scan Out
Scan Enable
ASICBack
Design Flow
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Floorplanning
o Floorplanning is a mapping between the
logical description (Hierarchical Netlist) and
the physical description (the floorplan).
The goals of floorplanning are to:
o arrange the blocks on a chip,
o decide the location of the I/O pads,
o decide the location and number of the
power pads,
o to minimize the chip area and delay
ASIC Design Flow
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Floorplanning
initial random floorplan
generated by a
floorplanning tool
Back
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Placement
o Placement is arranging all the logic cells within
the flexible blocks on a chip.
o objectives of placement
n Guarantee the router can complete the
routing step
n Minimize all the critical net delays
n Make the chip as dense as possible
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block A contains four rows of standard cells (A.211, A.19, A.43, A.25)
Back
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Back
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Back
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Routing
o Routing is done in 2 steps
n Global Routing : plans channels for routing between
blocks, Its goal are:
o Minimize the total interconnect length.
o Maximize the probability that the detailed router
can complete the routing.
o Minimize the critical path delay.
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Detailed Routing :
n complete all the connections between
logic cells
n exact location and layers for each interconnect
are determined
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Formal Verification
o Equivalence check between pre-layout and
post layout
o Mathematical models are made to check
functionality equivalence at each node of
netlist
o FV can also be done between RTL & Netlist
o EDA Tool
n Formal Pro (Mentor)
n Formality (synopsis)
Back
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Timing Paths :
o Input path (I/p pad to FF)
o Sequential path (FF to FF)
o Output path (FF to o/p)
o Combination path (i/p to o)
Back
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Back
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Power
o Increased DC power due to leakage
current
Signal Integrity
o Lower supply voltage reduces noise
margin
o Smaller geometries induces
coupling noise
o Higher current density causes EM
issues
Design Complexity
o Transistor Density doubles every
18 months (moors law)
o Clock frequency increases above 5
GHz
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ASIC Features
n CMOS Gate Array ASIC
n 256 pin package , 224 user I/Os
n 5 V core & 5V I/Os
n Radiation Hardened process
n Testability features like SCAN and ATPG with logic Fault
Coverage of > 95%
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DW8051
Synopsys DesignWare 8051
Soft IP Core
Features
o Highspeed architecture
:4 clocks per instruction
cycle 2.5X improvement
over the standard 8051
o Dual data pointers
o 3 Timers, 2 UARTs
o Extended Interrupts (7 nos)
o Variable length MOVX to
access fast/slow RAM
peripherals
o Fully static synchronous
design
ASIC Design Flow
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EEPPI - Architectute
clk
reset_n
8
Micro-controller
SFR
Interface
PPI
Ports
addr[7:0]
din[7:0]
dout[7:0]
Register
RegisterBank
Bank
Bank
6Register
XX88Bits
Bank
6Register
66XX8Bits
8Bits
Bits
6X8
bits
MUX
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48
Sfr_wr
reg sel
Port0_PPI [7:0]
Port1_PPI [7:0]
Port2_PPI [7:0]
8
8
Port3_PPI [7:0]
Port4_PPI [7:0]
Port5_PPI [7:0]
wr
Data out[2:0]
Look Up Table
Addr
(LUT)
(Event -Action)
6
64 X 3
bits
Flags
2
Timing_control_Sig1
MUX
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2
2
Event
Detect
Module
Timing_control_Sig0
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UART_RRS
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Thank You
To Probe Further :
http://Geocities.com/hnpatel81/asic.htm
ASIC Design Flow
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