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A Verification Methodology For Soc-Controlled, Highly-Integrated, Mixed - Signal and RF Ics
A Verification Methodology For Soc-Controlled, Highly-Integrated, Mixed - Signal and RF Ics
D. B. Walker
Sirenza Microdevices, Inc.
CDNLive! 2007 Silicon Valley
Session 2.11
Outline
Introduction
System
Problems
Example
Sirenza Solutions
Further Work
SoC System
RF
Mixer
IF
Mixer
Channel
Selection
LPF
2nd IF
PLL
Ref Freq
Vtune
Charge
Pump
Output
TX I/Q
Data
Input
RX
Output
~
PLL
Channel
Selection
LPF
SoC
PA
TX RF
Output
Baseband
Control
Problems
Sirenza Techniques
Analog
Analog Inputs
Analog Outputs
SoC
BC6502 Processor
(www.birdcomputer.ca)
Responsible for controlling
the DC Offset correction
P65 assembler
ROM
GPIO
RAM
ENABLE
CLK
C Core
Email:
dwalker@sirenza.com for
demo files.
End
Netlist Explicitly
Support Escape Names
Drop port range
p
o
SystemVerilog Models
Assertions
Types:
Inner-module
Checking within a module
Test module bound to the analog block
Intra-module
Checking between modules
Test module bound to the DUT
EN_AMP
Inp+
Out+
Inp
Out
I+I
DAC[7:0]
II
EN_DAC
EN_COMP
Need to model:
COMP
DAC
Delay of the amplifier to the comparator with respect to the DAC inputs
and block enables
A DC offset for the circuit to correct
Need to assure:
:
:
:
:
6us
5us
3us
2us
time
pointer to the bus fetch
register a contents
status register contents
mask indicating if any sr bits are 'x'
//
//
//
//
address of activity
data read/written
mask indicating x values
status of bus activity
Register
Contents
Bus Activity
Keep track of
Opcode and
Address
Mark address of
all instructions
fetched
Summary Statistics
Further Work
VerilogAMS integration
Instruction Trace
Firmware coverage