ABSTRACT

Wave-pipelining enables a digital circuit to be operated at higher frequency. In the

literature, only trial and error and manual procedures are adopted for the choice of the
optimum value of clock and clock skew between the I/O registers of wave-pipelined
circuits. The major contribution of this paper is the proposal for automating the above
procedure for the ASIC implementation of wave-pipelined circuits using built in self-test
approach. This is studied by a multiplier using dedicated AND gate by comparing in
three different schemes: wave-pipelining, pipelining and non-pipelining. Wave-pipelining
has been employed for implementing a number of systems on both ASICs and FPGAs .
The concept of wave-pipelining has been described in a number of previous works . The
technique of Wave-pipelining is proposed to improve the logic utilization by minimizing
the idle time and to allow for maximal rate of operation of the digital circuit.