Elimination of the Positive Zero in Fixed Frequency and Flyback Converters D.M. Sable, B.H. Cho, and R.B. Ridley _——— Its shown how a fined-fequency, leading-edge modolmed PWM can ‘eliminate the undearable postive zero in practical boom and fybac ‘Converters, ‘This alows a subsantal improvement in the closed-loop sets, Sreltehiguerar ampoved 1 pe hi el ‘esign procedure for elmination ofthe positive neo ie presented. Experimental veiication is provided. 1 INTRODUCTION ‘A. Background Suess greasing I pedis 3 poe re in the sono. ‘utpat tensfr fanction of boost and Ayback converters operating in tbe continuous mode, The 90 cope ph: ing sera) coerce te loop gain sressover to a frequency much lower than the righChat plane tro. This Emits the dynam performance ofthe converter ‘The PWM Switch Mode! [2 isan altemative average modelling tech- sigue that caer to implement in creit analysis programs sich a2 SPICE. ‘Tos small-signal characterises ofthe PWM rwntch movel re ‘ential to natespace averanng in the continuous conduction mode is used throughout this paper ‘Average modes, however, do not accurately predict the behsvor of power converters under ali dreumstancer It Nas been shown (3) that ‘when the eer compensation signal is pulsating due to the ESR of che ‘Output capacitance, that the Discrle~Aterage Model has better acu: ‘acy. The Disseae-Average Mosel employs the identical averasing of the sate variables The only ciflerence is that the outpat equation it sot averaged. The output equation of the converter power fate de- pends on the type of modulation that performed in the pole-widthe ‘odulator. This is desribed later in deta. Conventional PWM converter are designed with tang edge modo. Inion. In taing was modulation, the FM niga! turned ona tho et ol ot rel of when be oe pre ek Secor. mos commer svalabie PM Spee on tis pies" Howowr i fo a eny Yo empement ‘linge modal. in ending-cdpe mocuation, the PWHE a ee ree pe ea oven te amp wavelorn, ig shown thatthe positive zero can be eliminated from the power ‘age tranaer fUncton of booet and fivback regulators under stable Conditions. These conditions are a flows: 2 Ladingedes modaion ma be employ in the pale ‘3° idbck compension must aot sverags the ESR-peated ‘uipat velar aehing spl 5) Approprite power Spe parameter values are messy. 1B. Motivation “The motivation behind this study ovginated ater a stability analysis ofa spaceenh batery discharge employing a boost topology could wot ‘rede the converters exelent peformance and stably The cor ‘© 1990 IEEE. Reprinted, with permission, from Angeles, CA, March 11-16, 1990: pp. 205- Proceedings of the 349 verter, which was, ‘nthe early 19707, has been operating in {pace fawiesdy, for aboot 1S years The sabi analyse however. ‘Thich employed the aatespace Sveraging ecique, indicated that the ‘onverer sould be unstable Il, MODELLING TECHNIQUES ‘A. Waveform Analysis Systems that contain 8 rght-half plane zero, often refered to as non ‘Rinimam phase system, have a unique sep input response shown i Fig 1. The ootpr wil inially drop prior to nstng and reaching say te Sc Fi}, Naiman Phe Caner Sep Res, The Boece er total aed mochng S00 we a ———_ SYSTEM WITH RHP ZERO In boost and buck-boost derived converts, an incremental ep in- cone i duty ele tants © apestor hold-up time for th oat vgs ha il ce he eye out lage 1 i {aly drop wold the inductor cument boils up to recharge the ie” The lag time fom the iia drop und the valage recurs {9 the inal value is iverely proportions the pontve 2° Howe, geending onthe émanic of he dtu compensation setwork, the PWM cree proceso may respond tothe Putantanenus ‘utpat voltage.” When conventional tailigeoge modulation is em- $sloyed, the PWM responds to the istantancous voltage pict to the Ipeich tuning off "When leading edge modulation is employed. the YM repos tthe etantanaos otup Por the ch TUTENE Fig, 2. Somlated Boost Converter led Power Electronics Conference, Los EASFig. 2a shows a boost replter schematic that was simulated in SBicE: Fig ih snows the eich consat waver. At = 9 op incest in duty exe occu The inductor eurent ineete ng ‘mediately (abelee point on the tures The conta ocndtee Soren andr fncon deerme coin pose ewe gs 36 hows the voltage wavefory divetly sos the outwt cqaciton” At the rep increase duly ete captor solage waveform ay tops Pelore esoverng ‘Tis ia the sveoge capaci lag, wel as the instantaneous voltage afr the sch (Une ff bees point B on the figue) and the intantanenus voltage afer the swich {Toms of again (labeled point © onthe figure). The postive roca not he eiminues from the contealcagaitor Yoh test fone lon The capeter voltage i the mest the sree ours vo Fig 26 shows he output vobage waveform. At the inant that Sih i af 9g the dnp fg he Sa wohtage Gor isthe wahage op acoushe capastor ESR. At the sp increta in dtyejte, te snamancia oui soe, peo See a | 2 i tormofl. (labeled point D on the figure) tially drape 3° in the alas ons 608 Catan ‘capacitor voltage, Thus, when employing ratings modulation, the C2 Te eo J [Pontive zo ekanat be cminaed. ‘The istantanous output rope ‘TIME SECONDS) rior 10 switch tum on, (abeed pot & on toe fir) bower, eases. IU is a necestary condition for climinaion ofthe positive 20 Fig, 2b. lnductor Corrent Time Waveform. AC the step increase in dit {hat the insantaneous outpot voltage rior to switch urn on ineease Gye at t= ry the inducior crren! ionediateh ries iedcelng > ‘nego way erence tr duty ee. Thnivaependent fave nr nthe tly esl 6 det caret ener fox, Sn te power aducance,rapectans, oe fspanse ayer ESR the dy pce 0 Sn opening ety oe “ep tin of ti no ep i etn in fe postin vo Sai ors erie a se eee SRE a ae ee sata t hat o H(vOLTS) SEEREEREEE ‘The instantaneous capacitor vohage prior to the switch tuming on is ual tothe average Outpt voltage pts the change in eapcitor vole Siete he sees change Sore 5 c tae a &§ WWW ie g 8 Ti nananero ESR wing pooh wich moe ons cokes ome aobaa bala Coss vertiggtng My ae Fig, 2e-Capacito Voltage Time Waveform. A the step increase in ty the capacitr voltage weveorm deceatesprertentresiog. Tht te! ie he iy lo cpace vohege ater fino or Letd = D + d. The new value of the output voltage atthe instant Pies so ae ch tno op ded ne fe ia Presi tion of ie oes ay eee sa gaicy) o ‘To eliminate the postive er, the ew value of the output wate at the instant prior to the seth turing on must be preter thatthe old salve. ‘This eonditon i ren by: Roo ae ® B, Discrete-Average Model Mathematical Derivation ‘Suatespacesveraging is implementd by writing the stse equations and ‘output equation for the linear networks comepondiag the wich-on nd switch-off conditions. The equations are then weighted according ourrur vouracu vouts) SEER ER {othe switch-on and seth penods, Sx ldhy + ahr (eB, + 28 co) “Gams cnits 00s oom? ante mas wed eq a tel é Fig. 24, Output Voltage Time Waser. At the sep increare in duty “hg souom wr te te io tin eae Gi hay of men age mer (aly See ‘eall sgn Grout and the reuling tans functions. The Die. Pee to inrecalay. "The peak eee ear ‘Average Model fsa to te average ate in thatthe average Of reas immedi TPN the sate variables fe wed." However. the output volage is deermined ‘by discrete samples, The sumole point is dependent on whether 350 -= 8 at ps DT. Be vei ve PES ease wae vy | es weet ve jo--- tape SER oo Yo talling-edge or leading ede modulation it eoyploned Whon conven ional tramege modulation ts employed. the MUM respons othe instantaneous output voltage whe the switch is on in order to delet ‘mine the termination point of the on time oe ” ® When leading-sge modulation it employed. the PWV responds tothe retanuancous output volage ‘hile the swith ff in order to deter: ‘nine the termination poit of the of time wn Ge o ‘This leads 0 some subtle differences inthe contn-co-ouipa transfer faesion ofthe tree models. The controlto-puinot tanslerfoneion ofthe Average mode! is ven by Se TL Ut tle Mt = sto a DF + ge0+ Fhe a) where ay aa ‘Ths contro to-cutpt transi function ofthe Discrete-erage model for triing-edge adulation i Ben by SoM dadon i. 2 DP (+ se,0+Fho3) ‘The controlto-output transfer function ofthe Discete-Average model {or leading edge modulation i given by (1+ son) where ‘ RET DR, as = ‘This model predicts thatthe postive zero can he clminated vith leadingeige modulation providst thatthe felon condition i el Reo ae oi 06) SPICE Implementation of Discrete-Average Model ‘The Diseete-Average Model canbe easly implemented in SPICE. ing minor modifiation tothe PWM witch model For taling ede: modulation, the output equation i Ben by Ve Fig. 42. SPICE Implementation of Disete-Average Model with ‘Trailing Ede Modulation. ‘The velage vg" corresponds (0 the out voltage that the conrl lop sil veranda eng he erage ofa Fig. &._ SPICE implementation of Diserete-average Model with Leading: Fage Modiaton 351ak hy This SPICE implementation it shown in Vig 43, The feare in SPICE known ae dynamic mulipieaion of varishce [a] empioved for ees modeling af the PWM Block, For leting edge mdulstion, the output equation is given By ee Feehan as) “This SPICE implementation is shown in Fig. &, ‘Once the feedback loop i¢ closed, proper implementation of the Bicete-Avernge Model aleo eludes the sampling of the compen: Sation network output This deseied in ston Il. . Model Comparison “The boos rpulstor power stage of Fig 2 is modeled in SPICE with 3 techniques, averaging, diacree-avenigng wilh leading dpe modu. inton, and dacrete-averaging wih wauingedge medvlaton, Tig. $ Shows the conuolto-output tanser fyneuons that result from the three model There ave sigcant differences, especialy wih Fed te the phase, The postive pero ts apparent in the erage model and the Uralingredgr ducreteaverage model. &) stewing the asymptotic ‘phase response. It is abaon! fom the leadingedee diverie-a¥erage Irodel. This boost regulator can infact, behave ike any one ofthese {hee results, depending on the tpe of modulation and feedback com= penton, MAGNITUDE (08) CC ; e . i” ; oS. incanea Fig. 5. Coatr-to-Ouput Transfer Function of Average Model (A), Drcreicanrage, Modcl with Trailing Edge, Modulation ( ‘Discrete Average Mosel with Leading Ege Modulation (C)- IIL, COMPARISON WITH CURRENT-MODE CONTROL 1 singletop. leading-edge modulated boost converter hat many simi- lartis to a coneatimove controlled boost cemverer, tbe (WR! spies the emor signal thon the power switch off At this time the inductor euent is eharpng the ezpacitor and fcding the load.” The voltage acros the canactor ESR iF thus proportional to inductor cu Font. The compenation eetwork ampies this signal 10 produce Current sense ramped taveform. This is then compared wh She co {eral ramp ia the pube-withvmodulator Recent analpris of eument ‘mode cont [S] provider an accurate model of the modulator gain haracertie. Pig 6a block daar of the sytem. The gain of the ‘modulators Sven by 1 PEST, were 5, i the slope ofthe enor signal, and S; is the sore ofthe os: temal amp. ‘The curteat feedback loop in 2 chrrentmode conmoied regulator also has 3 frequency dependent elerent duc tothe samping nature ofthe system, "This is ven by a9 Nos leis an OS er oF : wher abo e an ence, athough the boost regulator positive zero is eliminated from the power sage, two aéiionsl postive zeroes located stone half he ‘itching frequency are iruosuerd dus va the sampling nature of the System. ‘These wo postive zeros limit the crossover frequency of ihe loop gain to below approximately one-fiflh of the setching Frequency ‘Tris much lee constraining, however, than the power slage post ‘em which can often limit eronover to below F,/30 el Fe. 6 Systm Block Diagrams Tas representation ofthe ptr con ‘ere and contra lap ensages al four f the pte sete vara ape a or ad eh of 352Proper implementation of the Diteme-Average Mode se incides thcTaampling of the compensation network euthat, In Fig. 6 the Compcnstnin network hae two adional state Vanables. fe and 3 The output equation of this network een Bw at Re 2, where Rite 2 ‘This output equation is implemented with the controlled sources and summing netetrk shown in Fig 6 The dependency of the modulator gain on the slope of the exor signa act to mitigate the effects of varying compensator gain ov (SR, For trample. a decease in ESR sl educe the pun ofthe POuCT age hy ‘mowing the tro to higher frequency. However. it wil Hereace the ‘odulatar gain by reducing the pple On the er signal IV. PRACTICAL CIRCUIT DESIGN ‘A. Power Component Selection ‘A boost converier is designed to the following specifications: j= 2-25v VSS Bvp—p Fase Rtv Sw ‘An inductor value of 35041 i chosen to alow fora + 157% cure frp at the low line, high load condlion, 690uF of capaciance with EVESR of 0.075nd2 ie wied to filter the ripple © the speed valve, The condition for elimination ofthe posive 2er0 ix met B. Leading-Edge PWM. Mos PWM IC's employ tniling edge modulation. Dy simpy iver ing the output ple, the leadingsose s modulated. To retin negative feedback in the conirol loop, the eror signal i ato invened. Most TWM IC's allow for an adjustable uty evele matimus lit. 4 ne cesity for boost regulators. Vowerer. the duly eyle masimium limit becomes a det eyete minimom once the output i ivened. ‘The uy crcl mit ean be externally conoled in scveral wayn In this iene ‘Relation, 4 s¥nchronized. sal containing 2 50°. mavimurt duty ele was ANDed with the PWM out C. Controt Loop Design {A two-pole and teo-rero compenstoris used in the control oon. The frst poke ts placed atthe orig for DC regulation. ihe en orbs ate ‘laced to ahuain the masimorn mihand gain and a ood phate margin bbe loop gain while miniming the system traicm expanse sing, Sime. ‘The fet vero was placed font afer the resonant fecueney 1 oid a conditionally stable system. The second 7¥0 3s placed at pprorimately twee the frequency ofthe first rer, The end pole (SiS placed 10 canes the 2% gr de Power sixge that ha Row Seen ‘moved tothe lefhall-plane. A wide bandwidth operational splier (LMa18) was employed to provide the necessary pam atthe ching Frequency, Fig? isa schematic diagram ofthe entre power converte civil ine ding power sage, PWM and contol V. SYSTEM MEASUREMENTS A. Loop Gain Measurement Sina ima oh ses pe te tt ee ge cause coarser a ea Seta planet ay a Seu cet nee coreceemed te TED ied ee ea ee oan Semele std yoo ae fh Fig. 7. Schematic Disgram of Entre Pomer Converter Circuit Fig, 8, Phowograph of Steady State Gate Drive Signal (20 V/Die, Error Signal (2 V/DR, and’ Output Voltage Waveform (02 ¥/Di AC). The slope ofthe error signal mile che owtch ts of partially de ermine! the gain of he modultor Inted. The amplitude modulation contains an upperside, correspond tng to when te such @ on ands lower ade eotraponding to when {0 switch @ ff The eral gust en phase information is Contained Inthe upper ade ofthe asptose modulation component, oweves the network anlyer inet al components The ene deve sera however, only duty eyele module. Thais the onl sal the roped : [un be employed (6. Pig 9 shows the theorctiea and exer {oop gun tater at the mutimam line and maximum load condition. ‘Toe theoretical and expenmental results ae in excelent agreement Up tp one-half of Ure swtching frequency.” The cosover oe shout 5 kll, which one of te switching frequency. The phase frargn ore 60 depres, lad this been 2 conventional tralng-edge ‘modulated boos converter, the system woul! have been unable. The euthe 29 would ve bee a abot 5 Re eau an ada £5 deges of phase lag a this frequency. Loop jain roster would fave been contned to beat about 2 to maintain 0 degrees of pha maps 1B. Measurement of the Contrl-to-Output Transfer Function Fig. 10 a photopaph ofthe ear signal and output voltage in the 353MaantfU06 (09) purse cance é ve To FREQUENCY 02 Fig. 9. Theoretical (oli tne) and Experimenal Loop Gain spd Out Votage ton Bou he eee signal and “aperte gal fo her ope kal of corsa ar opel of ecu age Fe 1 hoped oy feback air, The pase Ss kif of ie rokage ®sgeicnih greater tha lower haf of ere (ag of of the the top half. presence ofan external 3k, Siurbanee. The double-sided amplitude Froculation of the output voltage is clearly visible, There sa sgl. ‘Rant phaoe diference betwee the wp und wotiom halves. The wp BAL oer not contain the posiive aro whe the bottom half des. (ge would tke to mentire the cneielta-output wanes Function per to losing the loop. However. this not practic iy thi cr Eomuance Inthe err sal and outpt voltage are placal into the ‘Senet so tt ng aan ara eee wl a Shitvihe average model. The network anaiast average al the com: Fores ofthe ouput wokagesolching app, This tiem fue Fritat the open lnop plant characte infact denen on the ede Bock 'contal dynamic characterises Once the loop i elesd. the Contolto-outpet transfer function ean be indrelly measured by 236 ttaning the compensator transfer fonction fom The een ai.” This tmonurementrequver are aa well ance the compensator tt and Suipat are both dicontinuos. One posi. to employ & Spleand-holdcteuit However. the wl nroduce phsc cron that ton be counted for The lak of good measurement proedur ot {he controlto-output tanier function one drawback fortis tech: eee VI. CONCLUSIONS, {hasbeen Shown how the ghe-hall pratial boost convener creulte ated under the following conditions: 2 teint medalaion must be employed in the pet {DPropes power sage parameter aloes are necetany zero can be eliminated front Tehchalf-plane zero is cima L Ro DR, 23) The switching ripple most not be integrated by the contrat ioe. ‘The Discrete Average Mode! is used to predic this result. Its shown how the Discrete Average Mode! can be implemented in SPICE using 2 right variation ofthe PWM switch model This same erterion holds for fyback converter cteits."For Nyack converters, the inductance Cs the secondary inductance of the Mibacktansformet Ce a oe aoe : ‘The theoretical and experimental result indicate high stability margin 4nd wide bandwidth. Loop tin eronover i shown to be much higher than one could ofdinany expect sith» conventional Ualing-edge ‘modulated boos regulator: 1 shown that Yeading-cige modulation is ven, similar to. curent ‘made control in this case. By modulating the leading-edge. the output Spee cent ed y ening i von cmt ESR ‘caren ‘when the seth ir of is eual No tnguetor Curent ‘minus the load current. By providing a eflecve fedlorward ofthe load curent, this technique ensures excelent load transient response ted fs output pedance ‘There are several dimdvaniages of this technique. Measurement ofthe contel-to-gutput transfer Rincon cannot eauly be performed. Also, the positive zo elimination i dependent on the capactior ESR value (Capacitor ESR can olen change substantial over temperature, Small hangs n the ESR valve wil not effect the sabisty margin. This is ue fo te of the modulator gain on the crorsipal pple. However, retocion of the ESR well below the crtercn for postive evo elimination wil eect sytem sabilty. Fina, this technique can ‘Se mocepibie to noize nee the output vokage switching pple is HOt ‘ltred in the compensation network ACKNOWLEDGEMENTS, ‘The author wishes to acksowledge E. Aston Boyd for providing the ‘motivation of is ody. REFERENCES R.D. Middlebrook and S. Cuk. “A General Unified Approach to Modeling Switching Converter Power Stage.” IEEE Power Fleetronis Specials Conference, 1976. Mm 354na 13 14 ta, LV Voepérian, “Simplified Analysis of PWM Convener: Using the Model of the PWM Switch: Pans J and fl" #ECE Trane aeons on Aerospace and Electronie Systems, March 1990, Vol Bee? F.C. tze and J. Short. “An Improved Model for Preitng the Dynamic Performance of Wide Bandwidth Switching Cape wenern PowerCon TI, 1984 V, Delo. “Computer Program ads SPICE. 10 5 Isior Anaiysic Electronic Design, March T9R1 ig Regs. RB. Ridley, “A New, Continnows-Time Mode! for Curent Mode Contr,” Power Conversion and Intelligent Mion Con. ference ‘85, October, 1989. BH. Cho and F.C. Lee, “Mearurement of Loop Gain with the Big Modulator IEEE Power Becrons Speci Confer ene, June, 1984, 355