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Cmos CKT Design
Cmos CKT Design
6.1 Introduction
CMOS circuits are used in many applications from gate arrays to control logic.
They have the advantage over NMOS circuits in that they do not require active
pull-up loads. For a CMOS inverter stage only one of the transistors conduct at a
time. In the low output state the pull-down transistor conducts and the pull-up
transistor is off. When the output is high the pull-up transistor conducts and the
pull-down transistor is off. Pure CMOS circuits conduct very little current and,
at low digital frequencies, consume small amounts of power. Most of the power
dissipation is due to a changing logic state because both the pull-up and pulldown transistors are conducting. Thus, CMOS circuits dissipate an increasing
power for increasing digital signal frequency.
6.2 CMOS processing
The three main types of CMOS processes are:
n-well CMOS which uses a p-type substrate. As with NMOS technology, the
NMOS transistors are formed by diffusing n-type material into the substrate.
For the PMOS transistors, a well of n-type is diffused in the substrate and the
p-type diffusion then defines the drain and source of the PMOS transistors.
This type is compatible with NMOS technology as it uses a p-type substrate.
p-well CMOS which uses an n-type substrate. PMOS transistors are formed
by diffusing p-type material into the substrate. For NMOS transistors a well
of n-type is diffusion followed by a p-type diffusion within the well. This
technology is not as popular as n-well CMOS as it incompatible with NMOS
fabrication.
Twin tub CMOS which uses both n-type and p-type wells in a lightly doped
substrate.
Figure 6.1 shows an n-well CMOS inverter layout. The substrate is p-type and
the diffusion for the pull-down transistor is n-type (NMOS). To create a PMOS
transistor a tub of n-type is diffused into the substrate. Next, p-type diffusion is
inserted to create the drain and source of the transistor. The source of the pull-up
transistor is joined to the drain of the pull-down by metal (as diffusion or
polysilicon creates another transistor).
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VDD
p-diffusion
n-diffusion
Polysilicon
Metal
GND
Substrate
Silicon dioxide
A
GND
VDD
n-type well
p-type substrate
Figure 6.1
PMOS
n-diffusion (GREEN)
Polysilicon (RED)
A
NMOS
Figure 6.2
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CMOS inverter.
Metal 1 (BLUE)
p-well
VSS
Figure 6.3
CMOS inverter.
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output). Again, metal connects to the output and polysilicon as the input. If output metal layer from one gate connects to the next gate then the layer must be
changed to polysilicon by inserting a contact between the metal and polysilicon
layers. Figure 6.5 shows a possible layout of the circuit.
VDD
B
Z
A
VSS
Figure 6.4
VSS
Figure 6.5
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Z
B
VSS
Figure 6.6
VDD
VSS
Figure 6.7
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Explain why the ratios of the pull-up and pull-down transistors with a
CMOS inverter do not effect the output voltage levels. Contrast this
with an NMOS inverter.
6.2
Explain what effect the L:W ratios of the CMOS inverter pull-up and
pull-down transistors will have on circuit speed.
6.3
Determine the approximate cell sizes (in nm) for the gates in
Figure 6.3, Figure 6.5 and Figure 6.7.
6.4
Redesign the cells in Figure 6.3, Figure 6.5 and Figure 6.7 so that
each of the cell size areas are minimized.
6.5
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inverter;
2-input NAND gate;
2-input NOR gate.