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1.2DesignFlow

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PortionsfromApplicationSpecificIntegratedCircuitsCopyright1997byAddison
WesleyLongman,Inc.

1.2DesignFlow
Figure1.10showsthesequenceofstepstodesignanASICwecallthisadesignflow
.Thestepsarelistedbelow(numberedtocorrespondtothelabelsinFigure1.10)with
abriefdescriptionofthefunctionofeachstep.

FIGURE1.10ASICdesignflow.
1. Designentry.EnterthedesignintoanASICdesignsystem,eitherusinga
hardwaredescriptionlanguage(HDL)orschematicentry.
2. Logicsynthesis.UseanHDL(VHDLorVerilog)andalogicsynthesistoolto
produceanetlistadescriptionofthelogiccellsandtheirconnections.
3. Systempartitioning.DividealargesystemintoASICsizedpieces.
4. Prelayoutsimulation.Checktoseeifthedesignfunctionscorrectly.
5. Floorplanning.Arrangetheblocksofthenetlistonthechip.
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1.2DesignFlow

6. Placement.Decidethelocationsofcellsinablock.
7. Routing.Maketheconnectionsbetweencellsandblocks.
8. Extraction.Determinetheresistanceandcapacitanceoftheinterconnect.
9. Postlayoutsimulation.Checktoseethedesignstillworkswiththeaddedloads
oftheinterconnect.
Steps14arepartoflogicaldesign,andsteps59arepartofphysicaldesign.
Thereissomeoverlap.Forexample,systempartitioningmightbeconsideredaseither
logicalorphysicaldesign.Toputitanotherway,whenweareperformingsystem
partitioningwehavetoconsiderbothlogicalandphysicalfactors.Chapters914of
thisbookislargelyaboutlogicaldesignandChapters1517largelyaboutphysical
design.
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