Introduction

to
Verilog - II
Digital Design

Behavioral Modeling Contd..

The procedural block defines
A region of code containing sequential statements.
Two types of procedural blocks in Verilog
The always block
A continuous loop that never terminates.
The initial block
Executed once at the beginning of simulation (used in
Test-benches).
Only reg type variables can be assigned within an
always block.

Blocking Vs. Nonblocking Assignment

Two types of assignments within always blocks, with subtly
different behaviors
Blocking assignment: Evaluation and assignment are immediate
always @ (a or b or c)
begin
x = a | b;

1. Evaluate a | b, assign result to x

y = x ^ b ^ c; 2. Evaluate x^b^c, assign result to y

z = y & ~c;
end

3. Evaluate y&(~c), assign result to z

 Nonblocking assignment: All assignments deferred until all

right-hand sides have been evaluated
always @ (a or b or c)
begin
x <= a | b;
y
z

1. Evaluate a | b but defer assignment of x

y <= x ^ b ^ c;2. Evaluate x^b^c but defer assignment of

z <= y & ~c;
end

3. Evaluate y&(~c) but defer assignment of

4. Assign x, y, and z with their new values

Example
// Assume a = 5 and b = 3 before the clock
always@(posedge clk)
begin
a = b;
b = a;
end

Example
// Assume a = 5 and b = 3 before the clock
always@(posedge clk)
begin
a <= b;
b <= a;
end

Flip Flops
D Flip Flop
JK Flip Flop
T Flip Flop

- Basic building block

- Implement using D Flip Flop
- Implement using JK Flip Flop

Flip Flop Conversion Equations

D = JQ + KQ
T=J=K

Counters
Binary Counter (4 bit)
Ring Counter (4 bit)

Designing FSM using Verilog

Finite State Machine (FSM)

Moore
State Machine

Mealy
State Machine

Moore State Machine

Inputs

Next State
Logic

State Register

Output
Logic

Outputs

Mealy State Machine

Inputs

Next State
Logic

Output
Logic
State Register

Outputs

 The logic in a state machine is described using a case

statement or the equivalent (e.g., if-else)
All possible combinations of current state and inputs are
enumerated, and the appropriate values are specified for
next state and the outputs.

FSM Example
Consider the case of a circuit to detect a pair of 1's or 0's
in the single bit input.
That is, input will be a series of one's and zero's.
If two one's or two zero's comes one after another, output
should go high. Otherwise output should be low.
Overlapping pair is not considered

Moore state transition diagram

Reset

S0/0

1
1

S1/0

S2/0

S3/1

1
Reset

00/0

01/0

10/0

11/1

Mealy state transition diagram

1/1

S0

1/0

0/0

S1

0/0

1/0

0/1
S2

1/1

00

1/0

0/0

01

0/0

1/0

0/1
10