Scribd Logo
Upload

Welcome to Scribd!

  • 167 views

    Simulation Lab 4

    Uploaded by

    nkchen
    The document contains truth tables describing the behavior of 1-bit and 4-bit registers, as well as buffers. The 1-bit register truth table shows the output Q is 0 when clear is 1, and keeps its previous value when enable is 1 and clock transitions. The 4-bit register truth table similarly shows the behavior of a 4-bit register under different input combinations. The buffer truth table shows the inputs A3-A0 are passed straight to the outputs Y3-Y0 when both enable lines are 1.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content

    You might also like

    Simulation Lab 4

    Uploaded by

    nkchen
    167 views2 pages
    The document contains truth tables describing the behavior of 1-bit and 4-bit registers, as well as buffers. The 1-bit register truth table shows the output Q is 0 when clear is 1, and keeps its previous value when enable is 1 and clock transitions. The 4-bit register truth table similarly shows the behavior of a 4-bit register under different input combinations. The buffer truth table shows the inputs A3-A0 are passed straight to the outputs Y3-Y0 when both enable lines are 1.

    Original Description:

    For you, my indian

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    DOC, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document contains truth tables describing the behavior of 1-bit and 4-bit registers, as well as buffers. The 1-bit register truth table shows the output Q is 0 when clear is 1, and keeps its previous value when enable is 1 and clock transitions. The 4-bit register truth table similarly shows the behavior of a 4-bit register under different input combinations. The buffer truth table shows the inputs A3-A0 are passed straight to the outputs Y3-Y0 when both enable lines are 1.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    167 views2 pages

    Simulation Lab 4

    Uploaded by

    nkchen
    The document contains truth tables describing the behavior of 1-bit and 4-bit registers, as well as buffers. The 1-bit register truth table shows the output Q is 0 when clear is 1, and keeps its previous value when enable is 1 and clock transitions. The 4-bit register truth table similarly shows the behavior of a 4-bit register under different input combinations. The buffer truth table shows the inputs A3-A0 are passed straight to the outputs Y3-Y0 when both enable lines are 1.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    of 2

    1 bit register truth table

    Clear Enable Clock Data Q


    1 X X X 0
    0 0 X X Q
    0 1 Down 1 1
    0 1 Down 0 0

    4 bit register truth table


    A3 A2 A1 A0 Enable Clock Clear Y3 Y2 Y1 Y0
    0 0 0 0 1 DOWN 0 0 0 0 0
    0 0 0 1 1 DOWN 0 0 0 0 1
    0 0 1 0 1 DOWN 0 0 0 1 0
    0 0 1 1 1 DOWN 0 0 0 1 1
    0 1 0 0 1 DOWN 0 0 1 0 0
    0 1 0 1 1 DOWN 0 0 1 0 1
    0 1 1 0 1 DOWN 0 0 1 1 0
    0 1 1 1 1 DOWN 0 0 1 1 1
    1 0 0 0 1 DOWN 0 1 0 0 0
    1 0 0 1 1 DOWN 0 1 0 0 1
    1 0 1 0 1 DOWN 0 1 0 1 0
    1 0 1 1 1 DOWN 0 1 0 1 1
    1 1 0 0 1 DOWN 0 1 1 0 0
    1 1 0 1 1 DOWN 0 1 1 0 1
    1 1 1 0 1 DOWN 0 1 1 1 0
    1 1 1 1 1 DOWN 0 1 1 1 1
    X X X X X X 1 0 0 0 0
    X X X X 0 X 0 Q Q Q Q

    Buffer Truth Table


    EN1 EN2 A3 A2 A1 A0 Y3 Y2 Y1 Y0
    0 0 1 1 1 1 x x x x
    0 1 1 1 1 1 x x x x
    1 0 1 1 1 1 x x x x
    1 1 1 1 1 1 1 1 1 1

    Task 4-5
    Microprocessor gate delay = 18 gates
    Propagation delay =72 nanoseconds
    72 * (10^-9) = 72 nanoseconds
    Frequency = 1.38888888 megahertz

    Task 4-6
    Hex
    Input Enable Y0 Y1 Y2 Y3
    0 1 1 0 0 0
    1 1 0 1 0 0
    2 1 0 0 1 0
    3 1 0 0 0 1
    Task 4-7
    EN1 EN2 A3 A2 A1 A0 Y3 Y2 Y1 Y0
    0 0 1 0 1 0 x x x x
    0 1 1 0 1 0 x x x x
    1 0 1 0 1 0 x x x x
    1 1 1 0 1 0 1 0 1 0

    Task 4-8
    MS
    A3 A2 A1 A0 Line Write Line Clock Clear Y3 Y2 Y1
    0 0 0 0 1 1 DOWN 0 0 0 0
    0 0 0 1 1 1 DOWN 0 0 0 0
    0 0 1 0 1 1 DOWN 0 0 0 1
    0 0 1 1 1 1 DOWN 0 0 0 1
    0 1 0 0 1 1 DOWN 0 0 1 0
    0 1 0 1 1 1 DOWN 0 0 1 0
    0 1 1 0 1 1 DOWN 0 0 1 1
    0 1 1 1 1 1 DOWN 0 0 1 1
    1 0 0 0 1 1 DOWN 0 1 0 0
    1 0 0 1 1 1 DOWN 0 1 0 0
    1 0 1 0 1 1 DOWN 0 1 0 1
    1 0 1 1 1 1 DOWN 0 1 0 1
    1 1 0 0 1 1 DOWN 0 1 1 0
    1 1 0 1 1 1 DOWN 0 1 1 0
    1 1 1 0 1 1 DOWN 0 1 1 1
    1 1 1 1 1 1 DOWN 0 1 1 1
    X X X X X X X 1 0 0 0
    X X X X 0 0 X 0 Q Q Q
    X X X X 0 1 X 0 Q Q Q
    X X X X 1 0 X 0 Q Q Q

    You might also like