Project Part 6: Five Stage Pipelined RISC Processor

Washington University in St. Louis

Graduate Computer Architecture (CSE/ESE 560M)
Assignment Date: September 22, 2005
Instructor: Young H. Cho

Fall 2005

Five Stage Pipelined RISC Processor Design

This would be what is required for a prerequisite undergraduate Computer Architecture course. Beyond
this point will be cover more advanced materials such as Super-scalar, Vector Computer, VLIW, various
forms of hardware optimization techniques. The end result of this part should look somewhat like the MIPS
DLX pipelined processor. Following figure is a copy of the pipelined datapath.

Each group should apply minimal instructions to run simple programs such as bubble sort and Fibonacci
programs. Depending on your architecture, ISA maybe more efficient to layout certain way, but in some
cases, you may have constraints set by legacy architecture because of the backwards compatibility issues.
Intel was in danger of being trapped in cranking out inefficient designs due to backwards compatibility
issues, but they survived by further breaking down their instruction sets into microcode, thus using more
RISC like instructions internally.
Since you are in control of your own design, you are not constrained to anything (or at least not too
many.) So make your design as ambitious as you can and want. You can even have vector instructions.
This is a computer architecture course, NOT A REAL LIFE situations where you are usually motivated by
cost and performance, so be creative up to a point where you can complete your design by end of the due
dates.

II Simulation and Test

First, make sure individual components simulate correctly. Write a few toy program in your assembly
code and dump the result into the memory to execute it. Use some test vectors to test all of your subcomponents. Do the following for testing your processor
Generate a testbench program to test the whole design.
Try writing a small sorting program if you have time (itll be assigned in next lab or so anyways.)
III Write-up
- Write 4-page description and summary of your design The write-up should be extension of write-ups
from previous labs. Indicate the unique features (if any) of your design from others (i.e. optimizations,
additional functionalities, and etc.)
- Attach Schematic and Waveform printouts.
- Attach logbook written individually indicating what each one did at what times.
- Make logs of your part in the lab with Date/Time stamps
- Make short but descriptive log at the end of each work session