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Dynamic-Threshold Logic For Low-Power VLSI Design
Dynamic-Threshold Logic For Low-Power VLSI Design
Dynamic-Threshold Logic For Low-Power VLSI Design
Alan J. Drake
University of Michigan
ajdrake@umich.edu
Richard B. Brown
University of Michigan
brown@umich.edu
IBM Technical Contact
Jeffrey L. Burns
Austin Research Lab
jlburns@us.ibm.com
Abstract
Power dissipation is a serious concern for circuit designers. Partially-depleted SOI provides a Dynamic Threshold
MOS transistor that may be useful in reducing static power
and dynamic power. DTMOS can be used to choke off
leakage current and improve performance of transistors
under lower voltage conditions, but suffers from high bodycontact resistance, Miller capacitance, area penalties, and
limited operating voltage. Driving the body with a separate conditioning signal and careful design are proposed
as ways to offset the above problems and still take advantage of DTMOS. A ring oscillator has been implemented to
verify the use of this technology in various configurations.
This information will be helpful in the design of circuits
for datapath elements.
1. Introduction
Power dissipation is a problem of increasing concern to
designers of VLSI circuits. Figure 1 shows the estimated
power dissipation trend of high-performance microprocessors through 2005 taken from the SIA roadmap [1]. Low200
Total Power
Static Limit
Static Power
150
)sttaW( rewoP
100
2. SOI technology
50
0
1999
2001
2002
2003
2004
Year
2005
Gate[G]
N+
N+
tSi
[B]
O x id e
Oxide
[D]
tOX
[S]
(a)
G
nFET
I npn
Cgb
Csb
Csx
Isb
Ibd
Cdb
Cdx
B
Cbx
(b)
Figure 2: (a) Schematic cross section of a PDSOI NFET. (b) Equivalent circuit model. (Inpn is
the parasitic lateral npn current, the diodes are
the base-emitter and base-collector junction
diodes, Isb and Ibd are impact ionization currents.) [3]
3. DTMOS
An added degree of freedom in PD-SOI arises from the
floating back-gate which can be controlled as an additional
port. If the gate of the transistor is connected to the body,
see Figure 3, a dynamic-threshold transistor (DTMOS)
also called Body Controlled MOS and Variable Threshold
MOSis created [10]. Notice that as the voltage on the
gate rises, the body voltage is forward-biased with respect
(a)
(b)
ref
(c)
(d)
(e)
ref
ref
Logic
Circuits
ref
Boosted Gnd
Vreff
(f)
(g)
(h)
(i)
(j)
[14]
sistors and thus load capacitance. Since operating voltages
are expected to drop to 0.8 V for low power and 1.1V for
performance chips by 2005, which is only 100 to 400 mV
higher than the 0.7 V for DTMOS, this added complexity
may be unwarranted. The threshold-lowering of DTMOS
at 0.7 V could make it a higher performer than floatingbody circuits at 0.8 V and higher. If the Miller capacitance
is too high, a separate signal, such as a pre-charge, can condition the body voltage without the added transistors
shown in Figure 4. This technique, of driving the body
with a conditioning voltage separate from the gate, will be
referred to as decoupled DTMOS.
The potential of DTMOS was demonstrated in a 32-bit
ALU designed using pass-gate logic [14]. At 0.5V operating voltage, the off-state VT was 0.15V and the on-state VT
was -0.05V while the ALU operated at 260 MHz and dissipated 2.5 mW. The power dissipation, was 1/50 and the
power-delay-product was 1/20 that of a bulk pass-gate
design with similar design rules.
Vout
Vin
Vout
Vin
Vout
Vfb
Strong N
Strong P
Vout
(b) Positive body conditioning
Vin
Vfb
Strong P
Strong N
Vout
(c) Negative body conditioning
Figure 5: Ring-oscillator inverters and timing diagrams for body contacts
n-transistor as it pulls down the output as in Figure 5(b).
This may be referred to as positive body condition since
the body voltage positively affects the drive strength of the
transistor. Figur e5(c) shows the opposite case, or negative
body condition, where the n-transistor body is low, causing
a weak transistor trying to pull down the output against a
strong p-transistor. By varying the shape and position of
the body bias, favorable conditions can be obtained to
maximize gain and minimize leakage currents in the transistors. The ideal case would be a positive body condition
only while the transistor is driving the output and a negative body condition at all other times to minimize leakage.
This technique is particularly applicable to synchronous
circuits where clock shaping and conditioning already
takes place and phased signals are readily available. A
separate clock phase, or a phase already generated, can be
routed to the circuits in the datapath to provide biasing in a
manner that enhances the drive of transistors in the circuit
while reducing leakage currents. The challenge will be in
shaping that signal and aligning it for maximum benefit.
s1
s2
s4 0
s4 1
Vb
Vb
Vb
Vb
s1
s2
s40
s41
Vb
Vb
Vb
Vb
6. Conclusion
SOI has become a mainstream technology used for
some modern high-performance microprocessors. It is
seen to be beneficial for performance and power dissipation. The controllability of the body of the transistors
allows for DTMOS circuits to be implemented. DTMOS
provides both low leakage and high current drive but must
be carefully used to offset decreased area and lower supply
voltages. In spite of its limitations, DTMOS shows promise for power-conscious designs. When off, a DTMOS
transistor chokes off leakage current and when on it
enhances its current drive to offset its low operating voltage. A ring-oscillator macro was developed to test the performance of DTMOS in a 0.13 m, 8 metal, 1.1V, copper
SOI process. Data from this macro will be used in developing low-power circuit styles to use for datapath elements. These circuits will be tested in a multiplyaccumulate unit which will be built in the next phase of
this research.
7. References
[1] Semiconductor Industry Association, The International Technology Roadmap for Semiconductors: 2000 Update.
[2] Rabaey, J. M., Digital Integrated Circuits: A Design Perspective, 1st ed Upper Saddle River, New Jersey: Prentice Hall, 1996.
[3] Chuang, C. T., Lu, P. F., Anderson, C. J., SOI for Digital
CMOS VLSI: Design Considerations and Advances, Proceedings of the IEEE, vol. 86, no. 4, pp. 689-720, Apr. 1998.