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Notes 18 - Multistage Transformers
Notes 18 - Multistage Transformers
Microwave Engineering
Fall
2011
Notes
18
Multistage
Transformers
Single-stage
Transformer
The transformer length is arbitrary in this analysis.
Step
Z1 line
Load
Z in - Z 0
Z in Z 0
Z L - Z1
Z L Z1
0
S110 - S 22
S210 S120
Z1 - Z 0
Z1 Z 0
2 Z 0 Z1
Z0
0
1
11 Z Z
Z1
1
0
2
Single-stage Transformer
From the self-loop formula, we have
(as derived in previous notes)
(cont.)
- j 21
0
0
S
S
e
S110 21 012 L - j 21
1 - S22 L e
2 Z 0 Z1
4 Z 0 Z1
0 0
S21
S12
2
Z1 Z 0
Z1 Z 0
2
2
2
Z1 Z 0
Z1 - Z 0
Z12 Z 02 2 Z 0 Z1 Z1 Z 0 Z1 Z 0 2 Z 0 Z1
1
1
1
2
2
2
Z
Z
Z1 Z 0
Z1 Z 0
Z1 Z 0
0
1
2
2
1
Z 02 2 Z 0 Z1 Z12 Z 02 2 Z 0 Z1
2
Z1 Z 0
4 Z 0 Z1
Z1 Z 0
Hence
2
0
S S 1- S11
0
21
0
12
Single-stage Transformer
We then have
(cont.)
S110
1 S
02
11
e- j 21
0
1 - S22
L e- j 21
or
S110 L e- j 21
1 S110 L e- j 21
4
Single-stage Transformer
S (cont.)
e
0
11
1 S110 L e- j 21
S110 L 1
S110 L e - j 21
- j 21
Denote 0 S110 , 1 L
0 1 e- j 21
Z1 - Z 0
Z -Z
; 1 L 1
Z1 Z 0
Z L Z1
5
Multistage Transformer
Assuming small
reflections:
Hence
Multistage Transformer
(cont.)
0 1 e- j 2 2 e- j 4 3e- j 6 ..... N e - j 2 N
Z n 1 - Z n
n
Z n 1 Z n
Note that this is a polynomial in powers of z = exp(-j2).
Multistage Transformer
(cont.)
0 1 e- j 2 2 e- j 4 3e- j 6 ..... N e- j 2 N
If we assume symmetric reflections of the sections (not a
symmetric layout of line impedances), we have
0 N , 1 N -1 , 2 N -2 , . . .
e- jN 0 e jN e- jN 1 e j ( N -2) e- j ( N -2) . . .
- j
Last term
Multistage Transformer
(cont.)
Hence, for symmetric reflections we then have
1
- jN
2
e
cos
N
cos
N
2
...
cos
N
2
n
...
N ; N even
1
n
0
2 2
n
N -1
0
Multistage Transformer
(cont.)
Design philosophy:
If we choose a response for ( ) that is in the form of a
polynomial (in powers of z = exp (-j2 )) or a Fourier cosine
series, we can obtain the needed values of n and hence
complete the design.
10
Ae- jN e j e - j A e - jN 2 N cos N
N
A 2 N cos
f f 0 i l
0
2
dn
Also,
0 for n 1, 2, ..., N -1
d n
2
1 z
CnN z n
where CnN
n 0
N!
N - n ! n!
A 1 e
- j 2
A CnN e- j 2 n
n 0
- j 2
A CnN e - j 2 n
n 0
Set equal
Z L - Z0
A 2N
Z L Z0
Hence
Z L - Z 0
A2
Note: A could be positive or negative
Z L Z 0
-N
Equating responses for each term in the polynomial series gives us:
n ACnN , n 1, 2,......., N
Hence
Z -Z
Z n 1 - Z n
2- N L 0 CnN
Z n 1 Z n
Z L Z 0
Z 0 Z 0 , Z N 1 Z L
This gives us a
solution for the
line
impedances.
13
N!
N - n ! n!
Note that
CNN n
N!
N!
CnN
N - ( N n) ! ( N n)! n ! ( N n)!
Hence
n N n
14
Note: The table only shows data for ZL > Z0 since the design can be reversed
(Ioad and source switched) for ZL < Z0 .
15
g 1 / 4
50 line
Z1
g 2 / 4
Z2
g 3 / 4
Z3
100 line
ZL
Z0
16
X 1
Recall
Z n 1 - Z n
- N Z L - Z 0
N
2
C
n
Z n 1 Z n
Z
Z
0
L
1 ln Z n1 2- N CnN 1 ln Z L
2
Zn
Z 0
Hence
ve
recursi
sh i p
n
o
i
t
a
l
e
r
Z L
ln Z n 1 2 C ln ln Z n
Z 0
-N
N
n
18
1
N
1 m
m cos
2 A
-1
f / 2
f / 2
f
2
f0
f0 - f m
f0
4
4
1
2 - 2 m 2 - 2 m 2 - m 2 - cos -1 m
f0
/2
2 A
Hence
f
4
1
2 - cos-1 m
2 A
f0
1
N
1
N
19
f 0 2
A 1 e
- j 2
CnN
Z L - Z 0
A2
Z
0
L
-N
A coefficient
Z L
ln Z n
Z 0
ln Z n 1 2- N CnN ln
N!
N - n ! n!
f
4
1
2 - cos-1 m
2 A
f0
1
N
Bandwidth
20
Example
Example: three-stage binomial
transformer
Given:
Z L 50 []
Z 0 100 []
m 0.05
N 3
50 -100
-0.0417
50 100
dB
m -26.0 [dB]
A 2-3
f
4
0.05
-1 1
BW
2 - cos
2 0.0417
f0
0.713
1
3
BW 71.3%
21
Example (cont.)
Z L
ln Z n 1 ln Z n 2 C ln
Z 0
-N
Z1 :
N
n
50
4.519
100
ln Z1 ln Z 0 2-3 C03 ln
Z1 91.7 []
Z2 :
CnN
N!
N - n ! n!
C30 = 1
C13 = 3
C32 = 3
50
4.259
100
ln Z 2 ln Z1 2-3 C13 ln
C33 = 1
Z 2 70.7 []
Z3 :
50
3.999
100
ln Z 3 ln Z 2 2-3 C23 ln
Z 3 54.5[]
22
Example (cont.)
Using the table in Pozar we have:
Z L / Z0 2 :
(The above normalized load impedance is the reciprocal of what we actually hav
Hence, switching the load and the source ends, we have
Z 0 50[]
Therefore
Z1 91.685 []
Z 2 70.711 []
Z 3 54.585 []
23
Example (cont.)
S11 dB 20 log10 f
-26
3.29 GHz
f 0 5.0 GHz
6.74 GHz
BW 69.0%
24
cos n cos 1 x , x 1
Tn x
1
cosh
n
cosh
x , x 1
T1 x x
T2 x 2 x 2 1
T3 x 4 x3 - 3x
M
For -1 x 1: Tn x 1
For x 1: Tn x 1
Tn x 2 xTn-1 x - Tn-2 x
We choose the response to be in the form of a Chebyshev polynomial.
25
m A
T1 x x
T2 x 2 x 2 1
T3 x 4 x 3 - 3 x
M
Tn x 2 xTn -1 x - Tn -2 x
28
the above formula we can extract the coefficients n (no general formula is given
As f 0 l 0
0 ATN sec m
Z L - Z0
Z L Z0
Z L - Z 0
1
Z
TN sec m
0
L
29
m m A TN sec m cos m A TN 1 A
A m
At 0 :
0 ATN sec m
TN sec m 0
Z L - Z0
Z L Z0
sec m 1
Hence
A sgn Z L - Z 0 m
30
Note: The table only shows data for ZL > Z0 since the design can be reversed
31
(Ioad and source switched) for ZL < Z0 .
4
f
2- m
f0
At f 0 : ATN sec m
Z L - Z0
1 Z -Z
1 Z L - Z0
TN sec m L 0
Z L Z0
A Z L Z 0
m Z L Z0
cosh N cosh -1 sec m
1
1 Z L - Z0
-1
sec m cosh
cosh
m Z L Z0
N
Hence
X -1 1
ln X ;
X 1 2
X 1
1
1
Z L
-1
sec m cosh
cosh
ln
N
2
m
Z 0
32
f 0 2
N
2
m
Z 0
m term
A sgn Z L - Z 0 m A coefficient
No formula given for the line impedances. Use
the Table from Pozar or generate (by hand) the Design of line impedances
solution by expanding ( ) into a polynomial
with terms cos (n ).
f
4
2 - m
f0
Bandwidth
33
Example
Example: three-stage Chebyshev
transformer
Given
Z L 100[]
Z 0 50[]
m 0.05
Assumed symmetry : 3 = 0 , 2 = 1
A sgn Z L - Z 0 m A 0.05
N 3 A e- j 3 T3 sec m cos
Ae- j 3 sec3 m cos 3 3cos - 3sec m cos
2 e- j 3 0 cos 3 1 cos
(finite Fourier cosine series form)
Equate
34
1
100
cosh -1
ln
3
2
0.05
50
1.408
1
3
0.05 1.408
2
f
4
2 - m
f0
0 3 0.0698
1
3
3 0.05 1.408 - 3 0.05 1.408
2
1 2 0.1037
35
Z n 1 - Z n
n
Z n 1 Z n
Z n 1 Z n
1 n
1- n
1 0.0698 57.5
1- 0.0698
1 0.1037 70.8
Z 2 57.5
1- 0.1037
1 0.1037 87.2
Z 3 70.8
10.1037
Z1 50
Z1 57.5
Z 2 70.8
Z 3 87.2
Checking consistency :
Z 4 Z L 87.2
1 0.0698
1- 0.0698
100.3
36
Z n 1 - Z n 1 Z n 1
n
ln
ln Z n 1 ln Z n 2 n
Z n 1 Z n 2 Z n
ln Z1 ln Z 0 2 0
ln 50 2 0.0698
4.051
ln Z 2 ln Z1 21
4.259
ln Z 3 ln Z 2 2 2
4.466
Z1 57.49
Z 2 70.74
Z 3 87.05
37
Z 2 1.4142 50 70.7
Z 3 1.7429 50 87.1
38
S11 dB 20 log10 f
-26
2.51 GHz
7.5 GHz
f 0 5.0 GHz
BW 99.8%
39
40
Tapered Transformer
The Pozar book also talks about using continuously tapered lines to
match between an input line Z0 and an output load ZL. (pp. 255-261).
Please read this.
41