Set_attribute library library_list

Read_hdl hdl_file_list
Elaborate
<SDC Rading and optimization>
####Setting up for DFT rule violation checking #####
Set_attribute dft_scan_style {muxed_scan}
Define_dft shift_enable -name SE -active high -no_ideal -hookup_pin <top level pin
name>
Define_dft test_mode -name TM -active high -no_ideal -hookup_pin <top level pin
name>
define_dft test_clock -name test_clock -domain test_clock_domain pin_name
####Running DFT run violation checking ####
Check_dft_rules design -advanced
report dft_violations -async -clock -shiftreg -tristate -race design
####Fixing DFT violations ####
Fix_dft_violations -violations violation_object_id_list
####Improving testability of design ###
Insert_dft -test_point <pin/port name> -test_control <test_signal> -type
<control_0/control_1>
#### Synthesize design and map to scan ####
Synthesize -to_mapped
#### DFT configurations and preview chains####
Define_dft scan_chain -name name -sdi sdi -sdo sdo -create_ports -shift_enable <name>
-shared_out
### Running scan configuration ####

Connect_scan_chains design -preview -auto_create_chains

Report_dft_chains
### Export to ATPG and placement tool ###
Write_scandef
Write_dft_abstarct_model
Write_hdl -abstarct
Write_atpg -stil
Write_et_atpg design