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  • Simple - Combinational - Mult: Reg Integer

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    Upendar Sapati Sapati Upendarsapati
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    This document contains the code for 3 Verilog modules that perform multiplication: 1. A simple combinational multiplier that multiplies two 16-bit numbers without registers or clocks. 2. A simple multiplier module that registers the inputs, uses a counter to perform the multiplication sequentially over clock cycles, and indicates when the result is ready. 3. A streamlined signed multiplier module that handles signed numbers, registers the inputs, performs the multiplication with shifting and addition over clock cycles, and handles the sign of the output.

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    This document contains the code for 3 Verilog modules that perform multiplication: 1. A simple combinational multiplier that multiplies two 16-bit numbers without registers or clocks. 2. A simple multiplier module that registers the inputs, uses a counter to perform the multiplication sequentially over clock cycles, and indicates when the result is ready. 3. A streamlined signed multiplier module that handles signed numbers, registers the inputs, performs the multiplication with shifting and addition over clock cycles, and handles the sign of the output.

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    3 views2 pages

    Simple - Combinational - Mult: Reg Integer

    Uploaded by

    Upendar Sapati Sapati Upendarsapati
    This document contains the code for 3 Verilog modules that perform multiplication: 1. A simple combinational multiplier that multiplies two 16-bit numbers without registers or clocks. 2. A simple multiplier module that registers the inputs, uses a counter to perform the multiplication sequentially over clock cycles, and indicates when the result is ready. 3. A streamlined signed multiplier module that handles signed numbers, registers the inputs, performs the multiplication with shifting and addition over clock cycles, and handles the sign of the output.

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    © All Rights Reserved
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    of 2

    module simple_combinational_mult(product,multiplier,multiplicand); //P

    input [15:0] multiplier, multiplicand;


    output
    product;
    reg [31:0]
    integer

    product;
    i;

    always @( multiplier or multiplicand )


    begin
    product = 0;

    for(i=0; i<16; i=i+1)


    if( multiplier[i] == 1'b1 ) product = product + ( multiplicand << i
    );

    end
    endmodule
    module simple_mult(product,ready,multiplier,multiplicand,start,clk); //P
    input [15:0] multiplier, multiplicand;
    input
    start, clk;
    output
    product;
    output
    ready;
    reg [31:0]

    product;

    reg [15:0]
    reg [31:0]

    multiplier_copy;
    multiplicand_copy;

    reg [4:0]
    wire

    bit;
    ready = !bit;

    initial bit = 0;
    always @( posedge clk )
    if( ready && start ) begin
    bit
    product
    multiplicand_copy
    multiplier_copy

    =
    =
    =
    =

    16;
    0;
    { 16'd0, multiplicand };
    multiplier;

    end else if( bit ) begin


    if( multiplier_copy[0] ==
    multiplicand_copy;

    1'b1 ) product = product +

    multiplier_copy = multiplier_copy >> 1;


    multiplicand_copy = multiplicand_copy << 1;
    bit = bit - 1;

    end
    endmodule
    module streamlined_signed_mult(product,ready,multiplier,multiplicand,
    start,clk);

    input [15:0]
    input
    output
    output

    multiplier, multiplicand;
    start, clk;
    product;
    ready;

    reg [31:0]
    reg [15:0]

    product;
    abs_multiplicand;

    reg [4:0]
    wire

    bit;
    ready = !bit;

    initial bit = 0;
    always @( posedge clk )
    if( ready && start ) begin
    bit
    = 16;
    product = { 16'd0, multiplier[15] ? -multiplier : multiplier };
    abs_multiplicand = multiplicand[15] ? -multiplicand : multiplicand;

    end else if( bit ) begin:A


    reg lsb;
    lsb
    = product[0];
    product = product >> 1;
    bit
    = bit - 1;

    if( lsb ) product[31:15] = product[30:15] + abs_multiplicand;


    if( !bit && multiplicand[15] ^ multiplier[15] ) product = -product;
    end
    endmodule

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