EEE 425/591

Digital Systems and Circuits Spring 2015

Homework #1
February 11th
Problem 1 (20 pts). A semiconductor company has the following costs associated with Product X:
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Fixed cost of $1B ($1,000,000,000)

Die yield of 60%
Die cost of $6
Testing and packaging cost of $3 per die
A final test yield of 90%
Product volume of 1B (1,000,000,000) chips

a) What is the cost per IC (considering both fixed and variable costs)?
b) Suppose that you are a strategic planner for this company and you need to reduce the cost to make
profit. Which one is a better strategy? The answers should be quantitatively justified to get credit!
Strategy 1: Reduce the fixed operating cost by 15%, i.e., by $150,000,000, with a potential reduction in
volume which is negligible.
Strategy 2: Spend an extra Research and Development cost of $300,000,000 to improve the die yield from
60% to 75%.
Problem 2 (20 pts). Draw the circuit diagram (transistor level) to implement the following boolean

functions using standard CMOS logic. (a) Exclusive NOR:

, (b) Exclusive OR:

Problem 3 (20 pts). Consider a 2-input NAND gate. Is the (i) fall time and (b) rise time the same for all
combinations of inputs? Justify your answer.
Problem 4 (20 pts). As you will find out later in the class, using basic gates with many inputs is not
necessarily a good idea. As such, no more than 3 inputs per gate are typically allowed in practice. Design
a 6-input OR gate using basic gates with 3 or less inputs each. Draw the transistor-level diagram of the
design.
Problem 5 (20 pts). Determine the truth table and logic function for the circuit given in Figure 1.

Bonus (10 pts.) Find a standard CMOS gate implementation (up 3 inputs per gate) of the same
function. Which one has more transistors? Which one do you think will be faster and why.

Figure 1: Logic circuit for problem 5