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CMOS Inverter: DC Analysis
CMOS Inverter: DC Analysis
VOH = VDD
VOL = 0 V
Logic Swing
VDSn=Vout, VSDp=VDD-Vout
+
VSGp
Transition Region (between VOH and VOL)
Vin low
Vin < Vtn
+
Mn in Cutoff, OFF
VGSn
Mp in Triode, Vout pulled to VDD
VGSn=Vin, VSGp=VDD-Vin
Vin high
Mn in Triode, Mp in Saturation
Mn in Triode, Mp in Cutoff
Noise Margin
Input Low Voltage, VIL
= VDD - VIH
= VIL
Switching Threshold
Switching threshold = point on VTC where Vout = Vin
also called midpoint voltage, VM
here, Vin = Vout = VM
Calculating VM
I Dn =
n
2
nCOX W
2
(VGSn Vtn ) 2 =
n
2
(VGSn Vtn ) 2 =
express in terms of VM
(VM Vtn ) 2 =
p
2
(VDD VM Vtp ) 2
solve for VM
VM =
1+
(VSGp Vtp ) 2 = I Dp
n
(V Vtn ) = VDD VM Vtp
p M
n
p
n
p
W
L
W
k 'n
n
L n
=
p
W
k'p
L p
If
W
n L p
, then n = 1
=
p W
p
L n
n
p
n
p
n
L n n
=
2or 3
=
p
p
W
pCoxp
L p
nCoxn
Example
Given
kn = 140uA/V2, Vtn = 0.7V, VDD = 3V
kp = 60uA/V2, Vtp = -0.7V
Find
a) tx size ratio so that VM= 1.5V
b) VM if tx are same size
Transient Parameters
Transient Response
Response to step change in input
delays in output due to parasitic R & C
Inverter RC Model
Resistances
Rn = 1/[n(VDD-Vtn)]
Rp = 1/[n(VDD-|Vtp|)]
+
Vout
CL -
CDp
Fall Time
Fall Time, tf
Vout (t ) = VDD e
n = RnCout
V
t = n ln DD
Vout
definition
tf is time to fall from
90% value [V1,tx] to 10% value
[V0,ty]
V
t = n ln DD ln DD
0.9VDD
0.1VDD
tf = 2.2 n
ECE 410, Prof. A. Mason
Rise Time
Rise Time, tr
t
Rp
initial condition, Vout(0) = 0V
solution
time constant
t
definition
tr = 2.2 p
Propagation Delay
Propagation Delay, tp
(tpf + tpr)
Fall propagation delay, tpf
tp =
n = RnCout
tf = 2.2 n, tr = 2.2 p,
Propagation Delay
Rn = 1/[n(VDD-Vtn)]
tp = 0.35(n + p)
delay n + p
n + p = Cout (Rn+Rp)
Beta Matched
Rn+Rp =
if n=p=,
2
= 2L
(VDD-Vt) Cox W (VDD-Vt)
Width Matched
Rn+Rp =
n p(VDD-Vt)
if Vt = Vtn = |Vtp|
= Cox (W/L)
Rp = 1/[p(VDD-|Vtp|)]
In General
Rn+Rp =
p = RpCout
if Wn=Wp=W,
and L=Ln=Lp
L (n+ p)
(n p) Cox W (VDD-Vt)
W increases Cout
estimate
Cout
~2L
W
L
Delay Cout(Rn+Rp) L W
W VDD
= L2
VDD
PDC
P = IDD VDD
= Cox (W/L)
Series Transistors
increases effective L
effective
Parallel Transistors
increases effective W
effective
2
ECE 410, Prof. A. Mason
NAND: DC Analysis
Multiple Inputs
Multiple Transitions
Multiple VTCs
VM = VA = VB = Vout
set IDn = IDp, solve for VM
VM =
1
VDD Vtp + Vtn
2
1+
1
2
n
p
n
p
1
1+
N
1
N
n
p
n
p
NOR: DC Analysis
Similar Analysis to NAND
Critical Transition
0,0 to 1,1
when all transistors change
1+ 2 n
p
for NOR2
n
p
n
p
n
p
for NOR-N
Rise Time, tr
tr = 2.2 p
p = Rp Cout
Fall Time, tf
Discharge Circuit
2 series nMOS, Rn 2Rn
must account for internal cap, Cx
tf = 2.2 n
n = Cout (2 Rn ) + Cx Rn
ECE 410, Prof. A. Mason
Cx = CSn + CDn
Lecture Notes 7.22
Fall Time, tf
tf = 2.2 n
n = Rn Cout
Rise Time, tr
Charge Circuit
2 series pMOS, Rp 2Rp
must account for internal cap, Cy
Cy = CSp + CDp
tr = 2.2 p
p = Cout (2 Rp ) + Cy Rp
ECE 410, Prof. A. Mason
NAND/NOR Performance
Inverter: symmetry (VM=VDD/2), n = p
(W/L)p = n/p (W/L)n
Match INV performance with NAND
pMOS, P = p, same as inverter
nMOS, N = 2n, to balance for 2 series nMOS
Match INV performance with NOR
pMOS, P = 2 p, to balance for 2 series pMOS
nMOS, N = n, same as inverter
NAND and NOR will still
be slower due to larger Cout
is adjusted by
changing transistor
size (width)
Tx Sizing Considerations
Performance Considerations
Speed based on n, p and parasitic caps
DC performance (VM, noise) based on n/p
Design for speed not necessarily provide good DC
performance
Generally set tx size to optimize speed and then test DC
characteristics to ensure adequate noise immunity
Review Inverter: Our performance reference point
for symmetry (VM=VDD/2), n = p
which requires (W/L)p = n/p (W/L)n
signal
faster
signal
power supply
pMOS
AB
0 0
0 0
0 0
Critical Path
CD
0 0
0 1
1 0
F
0
0
1
1 0 0 0 0
1 1 0 0 1
C
C D
B
1 1 1 1 1
longest delay through a circuit block
largest sum of delays, from input to output
intuitive analysis: signal that passes through most gates
Multi-Input Gates
same DC component as inverter, PDC = VDDIDDQ
for dynamic power, need to estimate activity of the
gate, how often will the output be switching
NOR NAND
Pdyn = aCoutV2DDf, a = activity coefficient
estimate activity from truth table
a = p0p1
p0 = prob. output is at 0
p1 = prob. of transition to 1
p0=0.75
p1=0.25
a=3/16
p0=0.25
p1=0.75
a=3/16
Pass Transistor
Single nMOS or pMOS tx
Often used in place of TGs
y
y
ID
=1
time x=0
y=1 0
ID
time
=1
x=1
y=0 1