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Pic 18f887
Pic 18f887
Data Sheet
28/40/44-Pin, Enhanced Flash-Based 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
DS41291E
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance,
UNI/O, WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS41291E-page ii
PIC16F882/883/884/886/887
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
nanoWatt Technology
High-Performance RISC CPU:
Peripheral Features:
Low-Power Features:
Standby Current:
- 50 nA @ 2.0V, typical
Operating Current:
- 11 A @ 32 kHz, 2.0V, typical
- 220 A @ 4 MHz, 2.0V, typical
Watchdog Timer Current:
- 1 A @ 2.0V, typical
DS41291E-page 1
PIC16F882/883/884/886/887
Device
Program
Memory
Data Memory
I/O
10-bit A/D
(ch)
ECCP/
CCP
EUSART
MSSP
Comparators
Timers
8/16-bit
128
24
11
1/1
2/1
256
24
11
1/1
2/1
256
256
35
14
1/1
2/1
8192
368
256
24
11
1/1
2/1
8192
368
256
35
14
1/1
2/1
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC16F882
2048
128
PIC16F883
4096
256
PIC16F884
4096
PIC16F886
PIC16F887
DS41291E-page 2
PIC16F882/883/884/886/887
Pin Diagrams PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
TABLE 1:
PIC16F882/883/886
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11/P1D
RB3/AN9/PGM/C12IN2RB2/AN8/P1B
RB1/AN10/P1C/C12IN3RB0/AN12/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
I/O
Pin
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt Pull-up
Basic
RA0
AN0/ULPWU
C12IN0-
RA1
AN1
C12IN1-
RA2
AN2
C2IN+
VREF-/CVREF
RA3
AN3
C1IN+
VREF+
RA4
C1OUT
T0CKI
RA5
AN4
C2OUT
SS
RA6
10
OSC2/CLKOUT
OSC1/CLKIN
RA7
RB0
21
AN12
IOC/INT
RB1
22
AN10
C12IN3-
P1C
IOC
RB2
23
AN8
P1B
IOC
RB3
24
AN9
C12IN2-
IOC
PGM
RB4
25
AN11
P1D
IOC
RB5
26
AN13
T1G
IOC
RB6
27
IOC
ICSPCLK
RB7
28
IOC
ICSPDAT
RC0
11
T1OSO/T1CKI
RC1
12
T1OSI
CCP2
RC2
13
CCP1/P1A
RC3
14
SCK/SCL
RC4
15
SDI/SDA
RC5
16
SDO
RC6
17
TX/CK
RC7
18
RX/DT
RE3
Y(1)
MCLR/VPP
20
VDD
VSS
19
VSS
Note 1:
DS41291E-page 3
PIC16F882/883/884/886/887
Pin Diagrams PIC16F882/883/886, 28-Pin QFN
8
9
10
11
12
13
14
1
21
2
20
3
19
4 PIC16F882/883/886 18
5
17
6
16
15
7
RB3/AN9/PGM/C12IN2RB2/AN8/P1B
RB1/AN10/P1C/C12IN3RB0/AN12/INT
VDD
VSS
RC7/RX/DT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
28
27
26
25
24
23
22
RA1/AN1/C12IN1RA0/AN0/ULPWU/C12IN0RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11/P1D
28-pin QFN
DS41291E-page 4
PIC16F882/883/884/886/887
TABLE 2:
I/O
Pin
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt Pull-up
Basic
RA0
27
AN0/ULPWU
C12IN0-
RA1
28
AN1
C12IN1-
RA2
AN2
C2IN+
VREF-/CVREF
RA3
AN3
C1IN+
VREF+
RA4
C1OUT
T0CKI
RA5
AN4
C2OUT
SS
RA6
OSC2/CLKOUT
RA7
OSC1/CLKIN
RB0
18
AN12
IOC/INT
RB1
19
AN10
C12IN3-
P1C
IOC
RB2
20
AN8
P1B
IOC
RB3
21
AN9
C12IN2-
IOC
PGM
RB4
22
AN11
P1D
IOC
RB5
23
AN13
T1G
IOC
RB6
24
IOC
ICSPCLK
RB7
25
IOC
ICSPDAT
RC0
T1OSO/T1CKI
RC1
T1OSI
CCP2
RC2
10
CCP1/P1A
RC3
11
SCK/SCL
RC4
12
SDI/SDA
RC5
13
SDO
RC6
14
TX/CK
RC7
15
RX/DT
RE3
26
Y(1)
MCLR/VPP
17
VDD
VSS
16
VSS
Note 1:
DS41291E-page 5
PIC16F882/883/884/886/887
Pin Diagrams PIC16F884/887, 40-Pin PDIP
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/AN5
RE1/AN6
RE2/AN7
VDD
VSS
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RD0
RD1
DS41291E-page 6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16F884/887
40-pin PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11
RB3/AN9/PGM/C12IN2RB2/AN8
RB1/AN10/C12IN3RB0/AN12/INT
VDD
VSS
RD7/P1D
RD6/P1C
RD5/P1B
RD4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
PIC16F882/883/884/886/887
TABLE 3:
I/O
Pin
Analog
Comparators
Timers
ECCP
EUSART
MSSP
RA0
AN0/ULPWU
C12IN0-
Interrupt Pull-up
Basic
RA1
AN1
C12IN1-
RA2
AN2
C2IN+
VREF-/CVREF
RA3
AN3
C1IN+
VREF+
RA4
C1OUT
T0CKI
RA5
AN4
C2OUT
SS
RA6
14
OSC2/CLKOUT
RA7
13
OSC1/CLKIN
RB0
33
AN12
IOC/INT
RB1
34
AN10
C12IN3-
IOC
RB2
35
AN8
IOC
RB3
36
AN9
C12IN2-
IOC
PGM
RB4
37
AN11
IOC
RB5
38
AN13
T1G
IOC
RB6
39
IOC
ICSPCLK
RB7
40
IOC
ICSPDAT
RC0
15
T1OSO/T1CKI
RC1
16
T1OSI
CCP2
RC2
17
CCP1/P1A
RC3
18
SCK/SCL
RC4
23
SDI/SDA
RC5
24
SDO
RC6
25
TX/CK
RC7
26
RX/DT
RD0
19
RD1
20
RD2
21
RD3
22
RD4
27
RD5
28
P1B
RD6
29
P1C
RD7
30
P1D
RE0
AN5
RE1
AN6
RE2
10
AN7
RE3
Y(1)
MCLR/VPP
11
VDD
32
VDD
12
VSS
31
VSS
Note 1:
DS41291E-page 7
PIC16F882/883/884/886/887
Pin Diagrams PIC16F884/887, 44-Pin QFN
PIC16F884/887
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RB3/AN9/PGM/C12IN2NC
RB4/AN11
RB5/AN13/T1G
RB6/ICSPCLK
RB7/ICSPDAT
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3//VREF+/C1IN+
RC7/RX/DT
RD4
RD5/P1B
RD6/P1C
RD7/P1D
VSS
VDD
VDD
RB0/AN12/INT
RB1/AN10/C12IN3RB2/AN8
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/P1A/CCP1
RC1/T1OSCI/CCP2
RC0/T1OSO/T1CKI
44-pin QFN
DS41291E-page 8
PIC16F882/883/884/886/887
TABLE 4:
I/O
Pin
Analog
Comparators
Timers
ECCP
EUSART
MSSP
RA0
19
AN0/ULPWU
C12IN0-
Interrupt Pull-up
Basic
RA1
20
AN1
C12IN1-
RA2
21
AN2
C2IN+
VREF-/CVREF
RA3
22
AN3
C1IN+
VREF+
RA4
23
C1OUT
T0CKI
RA5
24
AN4
C2OUT
SS
RA6
33
OSC2/CLKOUT
RA7
32
OSC1/CLKIN
RB0
AN12
IOC/INT
RB1
10
AN10
C12IN3-
IOC
RB2
11
AN8
IOC
RB3
12
AN9
C12IN2-
IOC
PGM
RB4
14
AN11
IOC
RB5
15
AN13
T1G
IOC
RB6
16
IOC
ICSPCLK
RB7
17
IOC
ICSPDAT
RC0
34
T1OSO/T1CKI
RC1
35
T1OSI
CCP2
RC2
36
CCP1/P1A
RC3
37
SCK/SCL
RC4
42
SDI/SDA
RC5
43
SDO
RC6
44
TX/CK
RC7
RX/DT
RD0
38
RD1
39
RD2
40
RD3
41
RD4
RD5
P1B
RD6
P1C
RD7
P1D
RE0
25
AN5
RE1
26
AN6
RE2
27
AN7
RE3
18
Y(1)
MCLR/VPP
VDD
VDD
28
VDD
VSS
30
VSS
31
VSS
13
NC (no connect)
29
NC (no connect)
Note 1:
DS41291E-page 9
PIC16F882/883/884/886/887
Pin Diagrams PIC16F884/887, 44-Pin TQFP
PIC16F884/887
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
NC
NC
RB4/AN11
RB5/AN13/T1G
RB6/ICSPCLK
RB7/ICSPDAT
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3//VREF+/C1IN+
RC7/RX/DT
RD4
RD5/P1B
RD6/P1C
RD7/P1D
VSS
VDD
RB0/AN12/INT
RB1/AN10/C12IN3RB2/AN8
RB3/AN9/PGM/C12IN2-
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/P1A/CCP1
RC1/T1OSCI/CCP2
NC
44-pin TQFP
DS41291E-page 10
PIC16F882/883/884/886/887
TABLE 5:
I/O
Pin
Analog
Comparators
Timers
ECCP
EUSART
MSSP
RA0
19
AN0/ULPWU
C12IN0-
Interrupt Pull-up
Basic
RA1
20
AN1
C12IN1-
RA2
21
AN2
C2IN+
VREF-/CVREF
RA3
22
AN3
C1IN+
VREF+
RA4
23
C1OUT
T0CKI
RA5
24
AN4
C2OUT
SS
RA6
31
OSC2/CLKOUT
RA7
30
OSC1/CLKIN
RB0
AN12
IOC/INT
RB1
AN10
C12IN3-
IOC
RB2
10
AN8
IOC
RB3
11
AN9
C12IN2-
IOC
PGM
RB4
14
AN11
IOC
RB5
15
AN13
T1G
IOC
RB6
16
IOC
ICSPCLK
RB7
17
IOC
ICSPDAT
RC0
32
T1OSO/T1CKI
RC1
35
T1OSI
CCP2
RC2
36
CCP1/P1A
RC3
37
SCK/SCL
RC4
42
SDI/SDA
RC5
43
SDO
RC6
44
TX/CK
RC7
RX/DT
RD0
38
RD1
39
RD2
40
RD3
41
RD4
RD5
P1B
RD6
P1C
RD7
P1D
RE0
25
AN5
RE1
26
AN6
RE2
27
AN7
RE3
18
Y(1)
MCLR/VPP
VDD
28
VDD
VSS
13
NC (no connect)
29
VSS
34
NC (no connect)
33
NC (no connect)
12
NC (no connect)
Note 1:
DS41291E-page 11
PIC16F882/883/884/886/887
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Memory Organization ................................................................................................................................................................. 21
3.0 I/O Ports ..................................................................................................................................................................................... 39
4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 61
5.0 Timer0 Module ........................................................................................................................................................................... 73
6.0 Timer1 Module with Gate Control............................................................................................................................................... 76
7.0 Timer2 Module ........................................................................................................................................................................... 81
8.0 Comparator Module.................................................................................................................................................................... 83
9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 99
10.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 111
11.0 Enhanced Capture/Compare/PWM Module ............................................................................................................................. 123
12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 151
13.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 179
14.0 Special Features of the CPU .................................................................................................................................................... 209
15.0 Instruction Set Summary .......................................................................................................................................................... 231
16.0 Development Support............................................................................................................................................................... 241
17.0 Electrical Specifications............................................................................................................................................................ 245
18.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 273
19.0 Packaging Information.............................................................................................................................................................. 301
Appendix A: Data Sheet Revision History.......................................................................................................................................... 313
Appendix B: Migrating from other PIC Devices ............................................................................................................................... 313
Index .................................................................................................................................................................................................. 315
The Microchip Web Site ..................................................................................................................................................................... 323
Customer Change Notification Service .............................................................................................................................................. 323
Customer Support .............................................................................................................................................................................. 323
Reader Response .............................................................................................................................................................................. 324
Product Identification System............................................................................................................................................................. 325
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
DS41291E-page 12
PIC16F882/883/884/886/887
1.0
DEVICE OVERVIEW
DS41291E-page 13
PIC16F882/883/884/886/887
FIGURE 1-1:
Flash
2K(2)/4K(1)/
8K X 14
Program
Memory
Program
Bus
PORTA
Data Bus
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RAM
128(2)/256(1)/
368 Bytes
File
Registers
8-Level Stack
(13-Bit)
14
RAM Addr
PORTB
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
9
Addr MUX
Instruction Reg
7
Direct Addr
Indirect
Addr
FSR Reg
PORTC
STATUS Reg
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
8
3
MUX
Power-up
Timer
Instruction
Decode and
Control
Oscillator
Start-up Timer
ALU
PORTE
Power-on
Reset
OSC1/CLKIN
Timing
Generation
Watchdog
Timer
W Reg
Brown-out
Reset
OSC2/CLKOUT
Internal
Oscillator
Block
MCLR
VDD
RE3
CCP2
CCP2
VSS
VREF+
VREF-
Note
1:
2:
DS41291E-page 14
Timer2
EUSART
Analog-To-Digital Converter
(ADC)
2 Analog Comparators
and Reference
PIC16F883 only.
PIC16F882 only.
SS
SCK/SCL
SDI/SDA
SDO
P1C
P1D
Master Synchronous
ECCP
C1IN+
C12IN0C12IN1C12IN2C12IN3C1OUT
C2IN+
C2OUT
Timer1
AN0
AN1
AN2
AN3
AN4
AN8
AN9
AN10
AN11
AN12
AN13
Timer0
T1CKI
P1B
T1G
T0CKI
RX/DT
T1OSO
TX/CK
Timer1
32 kHz
Oscillator
T1OSI
CCP1/P1A
In-Circuit
Debugger
(ICD)
VREF+
VREFCVREF
EEDATA
128(2)/
256 Bytes
Data
EEPROM
EEADDR
PIC16F882/883/884/886/887
PIC16F884/PIC16F887 BLOCK DIAGRAM
Configuration
13
Program Counter
Flash
4K(1)/8K X 14
Program
Memory
Program
Bus
Data Bus
RAM
256(1)/368 Bytes
File
Registers
8-Level Stack
(13-Bit)
14
RAM Addr
PORTA
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
PORTB
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
9
Addr MUX
Instruction Reg
7
Direct Addr
Indirect
Addr
FSR Reg
STATUS Reg
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
8
3
MUX
Power-up
Timer
Instruction
Decode and
Control
Oscillator
Start-up Timer
ALU
Power-on
Reset
OSC1/CLKIN
Timing
Generation
PORTD
Watchdog
Timer
W Reg
CCP2
Brown-out
Reset
OSC2/CLKOUT
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
Internal
Oscillator
Block
CCP2
MCLR
VDD
PORTE
VSS
RE0
RE1
RE2
RE3
Timer0
Timer1
VREF+
VREF-
Timer2
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
Analog-To-Digital Converter
(ADC)
Note
1:
EUSART
SCK/SCL
Master Synchronous
ECCP
2 Analog Comparators
and Reference
SDI/SDA
SDO
P1D
P1C
P1B
T1CKI
RX/DT
T1G
T0CKI
C1IN+
C12IN0C12IN1C12IN2C12IN3C1OUT
C2IN+
C2OUT
T1OSO
TX/CK
Timer1
32 kHz
Oscillator
T1OSI
CCP1/P1A
In-Circuit
Debugger
(ICD)
SS
FIGURE 1-2:
VREF+
VREFCVREF
EEDATA
256 Bytes
Data
EEPROM
EEADDR
PIC16F884 only.
DS41291E-page 15
PIC16F882/883/884/886/887
TABLE 1-1:
Name
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/AN12/INT
RB1/AN10/P1C/C12IN3-
RB2/AN8/P1B
Legend:
Function
Input
Type
RA0
TTL
Description
AN0
AN
ULPWU
AN
C12IN0-
AN
RA1
TTL
AN1
AN
C12IN1-
AN
RA2
TTL
AN2
AN
A/D Channel 2.
VREF-
AN
CVREF
AN
C2IN+
AN
RA3
TTL
AN3
AN
A/D Channel 3.
VREF+
AN
Programming voltage.
C1IN+
AN
RA4
TTL
T0CKI
ST
C1OUT
RA5
TTL
AN4
AN
A/D Channel 4.
SS
ST
C2OUT
RA6
TTL
OSC2
XTAL
CLKOUT
RA7
TTL
OSC1
XTAL
Crystal/Resonator.
CLKIN
ST
RB0
TTL
AN12
AN
INT
ST
External interrupt.
RB1
TTL
AN10
AN
P1C
C12IN3-
AN
RB2
TTL
AN8
AN
P1B
DS41291E-page 16
Output
Type
A/D Channel 8.
PIC16F882/883/884/886/887
TABLE 1-1:
Name
RB3/AN9/PGM/C12IN2-
RB4/AN11/P1D
RB5/AN13/T1G
RB6/ICSPCLK
RB7/ICSPDAT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RE3/MCLR/VPP
Function
Input
Type
RB3
TTL
Output
Type
Description
AN9
AN
PGM
ST
A/D Channel 9.
Low-voltage ICSP Programming enable pin.
C12IN2-
AN
RB4
TTL
AN11
AN
P1D
RB5
TTL
AN13
AN
T1G
ST
RB6
TTL
ICSPCLK
ST
RB7
TTL
ICSPDAT
ST
RC0
ST
T1OSO
T1CKI
ST
RC1
ST
T1OSI
ST
CCP2
ST
CMOS Capture/Compare/PWM2.
RC2
ST
P1A
CCP1
ST
CMOS Capture/Compare/PWM1.
RC3
ST
SCK
ST
SCL
ST
OD
I2C clock.
RC4
ST
SDI
ST
SDA
ST
OD
RC5
ST
SDO
RC6
ST
TX
CK
ST
RC7
ST
RX
ST
DT
ST
RE3
TTL
MCLR
ST
VPP
HV
VSS
VSS
Power
Ground reference.
VDD
VDD
Power
Positive supply.
Legend:
DS41291E-page 17
PIC16F882/883/884/886/887
TABLE 1-2:
Name
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/AN12/INT
RB1/AN10/C12IN3-
Function
Input
Type
RA0
TTL
AN0
AN
ULPWU
AN
AN
RA1
TTL
AN1
AN
C12IN1-
AN
RA2
TTL
AN2
AN
A/D Channel 2.
VREF-
AN
CVREF
AN
C2IN+
AN
RA3
TTL
AN3
AN
A/D Channel 3.
VREF+
AN
C1IN+
AN
RA4
TTL
T0CKI
ST
C1OUT
RA5
TTL
AN4
AN
A/D Channel 4.
SS
ST
C2OUT
RA6
TTL
OSC2
CLKOUT
Crystal/Resonator.
RA7
TTL
OSC1
XTAL
Crystal/Resonator.
CLKIN
ST
RB0
TTL
AN12
AN
INT
ST
External interrupt.
RB1
TTL
AN10
AN
C12IN3-
AN
RB2
TTL
AN8
AN
RB3/AN9/PGM/C12IN2-
RB3
TTL
A/D Channel 8.
AN9
AN
PGM
ST
C12IN2-
AN
DS41291E-page 18
Description
C12IN0-
RB2/AN8
Legend:
Output
Type
A/D Channel 9.
PIC16F882/883/884/886/887
TABLE 1-2:
Name
RB4/AN11
RB5/AN13/T1G
RB6/ICSPCLK
RB7/ICSPDAT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
Function
Input
Type
RB4
TTL
Output
Type
Description
AN11
AN
RB5
TTL
AN13
AN
T1G
ST
RB6
TTL
ICSPCLK
ST
RB7
TTL
ICSPDAT
ST
RC0
ST
T1OSO
T1CKI
ST
RC1
ST
T1OSI
XTAL
CCP2
ST
CMOS Capture/Compare/PWM2.
RC2
ST
P1A
ST
CCP1
CMOS Capture/Compare/PWM1.
RC3
ST
SCK
ST
SCL
ST
RC4
ST
SDI
ST
SDA
ST
OD
RC5
ST
OD
I2C clock.
SDO
RC6
ST
TX
CK
ST
RC7
ST
RX
ST
DT
ST
RD0
RD0
TTL
RD1
RD1
TTL
RD2
RD2
TTL
RD3
RD3
TTL
RD4
RD4
TTL
RD5/P1B
RD5
TTL
P1B
RD6
TTL
P1C
RC7/RX/DT
RD6/P1C
Legend:
DS41291E-page 19
PIC16F882/883/884/886/887
TABLE 1-2:
Input
Type
RD7/P1D
RD7
TTL
P1D
AN
RE0/AN5
RE0
TTL
AN5
AN
RE1/AN6
RE1
TTL
AN6
AN
RE2/AN7
RE2
TTL
Name
RE3/MCLR/VPP
Output
Type
Description
PWM output.
A/D Channel 5.
A/D Channel 6.
AN7
AN
A/D Channel 7.
RE3
TTL
MCLR
ST
VPP
HV
Programming voltage.
VSS
VSS
Power
Ground reference.
VDD
VDD
Power
Positive supply.
Legend:
DS41291E-page 20
PIC16F882/883/884/886/887
2.0
MEMORY ORGANIZATION
2.1
FIGURE 2-1:
FIGURE 2-2:
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Stack Level 8
PC<12:0>
13
13
Stack Level 1
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
Stack Level 1
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Page 1
0FFFh
Stack Level 2
FIGURE 2-3:
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-Chip
Program
Memory
Page 0
0004h
0005h
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
07FFh
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
On-Chip
Program
Memory
Page 1
Page 2
07FFh
0800h
0FFFh
1000h
17FFh
1800h
Page 3
1FFFh
DS41291E-page 21
PIC16F882/883/884/886/887
2.2
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
2.2.1
2.2.2
DS41291E-page 22
PIC16F882/883/884/886/887
FIGURE 2-4:
File
Address
File
Address
File
Address
Address
00h
80h
100h
180h
TMR0
01h
OPTION_REG
81h
TMR0
101h
OPTION_REG
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
WDTCON
105h
SRCON
185h
PORTB
06h
TRISB
86h
PORTB
106h
TRISB
186h
PORTC
07h
TRISC
87h
CM1CON0
107h
BAUDCTL
187h
188h
88h
CM2CON0
108h
ANSEL
PORTE
08h
09h
TRISE
89h
CM2CON1
109h
ANSELH
189h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
EEDAT
10Ch
EECON1
18Ch
PIR2
0Dh
PIE2
8Dh
EEADR
10Dh
EECON2(1)
18Dh
TMR1L
0Eh
PCON
8Eh
EEDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
OSCCON
8Fh
EEADRH
10Fh
Reserved
18Fh
T1CON
10h
OSCTUNE
90h
110h
190h
TMR2
11h
SSPCON2
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
193h
SSPBUF
13h
SSPADD
93h
113h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
116h
196h
CCP1CON
17h
VRCON
97h
117h
197h
RCSTA
18h
TXSTA
98h
118h
198h
TXREG
19h
SPBRG
99h
119h
199h
19Ah
RCREG
1Ah
SPBRGH
9Ah
11Ah
CCPR2L
1Bh
PWM1CON
9Bh
11Bh
19Bh
CCPR2H
1Ch
ECCPAS
9Ch
11Ch
19Ch
CCP2CON
1Dh
PSTRCON
9Dh
11Dh
19Dh
ADRESH
1Eh
ADRESL
9Eh
11Eh
19Eh
ADCON0
1Fh
ADCON1
9Fh
11Fh
19Fh
20h
General
Purpose
Registers
A0h
120h
1A0h
General
Purpose
Registers
32 Bytes
BFh
C0h
96 Bytes
EFh
7Fh
Bank 0
accesses
70h-7Fh
F0h
FFh
Bank 1
16Fh
accesses
70h-7Fh
Bank 2
170h
17Fh
1EFh
accesses
70h-7Fh
1F0h
1FFh
Bank 3
DS41291E-page 23
PIC16F882/883/884/886/887
FIGURE 2-5:
File
File
File
Address
Address
Address
Address
00h
80h
100h
180h
TMR0
01h
OPTION_REG
81h
TMR0
101h
OPTION_REG
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
WDTCON
105h
SRCON
185h
PORTB
06h
TRISB
86h
PORTB
106h
TRISB
186h
PORTC
07h
TRISC
87h
CM1CON0
107h
BAUDCTL
187h
PORTD(2)
08h
TRISD(2)
88h
CM2CON0
108h
ANSEL
188h
PORTE
09h
TRISE
89h
CM2CON1
109h
ANSELH
189h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
EEDAT
10Ch
EECON1
18Ch
PIR2
0Dh
PIE2
8Dh
EEADR
10Dh
EECON2(1)
18Dh
TMR1L
0Eh
PCON
8Eh
EEDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
OSCCON
8Fh
EEADRH
10Fh
Reserved
18Fh
T1CON
10h
OSCTUNE
90h
110h
190h
TMR2
11h
SSPCON2
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
SSPBUF
13h
SSPADD
93h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
116h
196h
CCP1CON
17h
VRCON
97h
117h
197h
RCSTA
18h
TXSTA
98h
118h
198h
TXREG
19h
SPBRG
99h
119h
199h
RCREG
1Ah
SPBRGH
9Ah
11Ah
19Ah
CCPR2L
1Bh
PWM1CON
9Bh
11Bh
19Bh
CCPR2H
1Ch
ECCPAS
9Ch
11Ch
19Ch
CCP2CON
1Dh
PSTRCON
9Dh
11Dh
19Dh
ADRESH
1Eh
ADRESL
9Eh
11Eh
19Eh
ADCON0
1Fh
ADCON1
9Fh
11Fh
19Fh
120h
1A0h
20h
General
Purpose
Registers
General
Purpose
Registers
80 Bytes
General
Purpose
Registers
80 Bytes
EFh
96 Bytes
7Fh
Bank 0
A0h
accesses
70h-7Fh
F0h
FFh
Bank 1
16Fh
accesses
70h-7Fh
Bank 2
170h
17Fh
1EFh
accesses
70h-7Fh
1F0h
1FFh
Bank 3
DS41291E-page 24
PIC16F882/883/884/886/887
FIGURE 2-6:
File
File
File
Address
Address
Address
Address
00h
80h
100h
180h
TMR0
01h
OPTION_REG
81h
TMR0
101h
OPTION_REG
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
WDTCON
105h
SRCON
185h
PORTB
06h
TRISB
86h
PORTB
106h
TRISB
186h
PORTC
07h
TRISC
87h
CM1CON0
107h
BAUDCTL
187h
PORTD(2)
08h
TRISD(2)
88h
CM2CON0
108h
ANSEL
188h
PORTE
09h
TRISE
89h
CM2CON1
109h
ANSELH
189h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
EEDAT
10Ch
EECON1
18Ch
PIR2
0Dh
PIE2
8Dh
EEADR
10Dh
EECON2(1)
18Dh
TMR1L
0Eh
PCON
8Eh
EEDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
OSCCON
8Fh
EEADRH
10Fh
Reserved
18Fh
T1CON
10h
OSCTUNE
90h
110h
190h
TMR2
11h
SSPCON2
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
SSPBUF
13h
SSPADD
93h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
CCP1CON
17h
VRCON
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
SPBRG
99h
General
Purpose
Registers
116h
16 Bytes
119h
117h
118h
General
Purpose
Registers
196h
16 Bytes
199h
197h
198h
RCREG
1Ah
SPBRGH
9Ah
11Ah
19Ah
CCPR2L
1Bh
PWM1CON
9Bh
11Bh
19Bh
CCPR2H
1Ch
ECCPAS
9Ch
11Ch
19Ch
CCP2CON
1Dh
PSTRCON
9Dh
11Dh
19Dh
ADRESH
1Eh
ADRESL
9Eh
11Eh
19Eh
ADCON0
1Fh
ADCON1
9Fh
11Fh
19Fh
20h
General
Purpose
Registers
3Fh
96 Bytes
6Fh
40h
General
Purpose
Registers
A0h
80 Bytes
70h
7Fh
Bank 0
120h
General
Purpose
Registers
80 Bytes
EFh
accesses
70h-7Fh
F0h
FFh
Bank 1
1A0h
General
Purpose
Registers
80 Bytes
16Fh
accesses
70h-7Fh
Bank 2
170h
17Fh
1EFh
accesses
70h-7Fh
1F0h
1FFh
Bank 3
DS41291E-page 25
PIC16F882/883/884/886/887
TABLE 2-1:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
37,217
01h
TMR0
xxxx xxxx
73,217
02h
PCL
0000 0000
37,217
03h
STATUS
29,217
04h
FSR
05h
PORTA(3)
06h
PORTB(3)
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
48,217
07h
PORTC(3)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
53,217
08h
PORTD(3,4)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
57,217
09h
PORTE(3)
RE3
RE2(4)
RE1(4)
RE0(4)
---- xxxx
59,217
0Ah
PCLATH
---0 0000
37,217
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF(1)
0000 000x
31,217
0Ch
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
34,217
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
IRP
RP1
RP0
TO
PD
DC
0001 1xxx
xxxx xxxx
37,217
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
39,217
RA6
RA5
0Dh
PIR2
0000 00-0
35,217
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
76,217
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
76,217
0000 0000
79,217
10h
T1CON
11h
TMR2
12h
T2CON
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
0000 0000
81,217
82,217
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
xxxx xxxx
183,217
SSPM2
SSPM1
SSPM0
0000 0000
181,217
xxxx xxxx
126,217
13h
SSPBUF
14h
SSPCON(2)
15h
CCPR1L
16h
CCPR1H
xxxx xxxx
126,217
17h
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
124,217
18h
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
161,217
19h
TXREG
0000 0000
153,217
1Ah
RCREG
0000 0000
158,217
1Bh
CCPR2L
xxxx xxxx
126,217
1Ch
CCPR2H
xxxx xxxx
126,218
1Dh
CCP2CON
--00 0000
125,218
1Eh
ADRESH
1Fh
ADCON0
Legend:
Note 1:
2:
3:
4:
SSPOV
SSPEN
DC2B1
CKP
DC2B0
SSPM3
CCP2M3
CCP2M2
CCP2M1
CCP2M0
ADCS0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
xxxx xxxx
99,218
0000 0000
104,218
= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers and 13-4 for more detail.
Port pins with analog functions controlled by the ANSEL and ANSELH registers will read 0 immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
PIC16F884/PIC16F887 only.
DS41291E-page 26
PIC16F882/883/884/886/887
TABLE 2-2:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h
INDF
81h
OPTION_REG
Addressing this location uses contents of FSR to address data memory (not a physical register)
82h
PCL
83h
STATUS
84h
FSR
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
DC
RP1
RP0
TO
xxxx xxxx
37,217
1111 1111
30,218
0000 0000
37,217
0001 1xxx
29,217
xxxx xxxx
37,217
39,218
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
48,218
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
53,218
88h
TRISD(3)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
89h
TRISE
TRISE3
8Ah
PCLATH
8Bh
INTCON
GIE
PEIE
T0IE
8Ch
PIE1
ADIE
8Dh
PIE2
OSFIE
C2IE
8Eh
PCON
8Fh
OSCCON
90h
OSCTUNE
91h
SSPCON2
GCEN
1111 1111
57,218
---- 1111
59,218
---0 0000
37,217
0000 000x
31,217
T0IF
INTF
RBIF(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
32,218
BCLIE
ULPWUIE
CCP2IE
0000 00-0
33,218
POR
BOR
--01 --qq
36,218
OSTS
HTS
LTS
SCS
-110 q000
62,218
TUN3
TUN2
TUN1
TUN0
---0 0000
66,218
RCEN
PEN
RSEN
SEN
0000 0000
181,218
INTE
RBIE
RCIE
TXIE
C1IE
EEIE
ULPWUE
SBOREN
IRCF2
IRCF1
IRCF0
TUN4
ACKSTAT
ACKDT
ACKEN
92h
PR2
1111 1111
81,218
93h
SSPADD(2)
0000 0000
189,218
93h
SSPMSK(2)
1111 1111
189,218
94h
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
189,218
95h
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
49,218
96h
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
49,218
97h
VRCON
VREN
VROE
VRR
VRSS
VR3
VR2
VR1
VR0
0000 0000
97,218
98h
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
160,218
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
99h
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
163,218
9Ah
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
163,218
PRSEN
PDC6
PDC5
PDC4
9Bh
PWM1CON
9Ch
ECCPAS
9Dh
PSTRCON
9Eh
ADRESL
9Fh
ADCON1
Legend:
Note 1:
2:
3:
STRSYNC
PDC3
PDC2
PDC1
PDC0
0000 0000
145,218
PSSAC1
PSSAC0
PSSBD1
PSSBD0
0000 0000
142,218
STRD
STRC
STRB
STRA
---0 0001
146,218
VCFG1
VCFG0
xxxx xxxx
99,218
0-00 ----
105,218
= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
Accessible only when SSPCON register bits SSPM<3:0> = 1001.
PIC16F884/PIC16F887 only.
DS41291E-page 27
PIC16F882/883/884/886/887
TABLE 2-3:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
37,217
101h
TMR0
xxxx xxxx
73,217
102h
PCL
0000 0000
37,217
103h
STATUS
0001 1xxx
29,217
IRP
RP1
RP0
TO
PD
DC
xxxx xxxx
37,217
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
---0 1000
225,218
104h
FSR
105h
WDTCON
106h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
48,217
107h
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1R
C1CH1
C1CH0
0000 -000
88,218
108h
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2R
C2CH1
C2CH0
0000 -000
89,218
109h
CM2CON1
MC1OUT
MC2OUT
C1RSEL
C2RSEL
T1GSS
C2SYNC
0000 --10
91,219
---0 0000
37,217
10Ah PCLATH
10Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF(1)
0000 000x
31,217
10Ch EEDAT
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
0000 0000
112,219
10Dh EEADR
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
0000 0000
112,219
10Eh EEDATH
EEDATH5
EEDATH4
EEDATH3
EEDATH2
EEDATH1
EEDATH0
--00 0000
112,219
10Fh EEADRH
112,219
Legend:
Note 1:
= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
PIC16F886/PIC16F887 only.
2:
TABLE 2-4:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
xxxx xxxx
37,217
30,218
Bank 3
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
181h
OPTION_REG
182h
PCL
183h
STATUS
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
37,217
TO
PD
DC
0001 1xxx
29,217
184h
FSR
185h
SRCON
186h
TRISB
187h
BAUDCTL
188h
ANSEL
189h
IRP
RP1
RP0
xxxx xxxx
37,217
SR1
SR0
C1SEN
C2REN
PULSS
PULSR
FVREN
0000 00-0
93,219
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
48,218
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
162,219
ANS7(2)
ANS6(2)
ANS5(2)
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
40,219
ANSELH
ANS13
ANS12
ANS11
ANS10
ANS9
ANS8
--11 1111
99,219
18Ah
PCLATH
18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
EEPGD
WRERR
WREN
WR
18Ch
EECON1
18Dh
EECON2
Legend:
Note 1:
2:
---0 0000
37,217
RBIF(1)
0000 000x
31,217
RD
x--- x000
113,219
---- ----
111,219
= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
PIC16F884/PIC16F887 only.
DS41291E-page 28
PIC16F882/883/884/886/887
2.2.2.1
STATUS Register
REGISTER 2-1:
R/W-0
IRP
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
R/W-x
R/W-x
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41291E-page 29
PIC16F882/883/884/886/887
2.2.2.2
OPTION Register
Note:
Timer0/WDT prescaler
External INT interrupt
Timer0
Weak pull-ups on PORTB
REGISTER 2-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS41291E-page 30
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
x = Bit is unknown
PIC16F882/883/884/886/887
2.2.2.3
INTCON Register
Note:
REGISTER 2-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE(1)
T0IF(2)
INTF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
DS41291E-page 31
PIC16F882/883/884/886/887
2.2.2.4
PIE1 Register
REGISTER 2-4:
Note:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41291E-page 32
x = Bit is unknown
PIC16F882/883/884/886/887
2.2.2.5
PIE2 Register
REGISTER 2-5:
Note:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULPWUIE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
x = Bit is unknown
DS41291E-page 33
PIC16F882/883/884/886/887
2.2.2.6
PIR1 Register
REGISTER 2-6:
Note:
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41291E-page 34
PIC16F882/883/884/886/887
2.2.2.7
PIR2 Register
REGISTER 2-7:
Note:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS41291E-page 35
PIC16F882/883/884/886/887
2.2.2.8
PCON Register
REGISTER 2-8:
U-0
U-0
R/W-0
R/W-1
U-0
U-0
R/W-0
R/W-x
ULPWUE
SBOREN(1)
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
BOREN<1:0> = 01 in the Configuration Word Register 1 for this bit to control the BOR.
DS41291E-page 36
PIC16F882/883/884/886/887
2.3
2.3.2
FIGURE 2-7:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
PC
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
PC
GOTO, CALL
2
PCLATH<4:3>
11
OPCODE<10:0>
PCLATH
2.3.1
STACK
MODIFYING PCL
2.4
EXAMPLE 2-1:
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSS
GOTO
CONTINUE
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
DS41291E-page 37
PIC16F882/883/884/886/887
FIGURE 2-8:
Direct Addressing
RP1 RP0
Bank Select
From Opcode
Indirect Addressing
0
IRP
Bank Select
Location Select
00
01
10
Location Select
11
00h
180h
Data
Memory
7Fh
1FFh
Bank 0
Note:
DS41291E-page 38
Bank 1
Bank 2
Bank 3
PIC16F882/883/884/886/887
3.0
I/O PORTS
3.1
Note:
EXAMPLE 3-1:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
REGISTER 3-1:
PORTA
PORTA
ANSEL
ANSEL
TRISA
0Ch
TRISA
INITIALIZING PORTA
;
;Init PORTA
;
;digital I/O
;
;Set RA<3:2> as inputs
;and set RA<5:4,1:0>
;as outputs
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 3-2:
R/W-1(1)
R/W-1(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
DS41291E-page 39
PIC16F882/883/884/886/887
3.2
3.2.1
ANSEL REGISTER
REGISTER 3-3:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANS7(2)
ANS6(2)
ANS5(2)
ANS4
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Note 1:
2:
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
Not implemented on PIC16F883/886.
DS41291E-page 40
PIC16F882/883/884/886/887
3.2.2
EXAMPLE 3-2:
BANKSEL
BSF
BANKSEL
BCF
BANKSEL
BCF
CALL
BANKSEL
BCF
BANKSEL
BSF
BSF
BSF
MOVLW
MOVWF
SLEEP
NOP
ULTRA LOW-POWER
WAKE-UP INITIALIZATION
PORTA
PORTA,0
ANSEL
ANSEL,0
TRISA
TRISA,0
CapDelay
PIR2
PIR2,ULPWUIF
PCON
PCON,ULPWUE
TRISA,0
PIE2, ULPWUIE
B11000000
INTCON
;
;Set RA0 data latch
;
;RA0 to digital I/O
;
;Output high to
;charge capacitor
;
;Clear flag
;Enable ULP Wake-up
;RA0 to input
;Enable interrupt
;Enable peripheral
;interrupt
;Wait for IOC
;
DS41291E-page 41
PIC16F882/883/884/886/887
3.2.3
3.2.3.1
FIGURE 3-1:
RA0/AN0/ULPWU/C12IN0-
Figure 3-1 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
VSS
+
D
WR
TRISA
CK Q
IULP
0
RD
TRISA
VTRG
Analog(1)
Input Mode
1
VSS
ULPWUE
RD
PORTA
To Comparator
To A/D Converter
Note
DS41291E-page 42
1:
PIC16F882/883/884/886/887
3.2.3.2
3.2.3.3
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
Figure 3-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-2:
Data Bus
D
WR
PORTA
CK
FIGURE 3-3:
VDD
Data Bus
WR
TRISA
CK
WR
PORTA
CK
CK
To Comparator
To A/D Converter
VSS
Analog(1)
Input Mode
RD
TRISA
1:
VDD
I/O Pin
D
WR
TRISA
RD
PORTA
Note
CVREF
VSS
Analog(1)
Input Mode
RD
TRISA
VROE
D
I/O Pin
D
RD
PORTA
1:
DS41291E-page 43
PIC16F882/883/884/886/887
3.2.3.4
RA3/AN3/VREF+/C1IN+
3.2.3.5
RA4/T0CKI/C1OUT
Figure 3-4 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-4:
FIGURE 3-5:
Data Bus
C1OUT
Enable
D
Data Bus
D
WR
PORTA
CK
WR
PORTA
VDD
WR
TRISA
CK
VSS
Analog(1)
Input Mode
RD
TRISA
CK
VDD
Q
Q
C1OUT
1
0
Q
I/O Pin
WR
TRISA
CK
I/O Pin
Q
Q
VSS
RD
TRISA
RD
PORTA
RD
PORTA
To Timer0
To Comparator (positive input)
To Comparator (VREF+)
To A/D Converter (VREF+)
To A/D Converter (analog channel)
Note
1:
DS41291E-page 44
PIC16F882/883/884/886/887
3.2.3.6
3.2.3.7
RA5/AN4/SS/C2OUT
RA6/OSC2/CLKOUT
Figure 3-6 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-7 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-6:
FIGURE 3-7:
Oscillator
Circuit
Data Bus
Data Bus
OSC2
C2OUT
Enable
D
WR
PORTA
CK
C2OUT
1
0
D
WR
TRISA
CLKOUT
Enable
VDD
I/O Pin
WR
PORTA
CK
Analog(1)
Input Mode
RD
TRISA
WR
TRISA
CK
Q
Q
RD
TRISA
RD
PORTA
I/O Pin
CLKOUT
Enable
D
VSS
CK
FOSC/4
VDD
VSS
INTOSCIO/
EXTRCIO/EC(1)
CLKOUT
Enable
RD
PORTA
To SS Input
To A/D Converter
Note
1:
DS41291E-page 45
PIC16F882/883/884/886/887
3.2.3.8
RA7/OSC1/CLKIN
Figure 3-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a crystal/resonator connection
a clock input
FIGURE 3-8:
Data Bus
OSC1
D
WR
PORTA
VDD
CK Q
I/O Pin
D
WR
TRISA
CK Q
VSS
INTOSC
Mode
RD
TRISA
RD
PORTA
CLKIN
TABLE 3-1:
Name
ADCON0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCS1
ADCS0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
0000 0000
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1R
C1CH1
C1CH0
0000 -000
0000 -000
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2R
C2CH1
C2CH0
0000 -000
0000 -000
CM2CON1
MC1OUT
MC2OUT
C1RSEL
C2RSEL
T1GSS
C2SYNC
0000 --10
0000 --10
PCON
OPTION_REG
PORTA
SSPCON
TRISA
Legend:
ULPWUE
SBOREN
POR
BOR
--01 --qq
--0u --uu
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
uuuu uuuu
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
DS41291E-page 46
PIC16F882/883/884/886/887
3.3
EXAMPLE 3-3:
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
Note:
3.4
INITIALIZING PORTB
PORTB
;
PORTB
;Init PORTB
TRISB
;
B11110000 ;Set RB<7:4> as inputs
;and RB<3:0> as outputs
TRISB
;
3.4.1
ANSELH REGISTER
3.4.2
WEAK PULL-UPS
3.4.3
INTERRUPT-ON-CHANGE
DS41291E-page 47
PIC16F882/883/884/886/887
REGISTER 3-4:
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANS13
ANS12
ANS11
ANS10
ANS9
ANS8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
REGISTER 3-5:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 3-6:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41291E-page 48
PIC16F882/883/884/886/887
REGISTER 3-7:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 3-8:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41291E-page 49
PIC16F882/883/884/886/887
3.4.4
3.4.4.1
RB0/AN12/INT
FIGURE 3-9:
Data Bus
WR
WPUB
BLOCK DIAGRAM OF
RB<3:0>
CK
RBPU
CCP1OUT Enable
D
WR
PORTB
RB1/AN10/P1C /C12IN3-
RB2/AN8/P1B(1)
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a PWM output(1)
CK
VSS
Analog(1)
Input Mode
RD
TRISB
RD
PORTB
D
Q
Q
CK Q
WR
IOCB
D
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
RB0/INT
RB3/PGM
To A/D Converter
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
DS41291E-page 50
VDD
CCP1OUT 1
0
WR
TRISB
RB3/AN9/PGM/C12IN2-
CK
3.4.4.4
I/O Pin
(1)
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
3.4.4.3
Weak
RD
WPUB
VDD
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
3.4.4.2
Analog(1)
Input Mode
1:
PIC16F882/883/884/886/887
3.4.4.5
RB4/AN11/P1D(1)
3.4.4.7
RB6/ICSPCLK
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
3.4.4.8
3.4.4.6
RB7/ICSPDAT
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
RB5/AN13/T1G
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a Timer1 gate input
FIGURE 3-10:
Data Bus
WR
WPUB
CK
VDD
Weak
RD
WPUB
RBPU
CCP1OUT Enable
VDD
D
WR
PORTB
CK
CCP1OUT
0
11
I/O Pin
00
1
D
WR
TRISB
CK
Q
VSS
RD
TRISB
Analog(1)
Input Mode
RD
PORTB
D
CK
WR
IOCB
Q
Q
ICSP(2)
Q
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
To Timer1 T1G(3)
To A/D Converter
To ICSPCLK (RB6) and ICSPDAT (RB7)
1:
2:
3:
DS41291E-page 51
PIC16F882/883/884/886/887
TABLE 3-2:
Name
Bit 5
Bit 4
ANS13
ANS12
P1M1
P1M0
DC1B1
DC1B0
ANSELH
CCP1CON
Bit 6
CM2CON1
IOCB
INTCON
OPTION_REG
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
ANS11
ANS10
ANS9
ANS8
T1GSS
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
Legend:
x = unknown, u = unchanged, = unimplemented read as 0. Shaded cells are not used by PORTB.
DS41291E-page 52
PIC16F882/883/884/886/887
3.5
EXAMPLE 3-4:
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
REGISTER 3-9:
INITIALIZING PORTC
PORTC
PORTC
TRISC
B00001100
TRISC
;
;Init PORTC
;
;Set RC<3:2> as inputs
;and set RC<7:4,1:0>
;as outputs
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 3-10:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1(1)
R/W-1(1)
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
DS41291E-page 53
PIC16F882/883/884/886/887
3.5.1
3.5.3
RC0/T1OSO/T1CKI
RC2/P1A/CCP1
Figure 3-11 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-13 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-11:
Data Bus
T1OSCEN
D
FIGURE 3-13:
Timer1 Oscillator
Circuit
CCP1CON
VDD
WR
PORTC
CK
Data bus
WR
PORTC
CK
VDD
Q
Q
CCP1/P1A
0
1
I/O Pin
D
WR
TRISC
0
1
CK
D
Q
VSS
WR
TRISC
RD
TRISC
CK
I/O Pin
Q
Q
VSS
RD
TRISC
RD
PORTC
RD
PORTC
To Enhanced CCP1
To Timer1 clock input
3.5.2
RC1/T1OSI/CCP2
Figure 3-12 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a Timer1 oscillator input
a Capture input and Compare/PWM output for
Comparator C2
FIGURE 3-12:
T1OSCEN
T1OSI
Data Bus
Timer1 Oscillator
Circuit
CCP2CON
D
WR
PORTC
CK
VDD
Q
Q
CCP2
0
1
1
0
D
WR
TRISC
CK
I/O Pin
Q
Q
VSS
T1OSCEN
RD
TRISC
RD
PORTC
To CCP2
DS41291E-page 54
PIC16F882/883/884/886/887
3.5.4
RC3/SCK/SCL
3.5.6
RC5/SDO
Figure 3-14 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-16 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-14:
FIGURE 3-16:
Data Bus
Port/SDO
Select
Data Bus
SSPEN
D
WR
PORTC
CK Q
SDO
VDD
0
1
SCK
WR
PORTC
1
0
0
1
1
0
VDD
I/O Pin
CK Q
I/O Pin
D
WR
TRISC
CK Q
WR
TRISC
VSS
RD
TRISC
RD
TRISC
RD
PORTC
RD
PORTC
CK Q
VSS
To SSPSR
3.5.5
RC4/SDI/SDA
Figure 3-15 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a SPI data I/O
an I2C data I/O
FIGURE 3-15:
Data Bus
SSPEN
D
WR
PORTC
SDI/SDA
CK Q
VDD
0
1
1
0
I/O Pin
D
WR
TRISC
CK Q
VSS
RD
TRISC
RD
PORTC
To SSPSR
DS41291E-page 55
PIC16F882/883/884/886/887
3.5.7
3.5.8
RC6/TX/CK
RC7/RX/DT
Figure 3-17 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-18 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-17:
FIGURE 3-18:
SPEN
SPEN
TXEN
SYNC
Data Bus
SYNC
EUSART
CK 1
0
Data Bus
EUSART
TX 0
1
D
WR
PORTC
WR
PORTC
VDD
I/O Pin
D
1
0
D
WR
TRISC
CK Q
VDD
0
1
1
0
0
1
CK Q
EUSART
DT
WR
TRISC
I/O Pin
CK Q
CK Q
VSS
RD
TRISC
VSS
RD
PORTC
RD
TRISC
EUSART RX/DT
RD
PORTC
TABLE 3-3:
Name
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
STRSYNC
STRD
STRC
STRB
STRA
---0 0001
---0 0001
Bit 7
Bit 6
Bit 5
CCP1CON
P1M1
P1M0
CCP2CON
RC7
PORTC
PSTRCON
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
T1CON
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTC.
DS41291E-page 56
PIC16F882/883/884/886/887
3.6
EXAMPLE 3-5:
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTD
PORTD
PORTD
TRISD
B00001100
TRISD
;
;Init PORTD
;
;Set RD<3:2> as inputs
;and set RD<7:4,1:0>
;as outputs
REGISTER 3-11:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 3-12:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41291E-page 57
PIC16F882/883/884/886/887
3.6.1
RD<4:0>
3.6.3
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a PWM output
FIGURE 3-19:
BLOCK DIAGRAM OF
RD<4:0>
3.6.4
Data Bus
D
WR
PORTD
CK
I/O Pin
D
WR
TRISD
CK
RD7/P1D(1)
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
VDD
RD6/P1C(1)
VSS
FIGURE 3-20:
BLOCK DIAGRAM OF
RD<7:5>
RD
TRISD
Data Bus
RD
PORTD
3.6.2
D
WR
PORTD
RD5/P1B(1)
D
WR
TRISD
PORTD
PSTRCON
TRISD
Legend:
CCP1
0
1
CK
I/O Pin
Q
Q
VSS
RD
TRISD
TABLE 3-4:
CK
VDD
1
0
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Name
PSTRCON
RD
PORTD
Bit 3
Bit 2
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RD1
RD0
xxxx xxxx
uuuu uuuu
STRB
STRA
---0 0001
---0 0001
TRISD0
1111 1111
1111 1111
Bit 7
Bit 6
Bit 5
Bit 1
RD7
RD6
RD5
RD4
RD3
RD2
STRSYNC
STRD
STRC
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTD.
DS41291E-page 58
PIC16F882/883/884/886/887
3.7
Note:
EXAMPLE 3-6:
REGISTER 3-13:
U-0
BANKSEL
CLRF
BANKSEL
CLRF
BCF
BANKSEL
MOVLW
MOVWF
on
INITIALIZING PORTE
PORTE
PORTE
ANSEL
ANSEL
STATUS,RP1
TRISE
B00001100
TRISE
;
;Init PORTE
;
;digital I/O
;Bank 1
;
;Set RE<3:2> as inputs
;and set RE<1:0>
;as outputs
available
U-0
U-0
R-x
R/W-x
R/W-x
R/W-x
RE3
RE2
RE1
RE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
REGISTER 3-14:
x = Bit is unknown
U-0
U-0
U-0
U-0
R-1(1)
R/W-1
R/W-1
R/W-1
TRISE3
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
x = Bit is unknown
DS41291E-page 59
PIC16F882/883/884/886/887
RE0/AN5(1)
3.7.1
3.7.4
RE3/MCLR/VPP
Figure 3-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
FIGURE 3-22:
RE1/AN6(1)
3.7.2
MCLRE
Data Bus
MCLRE
Reset
RD
TRISE
Weak
Input
Pin
VSS
MCLRE
RD
PORTE
VSS
RE2/AN7(1)
3.7.3
FIGURE 3-21:
BLOCK DIAGRAM OF
RE<2:0>
Data Bus
D
WR
PORTE
VDD
CK
Q
I/O Pin
D
WR
TRISE
CK
VSS
Analog(1)
Input Mode
RD
TRISE
RD
PORTE
To A/D Converter
Note
1:
TABLE 3-5:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other Resets
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
PORTE
RE3
RE2
RE1
RE0
---- xxxx
---- uuuu
TRISE
TRISE3
TRISE2
TRISE1
TRISE0
---- 1111
---- 1111
Name
Legend:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTE
DS41291E-page 60
PIC16F882/883/884/886/887
4.0
4.1
Overview
4.
5.
6.
7.
8.
FIGURE 4-1:
External Oscillator
OSC2
Sleep
MUX
OSC1
IRCF<2:0>
(OSCCON Register)
4 MHz
HFINTOSC
8 MHz
Postscaler
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
LFINTOSC
31 kHz
31 kHz
INTOSC
111
110
101
100
011
MUX
8 MHz
Internal Oscillator
System Clock
(CPU and Peripherals)
010
001
000
DS41291E-page 61
PIC16F882/883/884/886/887
4.2
Oscillator Control
REGISTER 4-1:
U-0
R/W-1
R/W-1
R/W-0
R-1
R-0
R-0
R/W-0
IRCF2
IRCF1
IRCF0
OSTS(1)
HTS
LTS
SCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
Bit resets to 0 with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
DS41291E-page 62
PIC16F882/883/884/886/887
4.3
TABLE 4-1:
4.4
4.4.1
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
LFINTOSC
HFINTOSC
31 kHz
125 kHz to 8 MHz
Sleep/POR
EC, RC
DC 20 MHz
2 cycles
EC, RC
DC 20 MHz
1 cycle of each
Sleep/POR
LP, XT, HS
32 kHz to 20 MHz
HFINTOSC
1 s (approx.)
4.4.2
EC MODE
FIGURE 4-2:
Clock from
Ext. System
PIC MCU
I/O
Note 1:
OSC2/CLKOUT(1)
DS41291E-page 63
PIC16F882/883/884/886/887
4.4.3
FIGURE 4-3:
FIGURE 4-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC MCU
OSC1/CLKIN
PIC MCU
C1
To Internal
Logic
OSC1/CLKIN
C1
Quartz
Crystal
C2
RP(3)
To Internal
Logic
RS(1)
RF(2)
RF(2)
Sleep
Sleep
C2 Ceramic
RS(1)
Resonator
OSC2/CLKOUT
Note 1:
OSC2/CLKOUT
Note 1:
2:
DS41291E-page 64
PIC16F882/883/884/886/887
4.4.4
4.5
EXTERNAL RC MODES
FIGURE 4-5:
VDD
EXTERNAL RC MODES
PIC MCU
REXT
OSC1/CLKIN
Internal
Clock
CEXT
2.
4.5.1
VSS
FOSC/4 or
I/O(2)
OSC2/CLKOUT
(1)
4.5.2
HFINTOSC
DS41291E-page 65
PIC16F882/883/884/886/887
4.5.2.1
OSCTUNE Register
REGISTER 4-2:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0
bit 4-0
00001 =
00000 = Oscillator module is running at the factory-calibrated frequency.
11111 =
DS41291E-page 66
PIC16F882/883/884/886/887
4.5.3
LFINTOSC
4.5.4
8 MHz
4 MHz (Default after Reset)
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz (LFINTOSC)
Note:
4.5.5
6.
DS41291E-page 67
PIC16F882/883/884/886/887
FIGURE 4-6:
HFINTOSC
HFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
IRCF <2:0>
=0
System Clock
HFINTOSC
HFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <2:0>
=0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC
Start-up Time
2-cycle Sync
Running
HFINTOSC
IRCF <2:0>
=0
System Clock
DS41291E-page 68
PIC16F882/883/884/886/887
4.6
Clock Switching
4.6.1
4.6.2
4.7
4.7.1
4.7.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
DS41291E-page 69
PIC16F882/883/884/886/887
4.7.3
FIGURE 4-7:
TWO-SPEED START-UP
HFINTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC
PC + 1
System Clock
DS41291E-page 70
PIC16F882/883/884/886/887
4.8
4.8.3
FIGURE 4-8:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
4.8.1
4.8.4
FAIL-SAFE DETECTION
4.8.2
FAIL-SAFE OPERATION
DS41291E-page 71
PIC16F882/883/884/886/887
FIGURE 4-9:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Name
Bit 7
CONFIG1(2)
OSCTUNE
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 4-2:
OSCCON
Test
Value on
POR, BOR
Value on
all other
Resets(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
IRCF2
IRCF1
IRCF0
OSTS
HTS
LTS
SCS
-110 x000
-110 x000
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000
---u uuuu
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULPWUIE
CCP2IE
0000 00-0
0000 00-0
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
0000 00-0
0000 00-0
Legend:
Note 1:
2:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word Register 1 (Register 14-1) for operation of all register bits.
DS41291E-page 72
PIC16F882/883/884/886/887
5.0
TIMER0 MODULE
5.1
Timer0 Operation
5.1.1
5.1.2
FIGURE 5-1:
FOSC/4
Data Bus
0
8
1
1
T0CKI
pin
T0SE
T0CS
0
8-bit
Prescaler
PSA
PS<2:0>
31 kHz
INTOSC
PSA
16-bit
Prescaler
TMR0
WDTE
SWDTEN
Sync
2 Tcy
1
WDT
Time-out
16
Watchdog
Timer
0
PSA
WDTPS<3:0>
Note
1:
2:
3:
DS41291E-page 73
PIC16F882/883/884/886/887
5.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
5.1.3.1
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0 WDT)
BANKSEL
CLRWDT
CLRF
TMR0
BANKSEL
BSF
CLRWDT
OPTION_REG
OPTION_REG,PSA
MOVLW
ANDWF
IORLW
MOVWF
b11111000
OPTION_REG,W
b00000101
OPTION_REG
TMR0
DS41291E-page 74
;
;Clear WDT
;Clear TMR0 and
;prescaler
;
;Select WDT
;
;
;Mask prescaler
;bits
;Set WDT prescaler
;to 1:32
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT TIMER0)
CLRWDT
5.1.4
TIMER0 INTERRUPT
5.1.5
PIC16F882/883/884/886/887
REGISTER 5-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
WDT RATE
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
A dedicated 16-bit WDT postscaler is available. See Section 14.5 Watchdog Timer (WDT) for more
information.
TABLE 5-1:
Name
TMR0
INTCON
OPTION_REG
TRISA
TMR0 RATE
x = Bit is unknown
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
T0IE
INTE
RBIE
T0IF
INTF
RBIF
T0CS
T0SE
PSA
PS2
PS1
PS0
PEIE
RBPU INTEDG
Value on
all other
Resets
Bit 4
Bit 5
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
DS41291E-page 75
PIC16F882/883/884/886/887
6.0
6.1
6.2
Clock Source
FIGURE 6-1:
Timer1 Operation
TMR1CS
FOSC/4
T1CKI pin
T1GINV
TMR1ON
Set flag bit
TMR1IF on
Overflow
To C2 Comparator Module
Timer1 Clock
TMR1(2)
TMR1H
TMR1L
Synchronized
clock input
EN
1
Oscillator
T1SYNC
(1)
OSC1/T1CKI
1
0
OSC2/T1G
Synchronize(3)
Prescaler
1, 2, 4, 8
det
2
T1CKPS<1:0>
TMR1CS
1
INTOSC
Without CLKOUT
T1OSCEN
FOSC
FOSC/4
Internal
Clock
SYNCC2OUT(4)
0
T1GSS
T1ACS
Note 1:
2:
3:
4:
DS41291E-page 76
ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.
Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.
PIC16F882/883/884/886/887
6.2.1
6.2.2
6.5
6.3
Timer1 Prescaler
6.4
Timer1 Oscillator
Timer1 Operation in
Asynchronous Counter Mode
6.5.1
6.6
Timer1 Gate
DS41291E-page 77
PIC16F882/883/884/886/887
6.7
Timer1 Interrupt
6.8
6.9
FIGURE 6-2:
6.10
6.11
Comparator Synchronization
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
DS41291E-page 78
PIC16F882/883/884/886/887
6.12
REGISTER 6-1:
R/W-0
R/W-0
(1)
T1GINV
TMR1GE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
x = Bit is unknown
DS41291E-page 79
PIC16F882/883/884/886/887
TABLE 6-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
CM2CON1
MC1OUT
MC2OUT
C1RSEL
C2RSEL
GIE
PEIE
T0IE
INTE
PIE1
ADIE
RCIE
TXIE
PIR1
ADIF
RCIF
TXIF
INTCON
Bit 3
Value on
POR, BOR
Value on
all other
Resets
Bit 2
Bit 1
Bit 0
T1GSS
C2SYNC
0000 --10
0000 --10
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0000 0000
uuuu uuuu
T1CON
Legend:
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the Timer1 module.
DS41291E-page 80
PIC16F882/883/884/886/887
7.0
TIMER2 MODULE
7.1
Timer2 Operation
FIGURE 7-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16
2
TMR2
Comparator
Sets Flag
bit TMR2IF
Reset
EQ
Postscaler
1:1 to 1:16
T2CKPS<1:0>
PR2
4
TOUTPS<3:0>
DS41291E-page 81
PIC16F882/883/884/886/887
REGISTER 7-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
TABLE 7-1:
x = Bit is unknown
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
1111 1111
1111 1111
0000 0000
0000 0000
-000 0000
-000 0000
PR2
TMR2
T2CON
Legend:
x = unknown, u = unchanged, = unimplemented read as 0. Shaded cells are not used for Timer2 module.
DS41291E-page 82
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
PIC16F882/883/884/886/887
8.0
COMPARATOR MODULE
8.1
Comparator Overview
FIGURE 8-1:
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Note:
DS41291E-page 83
PIC16F882/883/884/886/887
FIGURE 8-2:
C1POL
D
Q1
C12IN0-
C12IN1C12IN2-
1
MUX
2
C12IN3-
EN
To
Data Bus
RD_CM1CON0
D
Q3*RD_CM1CON0
Set C1IF
EN
CL
To PWM Logic
Reset
C1ON(1)
C1R
C1IN+
FixedRef
CVREF
0
MUX
1
C1VIN- C1
C1VIN+
+
0
MUX
C1VREF
1
C1OUT
C1OUT (to SR Latch)
C1POL
C1RSEL
Note 1:
2:
3:
FIGURE 8-3:
When C1ON = 0, the C1 comparator will produce a 0 output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
EN
RD_CM2CON0
C2CH<1:0>
2
D
Q3*RD_CM2CON0
C2ON(1)
C12IN0-
C12IN1C12IN2-
1
MUX
2
C12IN3-
CVREF
EN
CL
C2OUT
C2
C2POL
D
FixedRef
Set C2IF
C2SYNC
C2R
C2IN+
Reset
C2VINC2VIN+
To
Data Bus
0
MUX
1
From Timer1
Clock
0
MUX
1
SYNCC2OUT
To Timer1 Gate, SR Latch
and other peripherals
0
MUX
C2VREF
1
C2RSEL
Note 1:
2:
3:
DS41291E-page 84
When C2ON = 0, the C2 comparator will produce a 0 output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
PIC16F882/883/884/886/887
8.2
Comparator Control
Enable
Input selection
Reference selection
Output selection
Output polarity
8.2.1
COMPARATOR ENABLE
8.2.2
8.2.3
COMPARATOR REFERENCE
SELECTION
8.2.4
8.2.5
TABLE 8-1:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
8.3
COMPARATOR OUTPUT
SELECTION
DS41291E-page 85
PIC16F882/883/884/886/887
8.4
FIGURE 8-4:
COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
Q1
Q3
CIN+
TRT
CxOUT
Set CxIF (level)
CxIF
reset by software
FIGURE 8-5:
COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Q1
Q3
CxIN+
TRT
CxOUT
Set CxIF (level)
CxIF
cleared by CMxCON0 read
reset by software
DS41291E-page 86
PIC16F882/883/884/886/887
8.5
8.6
Effects of a Reset
DS41291E-page 87
PIC16F882/883/884/886/887
REGISTER 8-1:
R/W-0
R-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
C1ON
C1OUT
C1OE
C1POL
C1R
C1CH1
C1CH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1-0
Note 1:
x = Bit is unknown
Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port
TRIS bit = 0.
DS41291E-page 88
PIC16F882/883/884/886/887
REGISTER 8-2:
R/W-0
R-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
C2ON
C2OUT
C2OE
C2POL
C2R
C2CH1
C2CH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1-0
Note 1:
x = Bit is unknown
Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.
DS41291E-page 89
PIC16F882/883/884/886/887
8.7
FIGURE 8-6:
Rs < 10K
To ADC Input
AIN
VA
RIC
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
500 nA
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
= Interconnect Resistance
= Source Impedance
RS
= Analog Voltage
VA
VT
= Threshold Voltage
Note 1: See Section 17.0 Electrical Specifications.
DS41291E-page 90
PIC16F882/883/884/886/887
8.8
8.8.1
8.8.2
SYNCHRONIZING COMPARATOR
C2 OUTPUT TO TIMER1
8.8.3
SIMULTANEOUS COMPARATOR
OUTPUT READ
REGISTER 8-3:
R-0
R-0
R/W-0
R/W-0
U-0
U-0
R/W-1
R/W-0
MC1OUT
MC2OUT
C1RSEL
C2RSEL
T1GSS
C2SYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
DS41291E-page 91
PIC16F882/883/884/886/887
8.9
Comparator SR Latch
8.9.2
8.9.1
LATCH OPERATION
FIGURE 8-7:
LATCH OUTPUT
PULSS
Pulse
Gen(2)
C1OE
0
MUX
1
C1OUT pin(3)
C1SEN
SR
Latch(1)
C2OE
C2REN
PULSR
Note 1:
2:
3:
Pulse
Gen(2)
1
MUX
0
C2OUT pin(3)
SR1
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width.
Output shown for reference only. See I/O port pin block diagram for more detail.
DS41291E-page 92
PIC16F882/883/884/886/887
REGISTER 8-4:
R/W-0
R/W-0
(2)
(2)
SR1
SR0
R/W-0
R/W-0
R/S-0
R/S-0
U-0
R/W-0
C1SEN
C2REN
PULSS
PULSR
FVREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Note 1:
2:
The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly
configured.
DS41291E-page 93
PIC16F882/883/884/886/887
8.10
8.10.3
8.10.1
INDEPENDENT OPERATION
8.10.2
EQUATION 8-1:
V RR = 1 (low range):
CVREF = (VR<3:0>/24) V LADDER
V RR = 0 (high range):
CV REF = (VLADDER/4) + (VR<3:0> VLADDER/32)
V LADDER = V DD or ([VREF+] - [VREF-]) or VREF+
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 8-8.
DS41291E-page 94
8.10.4
8.10.5
8.10.6
8.10.7
VOLTAGE REFERENCE
SELECTION
PIC16F882/883/884/886/887
FIGURE 8-8:
VREF+
VRSS = 1
8R
VRSS = 0
VRR
8R
VDD
Analog
MUX
VREFVRSS = 1
15
CVREF
VRSS = 0
To Comparators
and ADC Module
0
VR<3:0>
VROE
4
VREN
C1RSEL
C2RSEL
CVREF
FVREN
Sleep
HFINTOSC enable
FixedRef
EN
Fixed Voltage
Reference
0.6V
To Comparators
and ADC Module
FIGURE 8-9:
VREF+
AVDD
AVDD
1
0
VCFG0
VRSS
CVREF
Comparator
Voltage
Reference
VROE
ADC
Voltage
Reference
VCFG1
VRSS
0
0
AVSS
AVSS
1
VCFG1
VREF-
DS41291E-page 95
PIC16F882/883/884/886/887
TABLE 8-2:
RA3
RA2
Comp.
Reference (+)
Comp.
Reference (-)
ADC
Reference (+)
ADC
Reference (-)
CFG1
CFG0
VRSS
VROE
I/O
I/O
AVDD
AVSS
AVDD
AVSS
I/O
CVREF
AVDD
AVSS
AVDD
AVSS
VREF+
VREF-
VREF+
VREF-
AVDD
AVSS
VREF+
CVREF
VREF+
AVSS
AVDD
AVSS
VREF+
I/O
AVDD
AVSS
VREF+
AVSS
VREF+
CVREF
AVDD
AVSS
VREF+
AVSS
VREF+
VREF-
VREF+
VREF-
VREF+
AVSS
VREF+
CVREF
VREF+
AVSS
VREF+
AVSS
I/O
VREF-
AVDD
AVSS
AVDD
VREF-
0
1
I/O
VREF-
AVDD
AVSS
AVDD
VREF-
VREF+
VREF-
VREF+
VREF-
AVDD
VREF-
VREF+
VREF-
VREF+
VREF-
AVDD
VREF-
VREF+
VREF-
AVDD
AVSS
VREF+
VREF-
VREF+
VREF-
AVDD
AVSS
VREF+
VREF-
VREF+
VREF-
VREF+
VREF-
VREF+
VREF-
VREF+
VREF-
VREF+
VREF-
VREF+
VREF-
DS41291E-page 96
PIC16F882/883/884/886/887
REGISTER 8-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
VRSS
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
TABLE 8-3:
Name
ANSEL
ANSELH
CM1CON0
CM2CON0
CM2CON1
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
ANS13
ANS12
ANS11
ANS10
ANS9
ANS8
--11 1111
--11 1111
C1ON
C1OUT
C1OE
C1POL
C1R
C1CH1
C1CH0
0000 -000
0000 -000
C2ON
C2OUT
C2OE
C2POL
C2R
C2CH1
C2CH0
0000 -000
0000 -000
T1GSS
C2SYNC
0000 --10
0000 --10
0000 000x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULPWUIE
CCP2IE
0000 00-0
0000 00-0
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
0000 00-0
0000 00-0
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
uuuu uuuu
PORTA
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
SRCON
SR1
SR0
C1SEN
C2SEN
PULSS
PULSR
FVREN
0000 00-0
0000 00-0
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
VREN
VROE
VRR
VRSS
VR3
VR2
VR1
VR0
0000 0000
0000 0000
VRCON
Legend:
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used for comparator.
DS41291E-page 97
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 98
PIC16F882/883/884/886/887
9.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 9-1:
AVSS
VREF-
VCFG1 = 1
AVDD
VCFG0 = 0
VREF+
AN0
0000
AN1
0001
AN2
0010
AN3
0011
AN4
0100
AN5
0101
AN6
0110
AN7
0111
AN8
1000
AN9
1001
AN10
1010
AN11
1011
AN12
1100
AN13
1101
CVREF
1110
FixedRef
1111
VCFG0 = 1
ADC
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
10
ADON
VSS
ADRESH
ADRESL
CHS<3:0>
DS41291E-page 99
PIC16F882/883/884/886/887
9.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
9.1.1
PORT CONFIGURATION
9.1.2
CHANNEL SELECTION
DS41291E-page 100
9.1.3
9.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON0 register. There
are four possible clock options:
FOSC/2
FOSC/8
FOSC/32
FRC (dedicated internal oscillator)
PIC16F882/883/884/886/887
TABLE 9-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADCS<1:0>
FOSC/2
20 MHz
00
FOSC/8
01
100 ns
(2)
400 ns
(2)
8 MHz
250 ns
500 ns
(2)
1.0 s
FOSC/32
10
1.6 s
4.0 s
FRC
11
2-6 s(1,4)
2-6 s(1,4)
Legend:
Note 1:
2:
3:
4:
4 MHz
(2)
(2)
2.0 s
(3)
8.0 s
2-6 s(1,4)
1 MHz
2.0 s
8.0 s(3)
32.0 s(3)
2-6 s(1,4)
FIGURE 9-2:
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
9.1.5
INTERRUPTS
DS41291E-page 101
PIC16F882/883/884/886/887
9.1.6
RESULT FORMATTING
FIGURE 9-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
(ADFM = 1)
bit 7
LSB
bit 0
Unimplemented: Read as 0
9.2
9.2.1
ADC Operation
STARTING A CONVERSION
9.2.2
COMPLETION OF A CONVERSION
9.2.3
TERMINATING A CONVERSION
bit 0
bit 7
bit 0
10-bit A/D Result
9.2.4
9.2.5
DS41291E-page 102
PIC16F882/883/884/886/887
9.2.6
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (See TRIS register)
Configure pin as analog
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Select result format
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 9-1:
A/D CONVERSION
A/D
Acquisition
DS41291E-page 103
PIC16F882/883/884/886/887
9.2.7
The following registers are used to control the operation of the ADC.
Note:
REGISTER 9-1:
R/W-0
R/W-0
ADCS1
ADCS0
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-2
bit 1
bit 0
DS41291E-page 104
PIC16F882/883/884/886/887
REGISTER 9-2:
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
ADFM
VCFG1
VCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-0
Unimplemented: Read as 0
x = Bit is unknown
DS41291E-page 105
PIC16F882/883/884/886/887
REGISTER 9-3:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 9-4:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
REGISTER 9-5:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES9
ADRES8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 9-6:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41291E-page 106
PIC16F882/883/884/886/887
9.3
EQUATION 9-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + [ ( Temperature - 25C ) ( 0.05s/C ) ]
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP PLIE D 1 -------------------------n
+
1
(2
)1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
(2
)1
T C = C HOLD ( R IC + R SS + R S ) ln(1/2047)
= 10pF ( 1k + 7k + 10k ) ln(0.0004885)
= 1.37 s
Therefore:
T ACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S /C ) ]
= 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41291E-page 107
PIC16F882/883/884/886/887
FIGURE 9-4:
Rs
CPIN
5 pF
VA
VT = 0.6V
VT = 0.6V
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
500 nA
CHOLD = 10 pF
VSS/VREF-
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
= Sample/Hold Capacitance
Note 1:
6V
5V
VDD 4V
3V
2V
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
FIGURE 9-5:
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
1 LSB ideal
3FBh
Full-Scale
Transition
004h
003h
002h
001h
000h
VSS/VREF-
DS41291E-page 108
Zero-Scale
Transition
VDD/VREF+
PIC16F882/883/884/886/887
TABLE 9-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
ADCS1
ADCS0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
0000 0000
ADCON1
ADFM
VCFG1
VCFG0
0-00 ----
-000 ----
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
ANS13
ANS12
ANS11
ANS10
ANS9
ANS8
--11 1111
--11 1111
ANSELH
ADRESH
xxxx xxxx
uuuu uuuu
ADRESL
xxxx xxxx
uuuu uuuu
0000 000x
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
uuuu uuuu
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
PORTE
RE3
RE2
RE1
RE0
---- xxxx
---- uuuu
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 111
TRISE
TRISE3
TRISE2
TRISE1
TRISE0
---- 1111
---- 111
Legend:
x = unknown, u = unchanged, = unimplemented read as 0. Shaded cells are not used for ADC module.
DS41291E-page 109
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 110
PIC16F882/883/884/886/887
10.0
EECON1
EECON2
EEDAT
EEDATH
EEADR
EEADRH (bit 4 on PIC16F886/PIC16F887 only)
10.1
10.1.1
DS41291E-page 111
PIC16F882/883/884/886/887
REGISTER 10-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory
REGISTER 10-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory
bit 7-0
REGISTER 10-3:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDATH5
EEDATH4
EEDATH3
EEDATH2
EEDATH1
EEDATH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 10-4:
x = Bit is unknown
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEADRH4(1)
EEADRH3
EEADRH2
EEADRH1
EEADRH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0
bit 4-0
EEADRH<4:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads
Note 1:
PIC16F886/PIC16F887 only.
DS41291E-page 112
PIC16F882/883/884/886/887
REGISTER 10-5:
R/W-x
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS41291E-page 113
PIC16F882/883/884/886/887
10.1.2
10.1.3
EXAMPLE 10-1:
BANKSEL EEADR
MOVLW
DATA_EE_ADDR
MOVWF
EEADR
;
;
;Data Memory
;Address to read
BANKSEL EECON1
;
BCF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, RD
;EE Read
BANKSEL EEDAT
;
MOVF
EEDAT, W
;W = EEDAT
BCF
STATUS, RP1
;Bank 0
Required
Sequence
EXAMPLE 10-2:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
BCF
BSF
EEADR
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDAT
EECON1
EECON1, EEPGD
EECON1, WREN
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;
;Point to DATA memory
;Enable writes
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON,
INTCON,
$-2
55h
EECON2
AAh
EECON2
EECON1,
INTCON,
GIE
GIE
;Disable INTs.
;SEE AN576
WR
GIE
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable INTs.
SLEEP
BCF
BCF
BCF
EECON1, WREN
STATUS, RP0
STATUS, RP1
DS41291E-page 114
PIC16F882/883/884/886/887
10.1.4
Required
Sequence
EXAMPLE 10-3:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
BSF
BSF
EEADR
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADR
EECON1
EECON1, EEPGD
EECON1, RD
;
;
;MS Byte of Program Address to read
;
;LS Byte of Program Address to read
;
;Point to PROGRAM memory
;EE Read
;
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
EEDAT
EEDAT, W
LOWPMBYTE
EEDATH, W
HIGHPMBYTE
STATUS, RP1
;
;W = LS Byte of Program Memory
;
;W = MS Byte of Program EEDAT
;
;Bank 0
DS41291E-page 115
PIC16F882/883/884/886/887
FIGURE 10-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
EEADRH,EEADR
INSTR (PC + 1)
BSF EECON1,RD
executed here
PC
+3
PC+3
EEDATH,EEDAT
INSTR(PC + 1)
executed here
PC + 5
PC + 4
INSTR (PC + 3)
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDAT
Register
EERHLT
DS41291E-page 116
PIC16F882/883/884/886/887
10.2
DS41291E-page 117
PIC16F882/883/884/886/887
FIGURE 10-2:
0 7
EEDATH
Sixteen words of
Flash are erased,
then four buffers
are transferred
to Flash
automatically
after this word
is written
EEDATA
14
14
14
EEADR<1:0> = 00
EEADR<1:0> = 10
EEADR<1:0> = 01
Buffer Register
Buffer Register
14
EEADR<1:0> = 11
Buffer Register
Buffer Register
Program Memory
FIGURE 10-3:
0 7
EEDATH
0
EEDATA
14
14
14
EEADR<2:0> = 000
Buffer Register
EEADR<2:0> = 010
EEADR<2:0> = 001
Buffer Register
Buffer Register
Sixteen words of
Flash are erased,
then eight buffers
are transferred
to Flash
automatically
after this word
is written
14
EEADR<2:0> = 111
Buffer Register
Program Memory
DS41291E-page 118
PIC16F882/883/884/886/887
An example of the complete eight-word write sequence
is shown in Example 10-4. The initial address is loaded
into the EEADRH and EEADR register pair; the eight
words of data are loaded using indirect addressing.
EXAMPLE 10-4:
LOOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
;
A valid starting address (the least significant bits = '000')
;
is loaded in ADDRH:ADDRL
;
ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL EEADRH
MOVF
ADDRH,W
; Load initial address
MOVWF
EEADRH
;
MOVF
ADDRL,W
;
MOVWF
EEADR
;
MOVF
DATAADDR,W ; Load initial data address
MOVWF
FSR
;
MOVF
INDF,W
; Load first data byte into lower
MOVWF
EEDATA
;
INCF
FSR,F
; Next byte
MOVF
INDF,W
; Load second data byte into upper
MOVWF
EEDATH
;
INCF
FSR,F
;
BANKSEL EECON1
BSF
EECON1,EEPGD ; Point to program memory
BSF
EECON1,WREN ; Enable writes
BCF
INTCON,GIE ; Disable interrupts (if using)
BTFSC
INTCON,GIE ; See AN576
GOTO
$-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Required Sequence
MOVLW
55h
; Start of required write sequence:
MOVWF
EECON2
; Write 55h
MOVLW
0AAh
;
MOVWF
EECON2
; Write 0AAh
BSF
EECON1,WR
; Set WR bit to begin write
NOP
; Required to transfer data to the buffer
NOP
; registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF
EECON1,WREN ; Disable writes
BSF
INTCON,GIE ; Enable interrupts (comment out if not using interrupts)
BANKSEL EEADR
MOVF
EEADR, W
INCF
EEADR,F
; Increment address
ANDLW
0x0F
; Indicates when sixteen words have been programmed
SUBLW
0x0F
;
0x0F = 16 words
;
0x0B = 12 words (PIC16F884/883/882 only)
;
0x07 = 8 words
;
0x03 = 4 words(PIC16F884/883/882 only)
BTFSS
STATUS,Z
; Exit on a match,
GOTO
LOOP
; Continue if more data needs to be written
DS41291E-page 119
PIC16F882/883/884/886/887
10.3
Write Verify
EXAMPLE 10-5:
WRITE VERIFY
BANKSEL EEDAT
MOVF
EEDAT, W
BANKSEL EECON1
BSF
EECON1, RD
BANKSEL
XORWF
BTFSS
GOTO
:
BCF
10.3.1
EEDAT
EEDAT, W
STATUS, Z
WRITE_ERR
STATUS, RP1
;
;EEDAT not changed
;from previous write
;
;YES, Read the
;value written
;
;
;Is data the same
;No, handle error
;Yes, continue
;Bank 0
10.4
10.5
DS41291E-page 120
PIC16F882/883/884/886/887
TABLE 10-1:
Name
EECON1
EECON2
EEADR
EEADRH
EEDAT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
EEPGD
WRERR
WREN
WR
RD
x--- x000
0--- q000
---- ----
---- ----
EEADR6
EEADR5
EEADR4
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEADR3
EEADR2
EEADR1
EEADR0
0000 0000
0000 0000
EEADRH2
EEADRH1
EEADRH0
---0 0000
---0 0000
EEDAT3
EEDAT2
EEDAT1
EEDAT0
0000 0000
0000 0000
EEADRH4(1) EEADRH3
EEDATH
EEDATH5
EEDATH4
EEDATH3
EEDATH2
EEDATH1
EEDATH0
--00 0000
--00 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULPWUIE
CCP2IE
0000 00-0
0000 00-0
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
0000 00-0
0000 00-0
Legend:
Note
1:
DS41291E-page 121
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 122
PIC16F882/883/884/886/887
11.0
CAPTURE/COMPARE/PWM
MODULES (CCP1 AND CCP2)
DS41291E-page 123
PIC16F882/883/884/886/887
11.1
Enhanced Capture/Compare/PWM
(CCP1)
TABLE 11-1:
ECCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
REGISTER 11-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-4
bit 3-0
DS41291E-page 124
PIC16F882/883/884/886/887
11.2
Capture/Compare/PWM (CCP2)
TABLE 11-2:
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
REGISTER 11-2:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
DS41291E-page 125
PIC16F882/883/884/886/887
11.3
Capture Mode
11.3.2
11.3.1
FIGURE 11-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
CCPx
pin
CCPRxH
and
Edge Detect
TMR1H
11.3.3
SOFTWARE INTERRUPT
11.3.4
CCP PRESCALER
EXAMPLE 11-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
CLRF
MOVLW
CCPRxL
MOVWF
Capture
Enable
TMR1L
CCPxCON<3:0>
System Clock (FOSC)
DS41291E-page 126
PIC16F882/883/884/886/887
11.4
Compare Mode
11.4.2
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxCON<3:0>
Mode Select
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
11.4.1
11.4.4
CCPx
Pin
11.4.3
DS41291E-page 127
PIC16F882/883/884/886/887
11.5
PWM Mode
PR2
T2CON
CCPRxL
CCPxCON
FIGURE 11-4:
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRxL:CCPxCON<5:4>
TMR2 = 0
FIGURE 11-3:
CCPRxH(2) (Slave)
CCPx
R
Comparator
TMR2
(1)
S
TRIS
Comparator
PR2
Note 1:
2:
Clear Timer2,
toggle CCPx pin and
latch duty cycle
DS41291E-page 128
PIC16F882/883/884/886/887
11.5.1
PWM PERIOD
EQUATION 11-1:
PWM PERIOD
TOSC = 1/FOSC
11.5.2
TMR2 is cleared
The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Note:
EQUATION 11-2:
PULSE WIDTH
EQUATION 11-3:
( CCPRxL:CCPxCON<5:4> )
Duty Cycle Ratio = ----------------------------------------------------------------------4 ( PR2 + 1 )
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 11-3).
DS41291E-page 129
PIC16F882/883/884/886/887
11.5.3
PWM RESOLUTION
EQUATION 11-4:
TABLE 11-3:
log [ 4 ( PR2 + 1 ) ]
Resolution = ------------------------------------------ bits
log ( 2 )
Note:
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 11-4:
PWM RESOLUTION
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
DS41291E-page 130
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
PIC16F882/883/884/886/887
11.5.4
11.5.5
11.5.6
11.5.7
4.
5.
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
6.
DS41291E-page 131
PIC16F882/883/884/886/887
11.6
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Single PWM
Half-Bridge PWM
Full-Bridge PWM, Forward mode
Full-Bridge PWM, Reverse mode
FIGURE 11-5:
DC1B<1:0>
CCP1M<3:0>
4
P1M<1:0>
2
CCPR1L
CCP1/P1A
CCP1/P1A
TRISn
CCPR1H (Slave)
P1B
R
Comparator
Output
Controller
P1B
TRISn
P1C
(1)
TMR2
Clear Timer2,
toggle PWM pin and
latch duty cycle
PR2
1:
S
P1D
Comparator
Note
P1C
TRISn
P1D
TRISn
PWM1CON
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 11-5:
ECCP Mode
P1M<1:0>
CCP1/P1A
P1B
P1C
P1D
Single
00
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Half-Bridge
10
Yes
Yes
No
No
Full-Bridge, Forward
01
Yes
Yes
Yes
Yes
Full-Bridge, Reverse
11
Yes
Yes
Yes
Yes
Note 1:
DS41291E-page 132
PIC16F882/883/884/886/887
FIGURE 11-6:
P1M<1:0>
PR2+1
Pulse
Width
Period
00
(Single Output)
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 Programmable Dead-Band Delay
Mode).
DS41291E-page 133
PIC16F882/883/884/886/887
FIGURE 11-7:
P1M<1:0>
PR2+1
Pulse
Width
Period
00
(Single Output)
P1A Modulated
P1A Modulated
10
(Half-Bridge)
Delay(1)
Delay(1)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note
1:
DS41291E-page 134
Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 Programmable Dead-Band Delay
Mode).
PIC16F882/883/884/886/887
11.6.1
HALF-BRIDGE MODE
FIGURE 11-8:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
FIGURE 11-9:
P1A
Load
FET
Driver
P1B
FET
Driver
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
DS41291E-page 135
PIC16F882/883/884/886/887
11.6.2
FULL-BRIDGE MODE
FIGURE 11-10:
FET
Driver
QC
QA
FET
Driver
P1A
Load
P1B
FET
Driver
P1C
FET
Driver
QD
QB
VP1D
DS41291E-page 136
PIC16F882/883/884/886/887
FIGURE 11-11:
Forward Mode
Period
P1A
(2)
Pulse Width
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Reverse Mode
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1)
Note 1:
2:
(1)
DS41291E-page 137
PIC16F882/883/884/886/887
11.6.2.1
FIGURE 11-12:
Signal
Period
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
(2)
P1D (Active-High)
Pulse Width
Note 1:
2:
The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is (1/Fosc) TMR2 prescale
value.
DS41291E-page 138
PIC16F882/883/884/886/887
FIGURE 11-13:
t1
Reverse Period
P1A
P1B
PW
P1C
P1D
PW
TON
External Switch C
TOFF
External Switch D
Potential
Shoot-Through Current
Note 1:
T = TOFF TON
2:
3:
TOFF is the turn off delay of power switch QD and its driver.
DS41291E-page 139
PIC16F882/883/884/886/887
11.6.3
START-UP CONSIDERATIONS
DS41291E-page 140
PIC16F882/883/884/886/887
11.6.4
FIGURE 11-14:
Drive logic 1
Drive logic 0
Tri-state (high-impedance)
ECCPAS<2:0>
PSSAC<0>
P1A_DRV
111
1
0
110
PSSAC<1>
101
100
INT
From Comparator C2
From Comparator C1
P1A
TRISx
011
010
PSSBD<0>
001
P1B_DRV
000
1
0
PRSEN
PSSBD<1>
P1B
TRISx
ECCPASE
PSSAC<0>
P1C_DRV
1
0
PSSAC<1>
P1C
TRISx
PSSBD<0>
P1D_DRV
1
0
PSSBD<1>
TRISx
P1D
DS41291E-page 141
PIC16F882/883/884/886/887
REGISTER 11-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3-2
bit 1-0
Note 1:
DS41291E-page 142
PIC16F882/883/884/886/887
FIGURE 11-15:
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
ECCPASE
Cleared by
Shutdown
Shutdown Firmware PWM
Event Occurs Event Clears
Resumes
Start of
PWM Period
11.6.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 11-16:
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
Start of
PWM Period
Shutdown
Shutdown
Event Occurs Event Clears
PWM
Resumes
DS41291E-page 143
PIC16F882/883/884/886/887
11.6.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 11-17:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See Figure 11-17 for illustration. The
lower seven bits of the associated PWM1CON register
(Register 11-4) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
FIGURE 11-18:
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
DS41291E-page 144
PIC16F882/883/884/886/887
REGISTER 11-4:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-0
DS41291E-page 145
PIC16F882/883/884/886/887
11.6.7
REGISTER 11-5:
Note:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
STRSYNC
STRD
STRC
STRB
STRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
DS41291E-page 146
PIC16F882/883/884/886/887
FIGURE 11-19:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRA
P1A Signal
CCP1M1
PORT Data
STRB
CCP1M0
PORT Data
PORT Data
PORT Data
P1B pin
TRIS
P1C pin
1
0
TRIS
STRD
CCP1M0
TRIS
STRC
CCP1M1
P1A pin
P1D pin
1
0
TRIS
Note 1:
2:
DS41291E-page 147
PIC16F882/883/884/886/887
11.6.7.1
Steering Synchronization
FIGURE 11-20:
PWM
STRn
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 11-21:
PWM
STRn
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS41291E-page 148
PIC16F882/883/884/886/887
TABLE 11-6:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP2CON
DC2B1
DC2B0
CCP2M3
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
Bit 2
CCPR1L
xxxx xxxx
xxxx xxxx
CCPR1H
xxxx xxxx
xxxx xxxx
CCPR2L
xxxx xxxx
xxxx xxxx
CCPR2H
xxxx xxxx
xxxx xxxx
CM2CON1
MC1OUT
MC2OUT
C1RSEL
C2RSEL
T1GSS
C2SYNC
0000 --10
0000 --10
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULPWUIE
CCP2IE
0000 00-0
0000 00-0
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
0000 00-0
0000 00-0
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
INTCON
T1CON
0000 0000
0000 0000
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Capture and
Compare.
TABLE 11-7:
Name
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
PSSAC0
PSSBD1
PSSBD0
0000 0000
0000 0000
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
STRD
STRC
STRB
STRA
Bit 6
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP2CON
DC2B1
DC2B0
CCP2M3
ECCPAS
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
INTCON
GIE
PEIE
T0IE
INTE
STRSYNC
PR2
Bit 5
Bit 1
Bit 7
Bit 3
Bit 2
1111 1111
1111 1111
---0 0001
---0 0001
PSTRCON
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
0000 0000
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
0000 0000
0000 0000
T2CON
TMR2
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
1111 1111
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
DS41291E-page 149
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 150
PIC16F882/883/884/886/887
12.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 12-1:
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
TX/CK pin
LSb
(8)
Pin Buffer
and Control
TRMT
SPEN
TXEN
Baud Rate Generator
FOSC
TX9
BRG16
+1
SPBRGH
SPBRG
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
DS41291E-page 151
PIC16F882/883/884/886/887
FIGURE 12-2:
CREN
RX/DT pin
Data
Recovery
FOSC
BRG16
SPBRGH
SPBRG
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
Stop
RCIDL
RSR Register
MSb
Pin Buffer
and Control
+1
OERR
(8)
LSb
0 START
RX9
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
DS41291E-page 152
PIC16F882/883/884/886/887
12.1
12.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
12.1.1.1
Note 1: When the SPEN bit is set the RX/DT I/O pin
is automatically configured as an input,
regardless of the state of the corresponding
TRIS bit and whether or not the EUSART
receiver is enabled. The RX/DT pin data
can be read via a normal PORT read but
PORT latch data output is precluded.
2: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
12.1.1.2
Transmitting Data
12.1.1.3
DS41291E-page 153
PIC16F882/883/884/886/887
12.1.1.4
TSR Status
12.1.1.6
12.1.1.5
1.
2.
3.
5.
6.
7.
FIGURE 12-3:
Write to TXREG
BRG Output
(Shift Clock)
ASYNCHRONOUS TRANSMISSION
Word 1
TX/CK
pin
Start bit
FIGURE 12-4:
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
bit 0
1 TCY
Word 1
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
DS41291E-page 154
PIC16F882/883/884/886/887
TABLE 12-1:
Name
Bit 7
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
0000 0010
TXREG
TXSTA
Legend:
TX9
TXEN
x = unknown, = unimplemented read as 0. Shaded cells are not used for Asynchronous Transmission.
DS41291E-page 155
PIC16F882/883/884/886/887
12.1.2
EUSART ASYNCHRONOUS
RECEIVER
12.1.2.1
12.1.2.2
Receiving Data
12.1.2.3
Receive Interrupts
DS41291E-page 156
PIC16F882/883/884/886/887
12.1.2.4
12.1.2.5
12.1.2.7
Address Detection
12.1.2.6
DS41291E-page 157
PIC16F882/883/884/886/887
12.1.2.8
1.
2.
3.
4.
5.
6.
7.
8.
9.
12.1.2.9
FIGURE 12-5:
Rcv Shift
Reg
Rcv Buffer Reg
RCIDL
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Start
bit
Word 1
RCREG
bit 0
Start
bit
Word 2
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41291E-page 158
PIC16F882/883/884/886/887
TABLE 12-2:
Name
Bit 7
Bit 6
BAUDCTL
ABDOVF
GIE
INTCON
PIE1
PIR1
RCREG
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
0000 0000
0000 0000
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
T0IE
INTE
ADIE
RCIE
ADIF
RCIF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TXREG
TXSTA
Legend:
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0000
0000 0000
0000 0010
0000 0010
x = unknown, = unimplemented read as 0. Shaded cells are not used for Asynchronous Reception.
DS41291E-page 159
PIC16F882/883/884/886/887
12.2
The factory calibrates the Internal Oscillator block output (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
REGISTER 12-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41291E-page 160
PIC16F882/883/884/886/887
REGISTER 12-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41291E-page 161
PIC16F882/883/884/886/887
REGISTER 12-3:
R-0
R-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS41291E-page 162
PIC16F882/883/884/886/887
12.3
EXAMPLE 12-1:
F OS C
Desired Baud Rate = --------------------------------------------------------------------64 ( [SPBRGH:SPBRG] + 1 )
16000000
-----------------------9600
= ------------------------ 1
64
= [ 25.042 ] = 25
16000000
Calculated Baud Rate = --------------------------64 ( 25 + 1 )
= 9615
TABLE 12-3:
CALCULATING BAUD
RATE ERROR
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
1
Legend:
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
TABLE 12-4:
Name
Bit 7
Bit 6
BAUDCTL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
0000 0010
Legend:
x = unknown, - = unimplemented read as 0. Shaded cells are not used for the Baud Rate Generator.
DS41291E-page 163
PIC16F882/883/884/886/887
TABLE 12-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1200
0.00
143
1202
0.16
103
2400
2404
0.16
129
2400
0.00
119
2400
0.00
71
2404
0.16
51
9600
9470
-1.36
32
9600
0.00
29
9600
0.00
17
9615
0.16
12
10417
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
10417
0.00
11
19.2k
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
103
300
0.16
51
1200
1202
0.16
51
1200
0.00
47
1202
0.16
25
1202
0.16
12
2400
2404
0.16
25
2400
0.00
23
2404
0.16
12
9600
9600
0.00
10417
10417
0.00
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
2400
2404
0.16
207
9600
9615
0.16
129
9600
0.00
119
9600
0.00
71
9615
0.16
51
10417
10417
0.00
119
10378
-0.37
110
10473
0.53
65
10417
0.00
47
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
19231
0.16
25
57.6k
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
55556
-3.55
115.2k
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
DS41291E-page 164
PIC16F882/883/884/886/887
TABLE 12-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
1202
0.16
103
300
1202
0.16
0.16
207
51
2400
2404
0.16
103
2400
0.00
95
2404
0.16
51
2404
0.16
25
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9615
0.16
25
9600
0.00
23
9615
0.16
12
10417
10417
0.00
23
10473
0.53
21
10417
0.00
11
10417
0.00
19.2k
19.23k
0.16
12
19.2k
0.00
11
57.6k
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
1666
300
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
299.9
-0.02
1200
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
1199
-0.08
416
2400
2399
-0.03
520
2400
0.00
479
2400
0.00
287
2404
0.16
207
51
9600
9615
0.16
129
9600
0.00
119
9600
0.00
71
9615
0.16
10417
10417
0.00
119
10378
-0.37
110
10473
0.53
65
10417
0.00
47
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
19.23k
0.16
25
57.6k
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
55556
-3.55
115.2k
113.636
-1.36
10
115.2k
0.00
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.1
0.04
832
300.0
0.00
767
299.8
-0.108
416
300.5
0.16
207
1200
1202
0.16
207
1200
0.00
191
1202
0.16
103
1202
0.16
51
2400
2404
0.16
103
2400
0.00
95
2404
0.16
51
2404
0.16
25
9600
9615
0.16
25
9600
0.00
23
9615
0.16
12
10417
10417
0.00
23
10473
0.53
21
10417
0.00
11
10417
0.00
19.2k
19.23k
0.16
12
19.20k
0.00
11
57.6k
57.60k
0.00
115.2k
115.2k
0.00
DS41291E-page 165
PIC16F882/883/884/886/887
TABLE 12-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
300.0
1200
0.00
-0.02
6666
1666
2400
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
2401
0.04
832
9600
9597
-0.03
520
9600
0.00
479
9600
0.00
287
9615
0.16
207
10417
10417
0.00
479
10425
0.08
441
10433
0.16
264
10417
191
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
19.2k
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
19.23k
0.16
103
57.6k
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
57.14k
-0.79
34
115.2k
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
117.6k
2.12
16
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
832
300
300.0
0.01
3332
300.0
0.00
3071
299.9
-0.02
1666
300.1
0.04
1200
1200
0.04
832
1200
0.00
767
1199
-0.08
416
1202
0.16
207
2400
2398
0.08
416
2400
0.00
383
2404
0.16
207
2404
0.16
103
9600
9615
0.16
103
9600
0.00
95
9615
0.16
51
9615
0.16
25
10417
10417
0.00
95
10473
0.53
87
10417
0.00
47
10417
0.00
23
19.2k
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
25
19.23k
0.16
12
57.6k
58.82k
2.12
16
57.60k
0.00
15
55.56k
-3.55
115.2k
111.1k
-3.55
115.2k
0.00
DS41291E-page 166
PIC16F882/883/884/886/887
12.3.1
AUTO-BAUD DETECT
TABLE 12-6:
FIGURE 12-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
Note:
BRG Value
RX pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRG
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode
DS41291E-page 167
PIC16F882/883/884/886/887
12.3.2
AUTO-WAKE-UP ON BREAK
12.3.2.1
Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
FIGURE 12-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
WUE bit
RX/DT Line
RCIF
Note 1:
DS41291E-page 168
PIC16F882/883/884/886/887
FIGURE 12-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
12.3.3
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
12.3.3.1
Sleep Ends
12.3.4
DS41291E-page 169
PIC16F882/883/884/886/887
FIGURE 12-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
DS41291E-page 170
Auto Cleared
PIC16F882/883/884/886/887
12.4
12.4.1
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
12.4.1.1
Master Clock
12.4.1.2
Clock Polarity
12.4.1.3
12.4.1.4
1.
2.
3.
4.
5.
6.
7.
8.
DS41291E-page 171
PIC16F882/883/884/886/887
FIGURE 12-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 12-11:
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 12-7:
Name
Bit 7
Bit 6
BAUDCTL
ABDOVF
GIE
PIE1
PIR1
INTCON
RCREG
RCSTA
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
0000 0000
0000 0000
RX9D
0000 000x
0000 000x
0000 0000
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
T0IE
INTE
ADIE
RCIE
ADIF
RCIF
RX9
SREN
CREN
ADDEN
FERR
OERR
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
0000 0010
TXREG
TXSTA
Legend:
TX9
TXEN
x = unknown, = unimplemented read as 0. Shaded cells are not used for Synchronous Master Transmission.
DS41291E-page 172
PIC16F882/883/884/886/887
12.4.1.5
12.4.1.6
Slave Clock
12.4.1.7
12.4.1.8
12.4.1.9
1.
DS41291E-page 173
PIC16F882/883/884/886/887
FIGURE 12-12:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 12-8:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
BAUDCTL
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
INTCON
PIE1
PIR1
RCREG
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
OERR
0000 0000
RX9D
0000 000x
0000 000x
RCSTA
SPEN
RX9
SREN
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
0000 0010
TXREG
TXSTA
Legend:
CREN
ADDEN
0000 0000
TX9
TXEN
x = unknown, = unimplemented read as 0. Shaded cells are not used for Synchronous Master Reception.
DS41291E-page 174
PIC16F882/883/884/886/887
12.4.2
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
2.
3.
4.
12.4.2.1
5.
12.4.2.2
1.
2.
3.
4.
5.
6.
7.
TABLE 12-9:
Bit 7
Bit 6
BAUDCTL
ABDOVF
GIE
PIE1
PIR1
RCREG
Name
INTCON
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
0000 0000
0000 0000
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
T0IE
INTE
ADIE
RCIE
ADIF
RCIF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
0000 0010
0000 0010
TRISC
TXREG
TXSTA
Legend:
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
x = unknown, = unimplemented read as 0. Shaded cells are not used for Synchronous Slave Transmission.
DS41291E-page 175
PIC16F882/883/884/886/887
12.4.2.3
12.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
Bit 7
Bit 6
BAUDCTL
ABDOVF
GIE
PIE1
PIR1
INTCON
RCREG
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
T0IE
INTE
ADIE
RCIE
ADIF
RCIF
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
0000 0000
0000 0000
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TRISC
TXREG
TXSTA
Legend:
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0000
0000 0000
0000 0010
0000 0010
x = unknown, = unimplemented read as 0. Shaded cells are not used for Synchronous Slave Reception.
DS41291E-page 176
PIC16F882/883/884/886/887
12.5
12.5.1
12.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
DS41291E-page 177
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 178
PIC16F882/883/884/886/887
13.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
13.1
13.2
Control Registers
DS41291E-page 179
PIC16F882/883/884/886/887
REGISTER 13-1:
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
x = Bit is unknown
bit 6
bit 5
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
DS41291E-page 180
PIC16F882/883/884/886/887
REGISTER 13-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
DS41291E-page 181
PIC16F882/883/884/886/887
REGISTER 13-3:
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS41291E-page 182
PIC16F882/883/884/886/887
13.3
SPI Mode
FIGURE 13-1:
Read
Write
SSPBUF Reg
SSPSR Reg
SDI
13.3.1
SDO
OPERATION
Shift
Clock
bit 0
SS Control
Enable
SS
Edge
Select
2
Clock Select
SSPM<3:0>
SMP:CKE 4
TMR2 Output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
SCK
DS41291E-page 183
PIC16F882/883/884/886/887
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
buffer full bit BF of the SSPSTAT register indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP Interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 13-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF
register. Additionally, the MSSP STATUS register
(SSPSTAT register) indicates the various status
conditions.
EXAMPLE 13-1:
13.3.2
MOVWF RXDATA
MOVF TXDATA, W
MOVWF SSPBUF
DS41291E-page 184
PIC16F882/883/884/886/887
13.3.3
MASTER MODE
The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. This, then,
would give waveforms for SPI communication as
shown in Figure 13-2, Figure 13-4 and Figure 13-5,
where the MSb is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
FIGURE 13-2:
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
Next Q4 Cycle
after Q2
DS41291E-page 185
PIC16F882/883/884/886/887
13.3.4
SLAVE MODE
13.3.5
SLAVE SELECT
SYNCHRONIZATION
FIGURE 13-3:
the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set (SSPSTAT register), then the SS pin
control must be enabled.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to
a high level, or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
SSPSR to
SSPBUF
DS41291E-page 186
Next Q4 Cycle
after Q2
PIC16F882/883/884/886/887
FIGURE 13-4:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
bit 7
SDI
(SMP = 0)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
FIGURE 13-5:
SS
Required
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
SSPSR to
SSPBUF
Next Q4 Cycle
after Q2
DS41291E-page 187
PIC16F882/883/884/886/887
13.3.6
SLEEP OPERATION
13.3.8
TABLE 13-1:
13.3.7
EFFECTS OF A RESET
Name
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
There is also a SMP bit that controls when the data will
be sampled.
TABLE 13-2:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
GIE/GIEH
PEIE/GIEL
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
0000 0000
xxxx xxxx
uuuu uuuu
INTCON
SSPBUF
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
0000 0000
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
Note 1:
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the MSSP in SPI mode.
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and
read 0.
DS41291E-page 188
PIC16F882/883/884/886/887
13.4
FIGURE 13-6:
Write
SSPBUF Reg
RC3/SCK/SCL
SSPSR Reg
MSb
LSb
Match Detect
13.4.1
Addr Match
SSPMSK Reg
b)
SSPADD Reg
Start and
Stop bit Detect
Note:
SLAVE MODE
Shift
Clock
RC4/
SDI/
SDA
Set, Reset
S, P bits
(SSPSTAT Reg)
DS41291E-page 189
PIC16F882/883/884/886/887
13.4.1.1
Addressing
2.
3.
4.
5.
6.
7.
8.
9.
13.4.1.2
13.4.1.3
Transmission
Reception
DS41291E-page 190
PIC16F882/883/884/886/887
I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 13-7:
SDA
SCL
SSPIF
P
Bus Master
Terminates
Transfer
BF
Cleared in software
SSPBUF register is read
SSPOV
Bit SSPOV is set because the SSPBUF register is still full
ACK is not sent
FIGURE 13-8:
Receiving Address
A7
SDA
SCL
A6
1
2
Data in
Sampled
R/W = 1
A5
A4
A3
A2
A1
ACK
R/W = 0
Not ACK
Transmitting Data
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
SSPIF
BF
Cleared in software
SSPBUF is written in software
CKP
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS41291E-page 191
PIC16F882/883/884/886/887
13.4.2
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT register). If the general call address
is sampled when the GCEN bit is set, and while the
slave is configured in 10-bit address mode, then the
second half of the address is not necessary. The UA bit
will not be set, and the slave will begin receiving data
after the Acknowledge (Figure 13-9).
FIGURE 13-9:
SDA
SCL
S
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SSPIF
BF
Cleared in software
SSPBUF is read
SSPOV
GCEN
DS41291E-page 192
PIC16F882/883/884/886/887
MASTER MODE
13.4.4
In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware.
4.
5.
6.
Start condition
Stop condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start condition
FIGURE 13-10:
3.
Note:
SSPM<3:0>
SSPADD<6:0>
Write
SSPBUF
SDA
Baud
Rate
Generator
Shift
Clock
SDA In
SCL In
Bus Collision
MSb
LSb
Clock Cntl
SCL
Receive Enable
SSPSR
13.4.3
DS41291E-page 193
PIC16F882/883/884/886/887
13.4.4.1
DS41291E-page 194
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
PIC16F882/883/884/886/887
13.4.5
FIGURE 13-11:
SSPM<3:0>
Reload
SCL
Control
CLKOUT
FIGURE 13-12:
SSPADD<6:0>
Reload
FOSC/4
SDA
DX
DX-1
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
DS41291E-page 195
PIC16F882/883/884/886/887
13.4.6
13.4.6.1
To initiate a Start condition, the user sets the Start Condition Enable bit SEN of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low, while SCL is high, is the
Start condition, and causes the S bit of the SSPSTAT
register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the Baud Rate Generator
times out (TBRG), the SEN bit of the SSPCON2 register
will be automatically cleared by hardware, the Baud
Rate Generator is suspended leaving the SDA line held
low and the Start condition is complete.
Note:
Note:
FIGURE 13-13:
TBRG
SDA
2nd Bit
TBRG
SCL
TBRG
S
DS41291E-page 196
PIC16F882/883/884/886/887
13.4.7
13.4.7.1
FIGURE 13-14:
Set S (SSPSTAT<3>)
SDA = 1,
SCL = 1
TBRG
TBRG
SDA
Falling edge of ninth clock
End of Xmit
SCL
DS41291E-page 197
PIC16F882/883/884/886/887
13.4.8
13.4.8.1
BF Status Flag
13.4.8.3
13.4.9
13.4.9.1
BF Status Flag
13.4.9.2
13.4.9.3
13.4.8.2
DS41291E-page 198
PEN
SEN
BF
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared in software
SSPBUF written
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared in software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 13-15:
SEN = 0
PIC16F882/883/884/886/887
DS41291E-page 199
DS41291E-page 200
ACKEN
SSPOV
BF
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
4
5
Cleared in software
7
8
9
2
D0
ACK
5
6
Cleared in software
ACK
Bus Master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
D7 D6 D5 D4 D3 D2 D1
D0
RCEN cleared
automatically
RCEN = 1 start
next receive
Cleared in software
Cleared in software
RCEN cleared
automatically
FIGURE 13-16:
SEN = 0
Write to SSPBUF occurs here
Start XMIT
ACK from Slave
Transmit Address to Slave R/W = 1
A7 A6 A5 A4 A3 A2 A1
ACK
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16F882/883/884/886/887
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC16F882/883/884/886/887
13.4.10
13.4.11
13.4.10.1
13.4.11.1
FIGURE 13-17:
TBRG
TBRG
SDA
D0
SCL
ACK
SSPIF
Set SSPIF at the end
of receive
Note: TBRG = one Baud Rate Generator period.
Cleared in
software
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
DS41291E-page 201
PIC16F882/883/884/886/887
FIGURE 13-18:
Write to SSPCON2
Set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
13.4.12
CLOCK ARBITRATION
13.4.13
FIGURE 13-19:
SLEEP OPERATION
13.4.14
EFFECT OF A RESET
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SCL line sampled once every machine cycle (TOSC*4),
Hold off BRG until SCL is sampled high
SDA
TBRG
DS41291E-page 202
TBRG
TBRG
PIC16F882/883/884/886/887
13.4.15
MULTI-MASTER MODE
Address transfer
Data transfer
A Start condition
A Repeated Start condition
An Acknowledge condition
13.4.16
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
FIGURE 13-20:
Sample SDA,
While SCL is high, data doesnt
match what is driven by the master,
Bus collision has occurred
SDA
SCL
BCLIF
DS41291E-page 203
PIC16F882/883/884/886/887
13.4.16.1
b)
then:
the Start condition is aborted,
and the BCLIF flag is set,
and the MSSP module is reset to its Idle state
(Figure 13-21).
The Start condition begins with the SDA and SCL pins
de-asserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
FIGURE 13-21:
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1.
SEN
BCLIF
SSPIF
SSPIF and BCLIF are
cleared in software.
DS41291E-page 204
PIC16F882/883/884/886/887
FIGURE 13-22:
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL =0 before BRG time-out,
Bus collision occurs, set BCLIF
BCLIF
Interrupt cleared
in software
SSPIF
FIGURE 13-23:
SDA
Set SSPIF
TBRG
SCL
S
SCL pulled low after BRG
time-out
SEN
BCLIF
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
Interrupts cleared
in software
DS41291E-page 205
PIC16F882/883/884/886/887
13.4.16.2
FIGURE 13-24:
If at the end of the BRG time-out, both SCL and SDA are
still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
SDA
SCL
Sample SDA when SCL goes high,
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
Cleared in software
0
SSPIF
FIGURE 13-25:
TBRG
SDA
SCL
BCLIF
RSEN
S
SSPIF
DS41291E-page 206
PIC16F882/883/884/886/887
13.4.16.3
b)
FIGURE 13-26:
TBRG
SDA sampled
low after TBRG,
set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
SSPIF
FIGURE 13-27:
TBRG
TBRG
SDA
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
DS41291E-page 207
PIC16F882/883/884/886/887
13.4.17
REGISTER 13-4:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed
through the SSPMSK register.
2: In all other SSP modes, this bit has no effect.
DS41291E-page 208
PIC16F882/883/884/886/887
14.0
The PIC16F882/883/884/886/887 have a host of features intended to maximize system reliability, minimize
cost through elimination of external components, provide power-saving features and offer code protection.
These features are:
Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Oscillator selection
Sleep
Code protection
ID Locations
In-Circuit Serial Programming
Low-voltage In-Circuit Serial Programming
The PIC16F882/883/884/886/887 have two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 64 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can use the
Power-up Timer to provide at least a 64 ms Reset. With
these three functions-on-chip, most applications need
no external Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through:
External Reset
Watchdog Timer Wake-up
An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 14-3).
DS41291E-page 209
PIC16F882/883/884/886/887
14.1
Configuration Bits
REGISTER 14-1:
Note:
DEBUG
LVP
FCMEN
IESO
BOREN1
BOREN0
bit 15
bit 8
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
bit 7
bit 0
bit 15-14
Unimplemented: Read as 1
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note
FOSC0
1:
2:
3:
4:
DS41291E-page 210
PIC16F882/883/884/886/887
REGISTER 14-2:
WRT1
WRT0
BOR4V
bit 15
bit 8
bit 7
bit 0
bit 15-11
Unimplemented: Read as 1
bit 10-9
bit 8
bit 7-0
Unimplemented: Read as 1
DS41291E-page 211
PIC16F882/883/884/886/887
14.2
Reset
The
PIC16F882/883/884/886/887
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
differentiates
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
FIGURE 14-1:
MCLR/VPP pin
Sleep
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
SBOREN
OST/PWRT
OST
Chip_Reset
OSC1/
CLKI pin
PWRT
LFINTOSC
Enable PWRT
Enable OST
Note
1:
DS41291E-page 212
PIC16F882/883/884/886/887
14.2.1
FIGURE 14-2:
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
Section 17.0 Electrical Specifications for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 14.2.4
Brown-out Reset (BOR)).
Note:
VDD
PIC16F886
R1
1 k (or greater)
MCLR
RECOMMENDED MCLR
CIRCUIT
C1
0.1 F
(optional, not critical)
14.2.3
VDD variation
Temperature variation
Process variation
14.2.2
MCLR
DS41291E-page 213
PIC16F882/883/884/886/887
14.2.4
FIGURE 14-3:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
< 64 ms
64 ms(1)
VDD
Internal
Reset
Note 1:
VBOR
64 ms(1)
DS41291E-page 214
PIC16F882/883/884/886/887
14.2.5
TIME-OUT SEQUENCE
14.2.6
TABLE 14-1:
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
TPWRT +
1024 TOSC
1024 TOSC
TPWRT +
1024 TOSC
1024 TOSC
1024 TOSC
LP, T1OSCIN = 1
TPWRT
TPWRT
TPWRT
TPWRT
Oscillator Configuration
XT, HS, LP
TABLE 14-2:
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
TABLE 14-3:
Name
PCON
STATUS
Legend:
Note 1:
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
SBOREN
POR
BOR
--01 --qq
--0u --uu
TO
PD
DC
0001 1xxx
000q quuu
Bit 6
Bit 5
Bit 4
ULPWUE
IRP
RP1
RPO
u = unchanged, x = unknown, = unimplemented bit, reads as 0, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41291E-page 215
PIC16F882/883/884/886/887
FIGURE 14-4:
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 14-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 14-6:
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS41291E-page 216
PIC16F882/883/884/886/887
TABLE 14-4:
Register
W
INDF
TMR0
Address
Power-on
Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
xxxx xxxx
uuuu uuuu
uuuu uuuu
00h/80h/10
0h/180h
xxxx xxxx
xxxx xxxx
uuuu uuuu
01h/101h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h/10
2h/182h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h/10
3h/183h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h/10
4h/184h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
xxxx xxxx
0000 0000
uuuu uuuu
PORTB
06h/106h
xxxx xxxx
0000 0000
uuuu uuuu
PORTC
07h
xxxx xxxx
0000 0000
uuuu uuuu
PORTD
08h
xxxx xxxx
0000 0000
uuuu uuuu
PORTE
09h
---- xxxx
---- 0000
---- uuuu
PCLATH
0Ah/8Ah/10
Ah/18Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh/10
Bh/18Bh
0000 000x
0000 000u
uuuu uuuu(2)
PIR1
0Ch
0000 0000
0000 0000
uuuu uuuu(2)
PIR2
0Dh
0000 0000
0000 0000
uuuu uuuu(2)
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 0000
uuuu uuuu
-uuu uuuu
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2CON
12h
-000 0000
-000 0000
-uuu uuuu
SSPBUF
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
14h
0000 0000
0000 0000
uuuu uuuu
CCPR1L
15h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
16h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
17h
0000 0000
0000 0000
uuuu uuuu
RCSTA
18h
0000 000x
0000 0000
uuuu uuuu
TXREG
19h
0000 0000
0000 0000
uuuu uuuu
RCREG
1Ah
0000 0000
0000 0000
uuuu uuuu
1Bh
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
Legend:
Note 1:
2:
3:
4:
5:
6:
DS41291E-page 217
PIC16F882/883/884/886/887
TABLE 14-4:
Address
Power-on
Reset
MCLR Reset
WDT Reset (Continued)
Brown-out Reset(1)
CCPR2H
1Ch
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
1Dh
--00 0000
--00 0000
--uu uuuu
ADRESH
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
00-0 0000
00-0 0000
uu-u uuuu
Register
OPTION_REG
81h/181h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
1111 1111
1111 1111
uuuu uuuu
TRISB
86h/186h
1111 1111
1111 1111
uuuu uuuu
TRISC
87h
1111 1111
1111 1111
uuuu uuuu
TRISD
88h
1111 1111
1111 1111
uuuu uuuu
TRISE
89h
---- 1111
---- 1111
---- uuuu
PIE1
8Ch
0000 0000
0000 0000
uuuu uuuu
PIE2
8Dh
0000 0000
0000 0000
uuuu uuuu
(1, 5)
PCON
8Eh
--01 --0x
--0u --uu
OSCCON
8Fh
-110 q000
-110 q000
OSCTUNE
90h
---0 0000
---u uuuu
---u uuuu
SSPCON2
91h
0000 0000
0000 0000
uuuu uuuu
PR2
92h
1111 1111
1111 1111
1111 1111
SSPADD(6)
93h
0000 0000
0000 0000
uuuu uuuu
SSPMSK(6)
93h
1111 1111
1111 1111
1111 1111
SSPSTAT
94h
0000 0000
0000 0000
uuuu uuuu
WPUB
95h
1111 1111
1111 1111
uuuu uuuu
IOCB
96h
0000 0000
0000 0000
uuuu uuuu
VRCON
97h
0000 0000
0000 0000
uuuu uuuu
TXSTA
98h
0000 -010
0000 -010
uuuu -uuu
SPBRG
99h
0000 0000
0000 0000
uuuu uuuu
SPBRGH
9Ah
0000 0000
0000 0000
uuuu uuuu
PWM1CON
9Bh
0000 0000
0000 0000
uuuu uuuu
ECCPAS
9Ch
0000 0000
0000 0000
uuuu uuuu
PSTRCON
9Dh
---0 0001
---0 0001
---u uuuu
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
9Fh
0-00 ----
0-00 ----
u-uu ----
WDTCON
105h
---0 1000
---0 1000
---u uuuu
CM1CON0
107h
0000 0-00
0000 0-00
uuuu u-uu
CM2CON0
108h
0000 0-00
0000 0-00
uuuu u-uu
Legend:
Note 1:
2:
3:
4:
5:
6:
--uu --uu
-uuu uuuu
DS41291E-page 218
PIC16F882/883/884/886/887
TABLE 14-4:
Address
Power-on
Reset
MCLR Reset
WDT Reset (Continued)
Brown-out Reset(1)
CM2CON1
109h
0000 0--0
0000 0--0
uuuu u--u
EEDAT
10Ch
0000 0000
0000 0000
uuuu uuuu
EEADR
10Dh
0000 0000
0000 0000
uuuu uuuu
EEDATH
10Eh
--00 0000
--00 0000
--uu uuuu
EEADRH
10Fh
---0 0000
---0 0000
---u uuuu
SRCON
185h
0000 00-0
0000 00-0
uuuu uu-u
BAUDCTL
187h
01-0 0-00
01-0 0-00
uu-u u-uu
ANSEL
188h
1111 1111
1111 1111
uuuu uuuu
ANSELH
189h
1111 1111
1111 1111
uuuu uuuu
EECON1
18Ch
---- x000
---- q000
---- uuuu
18Dh
---- ----
---- ----
---- ----
Register
EECON2
Legend:
Note 1:
2:
3:
4:
5:
6:
TABLE 14-5:
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
--01 --0x
000h
000u uuuu
--0u --uu
000h
0001 0uuu
--0u --uu
000h
0000 uuuu
--0u --uu
PC + 1
uuu0 0uuu
--uu --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
000h
0001 1uuu
--01 --u0
PC + 1(1)
uuu1 0uuu
--uu --uu
DS41291E-page 219
PIC16F882/883/884/886/887
14.3
Interrupts
The PIC16F882/883/884/886/887
interrupt sources:
has
multiple
A/D Interrupt
EUSART Receive and Transmit Interrupts
Timer1 Overflow Interrupt
Synchronous Serial Port (SSP) Interrupt
Enhanced CCP1 Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
DS41291E-page 220
14.3.1
RB0/INT INTERRUPT
PIC16F882/883/884/886/887
14.3.2
TIMER0 INTERRUPT
14.3.3
FIGURE 14-7:
PORTB INTERRUPT
INTERRUPT LOGIC
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
BCLIF
BCLIE
IOC-RB3
IOCB3
SSPIF
SSPIE
IOC-RB4
IOCB4
TXIF
TXIE
IOC-RB5
IOCB5
RCIF
RCIE
IOC-RB6
IOCB6
TMR2IF
TMR2IE
IOC-RB7
IOCB7
TMR1IF
TMR1IE
C1IF
C1IE
C2IF
C2IE
Interrupt to CPU
PEIE
GIE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
CCP1IF
CCP1IE
Note 1:
CCP2IF
CCP2IE
ULPWUIF
ULPWUIE
DS41291E-page 221
PIC16F882/883/884/886/887
FIGURE 14-8:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON<1>)
(5)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
INTCON
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Dummy Cycle
Inst (PC)
0005h
2:
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 17.0 Electrical Specifications.
5:
TABLE 14-6:
Name
Inst (PC + 1)
Inst (PC 1)
0004h
PC + 1
PC + 1
Inst (PC)
Instruction
Executed
Note 1:
PC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULPWUIE
CCP2IE
0000 00-0
0000 00-0
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
CCP2IF
0000 00-0
0000 00-0
PIR2
Legend:
DS41291E-page 222
PIC16F882/883/884/886/887
14.4
EXAMPLE 14-1:
MOVWF
SWAPF
W_TEMP
STATUS,W
MOVWF STATUS_TEMP
:
:(ISR)
:
SWAPF STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy W to TEMP
;Swap status to
;Swaps are used
;Save status to
register
be saved into W
because they do not affect the status bits
bank zero STATUS_TEMP register
DS41291E-page 223
PIC16F882/883/884/886/887
14.5
14.5.2
14.5.1
WDT OSCILLATOR
WDT CONTROL
FIGURE 14-9:
0
Prescaler(1)
8
PSA
31 kHz
LFINTOSC Clock
PS<2:0>
WDTPS<3:0>
0
1
PSA
Note
1:
TABLE 14-7:
This is the shared Timer0/WDT prescaler. See Section 5.1.3 Software Programmable Prescaler for more information.
WDT STATUS
Conditions
WDTE = 0
WDT
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
DS41291E-page 224
PIC16F882/883/884/886/887
REGISTER 14-3:
U-0
U-0
U-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-1
bit 0
x = Bit is unknown
Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
TABLE 14-8:
Name
Bit 7
CONFIG1(1)
OPTION_REG
WDTCON
Legend:
Note 1:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
---0 1000
DS41291E-page 225
PIC16F882/883/884/886/887
14.6
14.6.1
The first event will cause a device Reset. The two latter
events are considered a continuation of program execution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
8.
14.6.2
DS41291E-page 226
PIC16F882/883/884/886/887
FIGURE 14-10:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
14.7
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC 1)
PC + 1
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
14.8
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
2:
TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3:
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4:
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
Code Protection
ID Locations
14.9
PC + 2
1:
PC + 2
DS41291E-page 227
PIC16F882/883/884/886/887
FIGURE 14-11:
TYPICAL IN-CIRCUIT
SERIAL
PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC16F882/883/
884/886/887
+5V
VDD
0V
VSS
VPP
RE3/MCLR/VPP
CLK
RB6
Data I/O
RB7
To Normal
Connections
*
DS41291E-page 228
PIC16F882/883/884/886/887
For more information, see Using MPLAB ICD 2
(DS51265), available on Microchips web site
(www.microchip.com).
TABLE 14-9:
Pin (PDIP)
PIC16F884/887
PIC16F882/883/
886
Name
Type
Pull-up
40
28
ICDDATA
TTL
39
27
ICDCLK
ST
MCLR/VPP
HV
11,32
20
VDD
12,31
8,19
VSS
Description
Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage
DS41291E-page 229
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 230
PIC16F882/883/884/886/887
15.0
TABLE 15-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
Register file address (0x00 to 0x7F)
Byte-oriented operations
Bit-oriented operations
Literal and control operations
PC
Program Counter
TO
Time-out bit
Carry bit
C
DC
Z
PD
Power-down bit
FIGURE 15-1:
Read-Modify-Write Operations
13
15.1
OPCODE
0
k (literal)
11
OPCODE
10
0
k (literal)
DS41291E-page 231
PIC16F882/883/884/886/887
TABLE 15-2:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
01
01
01
01
1, 2
1, 2
3
3
2:
3:
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41291E-page 232
PIC16F882/883/884/886/887
15.2
Instruction Descriptions
ADDLW
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 127
0b7
Operation:
0 (f<b>)
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
Operation:
1 (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Description:
ANDLW
BTFSC
Syntax:
[ label ] ANDLW
Syntax:
Operands:
0 k 255
Operands:
Operation:
0 f 127
0b7
Status Affected:
Operation:
skip if (f<b>) = 0
Description:
Status Affected:
None
Description:
ANDWF
AND W with f
f,d
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d [0,1]
Operation:
f,d
Status Affected:
Description:
f,b
DS41291E-page 233
PIC16F882/883/884/886/887
BTFSS
CLRWDT
Syntax:
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
0b<7
Operands:
None
Operation:
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
TO, PD
Description:
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
Syntax:
[ label ] COMF
Operands:
0 k 2047
Operands:
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
0 f 127
d [0,1]
f,d
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
Decrement register f. If d is 0,
the result is stored in the W
register. If d is 1, the result is
stored back in register f.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
DS41291E-page 234
PIC16F882/883/884/886/887
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
GOTO k
INCF f,d
INCFSZ f,d
IORWF
f,d
DS41291E-page 235
PIC16F882/883/884/886/887
MOVWF
Move W to f
Syntax:
[ label ]
MOVF
Move f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
Operation:
(W) (f)
Operation:
(f) (dest)
Status Affected:
None
Status Affected:
Description:
Description:
Words:
Cycles:
Words:
Cycles:
Example:
MOVF f,d
MOVF
Example:
MOVW
F
MOVWF
OPTION
Before Instruction
OPTION =
W
=
After Instruction
OPTION =
W
=
FSR, 0
0xFF
0x4F
0x4F
0x4F
After Instruction
W =
value in FSR
register
Z = 1
MOVLW
Move literal to W
NOP
No Operation
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W)
Operation:
No operation
Status Affected:
None
Status Affected:
None
Description:
Description:
No operation.
Words:
Cycles:
Words:
Cycles:
Example:
MOVLW k
Example:
MOVLW
NOP
0x5A
After Instruction
W =
DS41291E-page 236
NOP
0x5A
PIC16F882/883/884/886/887
RETFIE
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 k 255
Operation:
TOS PC,
1 GIE
Operation:
k (W);
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TABLE
TOS
1
RETLW k
;W now has
;table value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
RETURN
Syntax:
[ label ]
Operands:
None
Operation:
TOS PC
Status Affected:
None
Description:
RETURN
DS41291E-page 237
PIC16F882/883/884/886/887
RLF
SLEEP
Syntax:
[ label ]
Syntax:
[ label ] SLEEP
Operands:
0 f 127
d [0,1]
Operands:
None
Operation:
Operation:
Status Affected:
Description:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
RLF
f,d
Words:
Cycles:
Example:
Status Affected:
TO, PD
Description:
Register f
RLF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
RRF
SUBLW
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
0 k 255
k - (W) (W)
RRF f,d
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
Description:
Description:
DS41291E-page 238
Register f
W>k
C=1
Wk
DC = 0
DC = 1
W<3:0> k<3:0>
PIC16F882/883/884/886/887
SUBWF
Subtract W from f
XORWF
Exclusive OR W with f
Syntax:
Syntax:
[ label ] XORWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
Description:
Description:
W>f
C=1
Wf
DC = 0
DC = 1
W<3:0> f<3:0>
SWAPF
Swap Nibbles in f
Syntax:
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected:
None
Description:
XORLW
f,d
Syntax:
[ label ] XORLW k
Operands:
0 k 255
Operation:
Status Affected:
Description:
DS41291E-page 239
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 240
PIC16F882/883/884/886/887
16.0
DEVELOPMENT SUPPORT
16.1
DS41291E-page 241
PIC16F882/883/884/886/887
16.2
MPASM Assembler
16.3
16.4
16.5
16.6
DS41291E-page 242
PIC16F882/883/884/886/887
16.7
16.8
16.9
DS41291E-page 243
PIC16F882/883/884/886/887
16.11 PICSTART Plus Development
Programmer
DS41291E-page 244
PIC16F882/883/884/886/887
17.0
ELECTRICAL SPECIFICATIONS
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
PORTD and PORTE are implemented on PIC16F886/PIC16F887 only.
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS41291E-page 245
PIC16F882/883/884/886/887
FIGURE 17-1:
5.5
5.0
VDD (V)
4.5
4.0
3.5
3.0
2.5
2.0
0
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2:
125
5%
Temperature (C)
85
2%
60
1%
25
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 246
PIC16F882/883/884/886/887
17.1
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Conditions
VDD
Supply Voltage
2.0
2.0
3.0
4.5
5.5
5.5
5.5
5.5
V
V
V
V
D002*
VDR
1.5
D003
VPOR
VSS
D004*
SVDD
0.05
D001
D001C
D001D
DS41291E-page 247
PIC16F882/883/884/886/887
17.2
DC CHARACTERISTICS
Param
No.
D010
Device Characteristics
Supply Current (IDD)
D011*
D012
D013*
D014
D015
D016*
D017
D018
D019
(1, 2)
Conditions
Min.
Typ
Max.
Units
13
19
2.0
22
30
3.0
33
60
5.0
180
250
2.0
290
400
3.0
VDD
490
650
5.0
280
380
2.0
480
670
3.0
0.9
1.4
mA
5.0
170
295
2.0
280
480
3.0
470
690
5.0
290
450
2.0
490
720
3.0
0.85
1.3
mA
5.0
20
2.0
16
40
3.0
31
65
5.0
416
520
2.0
640
840
3.0
1.13
1.6
mA
5.0
0.65
0.9
mA
2.0
1.01
1.3
mA
3.0
1.86
2.3
mA
5.0
340
580
2.0
550
900
3.0
0.92
1.4
mA
5.0
3.8
4.7
mA
4.5
4.0
4.8
mA
5.0
Note
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 4 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 4 MHz
EXTRC mode(3)
FOSC = 20 MHz
HS Oscillator mode
DS41291E-page 248
PIC16F882/883/884/886/887
17.3
DC CHARACTERISTICS
Param
No.
D020
Device Characteristics
Power-down Base
Current(IPD)(2)
D021
Typ
Max.
Units
0.05
1.2
0.15
1.5
Conditions
VDD
Note
2.0
3.0
0.35
1.8
5.0
150
500
nA
3.0
-40C TA +25C
1.0
2.2
2.0
WDT Current(1)
2.0
4.0
3.0
3.0
7.0
5.0
D022
42
60
3.0
85
122
5.0
D023
32
45
2.0
D024
D025*
D026
60
78
3.0
120
160
5.0
30
36
2.0
45
55
3.0
75
95
5.0
39
47
2.0
59
72
3.0
98
124
5.0
2.0
5.0
2.0
2.5
5.5
3.0
BOR Current(1)
Comparator Current(1), both
comparators enabled
CVREF Current(1) (high range)
3.0
7.0
5.0
D027
0.30
1.6
3.0
0.36
1.9
5.0
D028
90
125
3.0
125
162
5.0
DS41291E-page 249
PIC16F882/883/884/886/887
17.4
DC CHARACTERISTICS
Param
No.
D020E
Device Characteristics
Power-down Base
Current (IPD)(2)
D021E
D022E
D023E
D024E
D025E*
D026E
D027E
D028E
Typ
Max.
Units
0.05
0.15
Conditions
VDD
Note
2.0
11
3.0
0.35
15
5.0
28
2.0
30
3.0
35
5.0
42
65
3.0
85
127
5.0
32
45
2.0
60
78
3.0
120
160
5.0
30
70
2.0
45
90
3.0
75
120
5.0
39
91
2.0
59
117
3.0
98
156
5.0
3.5
18
2.0
WDT Current(1)
BOR Current(1)
Comparator Current(1), both
comparators enabled
CVREF Current(1) (high range)
4.0
21
3.0
5.0
24
5.0
0.30
12
3.0
0.36
16
5.0
90
130
3.0
125
170
5.0
DS41291E-page 250
PIC16F882/883/884/886/887
17.5
DC Characteristics:
PIC16F883/884/886/887-I (Industrial)
PIC16F883/884/886/887-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +85C for industrial
-40C TA +125C for extended
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Min.
Typ
Max.
Units
Vss
Vss
Conditions
0.8
0.15 VDD
Vss
0.2 VDD
D030
D030A
D031
D032
VSS
0.2 VDD
D033
VSS
0.3
VSS
0.3 VDD
2.0
VDD
VDD
0.8 VDD
VDD
0.8 VDD
VDD
1.6
VDD
D033A
VIH
D040
D040A
D041
D042
MCLR
D043
D043A
0.7 VDD
VDD
D043B
0.9 VDD
VDD
0.1
(Note 1)
(2)
IIL
D060
I/O ports
D061
MCLR(3)
0.1
D063
OSC1
0.1
IPUR
50
250
400
VOL
0.6
VDD 0.7
D070*
D080
I/O ports
VOH
D090
Note 1:
2:
3:
4:
5:
DS41291E-page 251
PIC16F882/883/884/886/887
17.5
DC Characteristics:
PIC16F883/884/886/887-I (Industrial)
PIC16F883/884/886/887-E (Extended) (Continued)
DC CHARACTERISTICS
Param
No.
Sym.
D100
IULP
Characteristic
Typ
Max.
Units
200
nA
OSC2 pin
15
pF
50
pF
Conditions
COSC2
D101A* CIO
D120
ED
Byte Endurance
100K
1M
E/W
D120A
ED
Byte Endurance
10K
100K
E/W
D121
VDRW
VMIN
5.5
D122
TDEW
D123
TRETD
Characteristic Retention
40
D124
TREF
1M
10M
E/W
-40C TA +85C
-40C TA +85C
+85C TA +125C
Using EECON1 to read/write
VMIN = Minimum operating
voltage
ms
EP
Cell Endurance
10K
100K
E/W
D130A
ED
Cell Endurance
1K
10K
E/W
D131
VPR
VMIN
5.5
D132
VPEW
VMIN
5.5
4.5
5.5
V
ms
D133
TPEW
2.5
D134
TRETD
Characteristic Retention
40
Note 1:
2:
3:
4:
5:
+85C TA +125C
VMIN = Minimum operating
voltage
DS41291E-page 252
PIC16F882/883/884/886/887
17.6
Thermal Considerations
Sym.
Characteristic
Typ.
Units
TH01
JA
Thermal Resistance
Junction to Ambient
47.2
24.4
45.8
60.2
80.2
89.4
29
C/W
C/W
C/W
C/W
C/W
C/W
C/W
TH02
JC
Thermal Resistance
Junction to Case
24.7
20.0
14.5
29
23.8
23.9
20.0
150
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
W
W
TH03
TH04
TH05
TH06
TH07
Note 1:
2:
3:
Conditions
40-pin PDIP package
44-pin QFN package
44-pin TQFP package
28-pin PDIP package
28-pin SOIC package
28-pin SSOP package
28-pin QFN package
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
PDER
Derated Power
W
PDER = (TJ - TA)/JA
(NOTE 2, 3)
IDD is current to run the chip alone without driving any load on the output pins.
TA = Ambient Temperature.
Maximum allowable power dissipation is the lower value of either the absolute maximum total power
dissipation or derated power (PDER).
DS41291E-page 253
PIC16F882/883/884/886/887
17.7
FIGURE 17-3:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL =
DS41291E-page 254
50 pF
15 pF
PIC16F882/883/884/886/887
17.8
FIGURE 17-4:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 17-1:
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
OS04*
TCY
TosH,
TosL
Min.
Typ
Max.
Units
DC
DC
DC
DC
0.1
1
DC
27
250
50
50
250
50
250
32.768
30.5
37
4
20
20
4
20
4
10,000
1,000
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
s
ns
ns
ns
s
ns
ns
ns
Conditions
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
200
TCY
DC
ns
TCY = 4/FOSC
2
s
LP oscillator
100
ns
XT oscillator
20
ns
HS oscillator
OS05* TosR, External CLKIN Rise,
0
ns
LP oscillator
TosF
External CLKIN Fall
0
ns
XT oscillator
0
ns
HS oscillator
* These parameters are characterized but not tested.
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at min values with an external
clock applied to OSC1 pin. When an external clock input is used, the max cycle time limit is DC (no clock) for
all devices.
DS41291E-page 255
PIC16F882/883/884/886/887
TABLE 17-2:
OSCILLATOR PARAMETERS
Sym.
Characteristic
Freq.
Tolerance
Min.
Typ
Max.
Units
Conditions
OS06
TWARM
TOSC
Slowest clock
OS07
TSC
21
ms
LFINTOSC/64
OS08
HFOSC
Internal Calibrated
HFINTOSC Frequency(2)
1%
7.92
8.0
8.08
MHz
2%
7.84
8.0
8.16
MHz
5%
7.60
8.0
8.40
MHz
15
31
45
kHz
OS09*
LFOSC
Internal Uncalibrated
LFINTOSC Frequency
OS10*
TIOSC
HFINTOSC Oscillator
Wake-up from Sleep
Start-up Time
ST
5.5
12
24
3.5
14
11
DS41291E-page 256
PIC16F882/883/884/886/887
FIGURE 17-5:
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 17-3:
Sym.
Characteristic
Min.
Conditions
TOSH2CKL
70
ns
VDD = 5.0V
OS12
TOSH2CKH
FOSC to CLKOUT
(1)
72
ns
VDD = 5.0V
OS13
TCKL2IOV
20
ns
OS14
TIOV2CKH
TOSC + 200 ns
ns
OS15*
TOSH2IOV
50
70
ns
VDD = 5.0V
OS16
TOSH2IOI
50
ns
VDD = 5.0V
OS17
TIOV2OSH
20
ns
OS18
TIOR
15
40
72
32
ns
VDD = 2.0V
VDD = 5.0V
OS19
TIOF
28
15
55
30
ns
VDD = 2.0V
VDD = 5.0V
OS20*
TINP
25
ns
OS21*
TRAP
TCY
ns
OS11
Note 1:
2:
DS41291E-page 257
PIC16F882/883/884/886/887
FIGURE 17-6:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1:
Asserted low.
FIGURE 17-7:
VDD
VBOR + VHYST
VBOR
37
Reset
(due to BOR)
*
33*
DS41291E-page 258
PIC16F882/883/884/886/887
TABLE 17-4:
Sym.
Characteristic
Min.
Typ
Max. Units
Conditions
30
TMCL
2
5
s
s
31
TWDT
10
10
16
16
29
31
ms
ms
32
TOST
1024
33*
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.0
2.2
3.6
4.0
4.4
3.6
4.0
4.5
50
mV
100
36*
VHYST
37*
TBOR
TOSC (NOTE 3)
VDD VBOR
DS41291E-page 259
PIC16F882/883/884/886/887
FIGURE 17-8:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 17-5:
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
No Prescaler
With Prescaler
41*
TT0L
No Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
With Prescaler
Asynchronous
46*
TT1L
T1CKI Low
Time
Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
47*
TT1P
48
FT1
49*
Asynchronous
Min.
Typ
Max.
Units
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
30
ns
0.5 TCY + 20
ns
15
ns
30
ns
Greater of:
30 or TCY + 40
N
ns
60
ns
32.768
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
DS41291E-page 260
PIC16F882/883/884/886/887
FIGURE 17-9:
CCP1
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 17-6:
Sym.
TccL
TccH
TccP
Characteristic
CCP1 Input Low Time
CCP1 Input High Time
CCP1 Input Period
Min.
Typ
Max.
Units
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
3TCY + 40
N
ns
Conditions
N = prescale
value (1, 4 or
16)
DS41291E-page 261
PIC16F882/883/884/886/887
TABLE 17-7:
COMPARATOR SPECIFICATIONS
Sym.
Characteristics
CM01
VOS
CM02
VCM
CM03* CMRR
CM04* TRT
Response Time
Min.
Typ
Max.
Units
5.0
10
mV
VDD - 1.5
+55
dB
Falling
150
600
ns
Rising
200
1000
ns
10
Comments
(VDD - 1.5)/2
(NOTE 1)
TABLE 17-8:
Sym.
Characteristics
Min.
Typ
Max.
Units
Comments
CV01*
CLSB
Step Size(2)
VDD/24
VDD/32
V
V
CV02*
CACC
Absolute Accuracy
1/2
1/2
LSb
LSb
CV03*
CR
2k
CV04*
CST
Settling Time(1)
10
TABLE 17-9:
Symbol
Characteristics
Typ.
Max.
Units
VR01
VROUT
VR voltage output
0.5
0.6
0.7
VR02*
TSTABLE
Settling Time
10
100*
Comments
DS41291E-page 262
PIC16F882/883/884/886/887
TABLE 17-10: PIC16F883/884/886/887 A/D CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C
Param
Sym.
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
10 bits
AD02
EIL
Integral Error
AD03
EDL
Differential Error
AD04
EOFF
Offset Error
+1.5
+3.0
AD07
EGN
bit
Gain Error
AD06 VREF
AD06A
Reference Voltage(3)
2.2
2.7
VDD
AD07
VAIN
Full-Scale Range
VSS
VREF
AD08
ZAIN
Recommended
Impedance of Analog
Voltage Source
10
AD09* IREF
10
1000
50
DS41291E-page 263
PIC16F882/883/884/886/887
TABLE 17-11: PIC16F883/884/886/887 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C
Param
Sym.
No.
AD130* TAD
Characteristic
A/D Clock Period
A/D Internal RC
Oscillator Period
AD131 TCNV
Conversion Time
(not including
Acquisition Time)(1)
Min.
Typ
1.6
9.0
3.0
9.0
3.0
6.0
9.0
1.6
4.0
6.0
At VDD = 5.0V
11
TAD
11.5
TOSC/2
TOSC/2 + TCY
TAMP
AD134 TGO
Max. Units
Conditions
DS41291E-page 264
PIC16F882/883/884/886/887
FIGURE 17-10:
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
9
A/D Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
DONE
Note 1:
Sampling Stopped
AD132
Sample
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 17-11:
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
9
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
Note 1:
AD132
Sampling Stopped
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS41291E-page 265
PIC16F882/883/884/886/887
FIGURE 17-12:
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note:
122
Symbol
Characteristic
FIGURE 17-13:
Min.
Max.
Units
40
ns
20
20
ns
ns
Conditions
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 17-3 for load conditions.
Symbol
Characteristic
DS41291E-page 266
Min.
Max.
Units
10
ns
15
ns
Conditions
PIC16F882/883/884/886/887
FIGURE 17-14:
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 17-3 for load conditions.
FIGURE 17-15:
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 17-3 for load conditions.
DS41291E-page 267
PIC16F882/883/884/886/887
FIGURE 17-16:
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
bit 6 - - - - - -1
77
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 17-3 for load conditions.
FIGURE 17-17:
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
77
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 17-3 for load conditions.
DS41291E-page 268
PIC16F882/883/884/886/887
TABLE 17-14: SPI MODE REQUIREMENTS
Param
No.
Symbol
70*
Characteristic
Min.
Typ
TCY
ns
71*
TSCH
TCY + 20
ns
72*
TSCL
TCY + 20
ns
73*
100
ns
74*
TSCH2DIL,
TSCL2DIL
100
ns
75*
TDOR
10
25
ns
76*
TDOF
3.0-5.5V
2.0-5.5V
25
50
ns
10
25
ns
77*
TSSH2DOZ
10
50
ns
78*
TSCR
3.0-5.5V
10
25
ns
2.0-5.5V
25
50
ns
79*
TSCF
10
25
ns
80*
3.0-5.5V
50
ns
2.0-5.5V
145
ns
81*
Tcy
ns
82*
TSSL2DOV
50
ns
83*
1.5TCY + 40
ns
FIGURE 17-18:
SCL
91
90
93
92
SDA
Start
Condition
Stop
Condition
DS41291E-page 269
PIC16F882/883/884/886/887
TABLE 17-15: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93
Characteristic
Start condition
4700
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
Hold time
*
Min.
600
4000
600
Conditions
ns
ns
ns
ns
FIGURE 17-19:
102
100
101
SCL
90
106
107
91
92
SDA
In
109
109
110
SDA
Out
Note: Refer to Figure 17-3 for load conditions.
DS41291E-page 270
PIC16F882/883/884/886/887
TABLE 17-16: I2C BUS DATA REQUIREMENTS
Param.
No.
100*
Symbol
THIGH
Characteristic
Clock high time
Min.
Max.
Units
4.0
0.6
1.5TCY
4.7
1.3
SSP Module
101*
TLOW
SSP Module
102*
103*
90*
91*
106*
107*
92*
109*
110*
TR
TF
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
CB
*
Note 1:
2:
Conditions
1.5TCY
1000
ns
0.1CB
300
ns
300
ns
20 + 0.1CB
300
ns
CB is specified to be from
10-400 pF
Only relevant for
Repeated Start condition
20 +
4.7
0.6
4.0
0.6
ns
0.9
250
ns
100
ns
Start condition
setup time
4.7
0.6
3500
ns
ns
4.7
1.3
400
pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
DS41291E-page 271
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 272
PIC16F882/883/884/886/887
18.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. Maximum or minimum represents
(mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range.
IDD (mA)
FIGURE 18-1:
TYPICAL I3V
DD vs. FOSC
DD (EC
Typical
2V
4V OVER V5V
EC Mode0.277
1Mhz
0.086
0.153
0.220
2Mhz
0.150
0.2596
0.3718
0.4681
4Mhz
0.279
0.472
0.675
0.850
4.0
6Mhz
0.382
0.635
0.903
1.135
8Mhz Typical: Statistical
0.486Mean @25C
0.798
1.132
1.420
10Mhz Maximum: Mean
0.589
0.961
1.360
1.706
(Worst-case
Temp) + 3
3.5
12Mhz
0.696
1.126
1.596
2.005
(-40C to 125C)
14Mhz
0.802
1.291
1.832
2.304
16Mhz
0.908
1.457
2.068
2.603
3.0
18Mhz
1.017
1.602
2.268
2.848
20Mhz
1.126
1.748
2.469
3.093
2.5
Max
2.0
1Mhz
2Mhz
4Mhz
1.5
6Mhz
8Mhz
1.0
10Mhz
12Mhz
14Mhz
0.5
16Mhz
18Mhz
20Mhz
0.0
1 MHz
2V
0.168
0.261
0.449
0.577
0.705
0.833
0.956
1.078
1.201
1.305
1.409
2 MHz
3V
0.236
0.394
0.710
0.972
1.233
1.495
1.711
1.926
2.142
2.326
2.510
4 MHz
6 MHz
4V
0.315
0.537
0.981
1.331
1.682
2.032
2.372
2.713
3.054
3.295
3.536
8 MHz
5V
0.412
0.704
1.287
1.739
2.191
2.642
3.101
3.560
4.018
4.324
4.630
10 MHz
MODE)
5.5V
0.310
0.5236
0.951
1.269
1.587
1.905
2.241
2.577
2.913
3.185
3.458
5.5V
5V
4V
5.5V
0.452
0.780
1.435
1.950
2.465
2.979
3.506
4.032
4.558
4.887
12 MHz
3V
2V
14 MHz
16 MHz
18 MHz
20 MHz
VDD (V)
DS41291E-page 273
PIC16F882/883/884/886/887
FIGURE 18-2:
6.0
5.0
5.5V
5V
4.0
IDD (mA)
4V
3.0
3V
2.0
2V
1.0
0.0
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
18 MHz
20 MHz
VDD (V)
FIGURE 18-3:
5.0
4.5
4.0
5.5V
5V
4.5V
IDD (mA)
3.5
3.0
2.5
2.0
1.5
1.0
3V
3.5V
4V
4.5V
5V
5.5V
0.567660978 0.6909750.8211857610.9883470541.0462473761.119615457
1.1610564131.4069334781.6664380432.0030751092.1193190652.268818804
4V 2.883088587 3.03554863
3.23775
3.5V 3.74139 3.967407543
3V
0.5
0.0
4 MHz
10 MHz
16 MHz
20 Mhz
FOSC
DS41291E-page 274
PIC16F882/883/884/886/887
FIGURE 18-4:
5.5
5.0
4.5
4.0
5.5V
5V
4.5V
Typical:
Mean @25C4V
3V Statistical 3.5V
4.5V
5V
5.5V
Maximum:
Mean (Worst-case Temp) + 3
0.8868608641.0693043161.2645617521.4868166111.5076394231.520959608
(-40C1.6176371031.9623642592.3355493582.7630868222.8139211682.849632041
to 125C)
3.8375797553.9157601913.967889512
4.685048474 4.78069621
IDD (mA)
3.5
3.0
2.5
4V
2.0
3.5V
3V
1.5
1.0
0.5
0.0
4 MHz
10 MHz
16 MHz
20 MHz
FOSC
FIGURE 18-5:
XT Mode
1,200
1,000
2.5
3.5
4.5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
244.8837 320.7132 396.5426 461.707 526.8719 587.642 648.412 724.0755
375.529 522.3721 669.2152 822.619 976.0232 1163.67 1351.32
IDD (uA)
800
4 MHz
600
400
1 MHz
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 275
PIC16F882/883/884/886/887
FIGURE 18-6:
1,800
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
1,600
1,400
IDD (uA)
1,200
1,000
4 MHz
800
600
1 MHz
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.5
5.0
5.5
VDD (V)
FIGURE 18-7:
(EXTRC Mode)
1,800
1,600
1,400
IDD (uA)
1,200
4 Mhz
1,000
800
1 Mhz
600
400
200
0
2.0
2.5
3.0
3.5
4.0
VDD (V)
DS41291E-page 276
PIC16F882/883/884/886/887
FIGURE 18-8:
2,000
Typical:
Typical:Statistical
StatisticalMean
Mean@25C
@25C
Maximum:Mean
Mean(Worst-case
(Worst CaseTemp)
Temp)+ +33
Maximum:
(-40C to 125C)
(-40C to 125C)
1,800
1,600
1,400
4 Mhz
IDD (uA)
1,200
1,000
800
1 Mhz
600
400
200
0
2.0
2.5
3.0
4.0
3.5
4.5
5.0
5.5
VDD (V)
FIGURE 18-9:
80
70
60
IDD (A)
50
Maximum
40
30
Typical
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 277
PIC16F882/883/884/886/887
FIGURE 18-10:
80
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
70
IDD (uA)
60
50
32 kHz Maximum
40
30
32 kHz Typical
20
10
0
2.0
3.0
2.5
4.0
3.5
4.5
5.0
5.5
VDD (V)
FIGURE 18-11:
2,500
IDD (uA)
2,000
HFINTOSC
5V
5.5V
5.5V
5V
1,500
4V
3V
1,000
2V
500
2V
3V
4V
5V
5.5V
0
125 kHz
25 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
VDD (V)
DS41291E-page 278
PIC16F882/883/884/886/887
FIGURE 18-12:
3,000
2,500
5.5V
5V
IDD (uA)
2,000
4V
1,500
3V
1,000
2V
500
0
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
VDD (V)
FIGURE 18-13:
0.45
0.40
0.35
IPD (uA)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 279
PIC16F882/883/884/886/887
FIGURE 18-14:
18
16
14
Max. 125C
IPD (A)
12
10
8
6
4
Max. 85C
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-15:
180
160
140
120
IPD (uA)
Maximum
100
80
Typical
60
Typical Max
31.9 40 43.9
45.6
60.8
59.3 20 77.7
73.0
95.8
86.7 113.8
0
100.4 131.8
114.1 149.9 2.0
127.7
DS41291E-page 280
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
PIC16F882/883/884/886/887
FIGURE 18-16:
160
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
140
120
IPD (A)
100
Maximum
80
Typical
60
40
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-17:
3.0
2.5
IPD (uA)
2.0
1.5
Typical:Typical
Statistical Mean
@25C Max 125C
Max 85C
2 1.007
2.140
27.702
2.5 1.146
2.711
29.079
3 1.285
3.282
30.08
3.5 1.449
3.899
31.347
4 1.612
4.515
32.238
4.5 1.924
5.401
33.129
5 2.237
6.288
34.02
5.5 2.764
7.776
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 281
PIC16F882/883/884/886/887
FIGURE 18-18:
40.0
35.0
Maximum:
Mean
+3
Maximum:
Mean
+ 3
Max. 125C
30.0
IPD (uA)
25.0
20.0
15.0
10.0
Max. 85C
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-19:
32
30
28
Max. (125C)
26
Max. (85C)
Time (ms)
24
22
20
Typical
18
16
14
Minimum
12
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 282
PIC16F882/883/884/886/887
FIGURE 18-20:
30
28
26
Maximum
Time (ms)
24
22
20
Typical
18
16
Minimum
14
12
10
-40C
25C
85C
125C
Temperature (C)
FIGURE 18-21:
IPD (uA)
Typical
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 283
PIC16F882/883/884/886/887
FIGURE 18-22:
180
160
140
Max. 125C
IPD (uA)
120
100
Max. 85C
80
Typical
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.5
5.0
5.5
VDD (V)
FIGURE 18-23:
160
140
120
IPD (uA)
100
Typical
80
60
40
20
0
2.0
2.5
3.0
3.5
4.0
VDD (V)
DS41291E-page 284
PIC16F882/883/884/886/887
FIGURE 18-24:
180
160
140
Max 125C
IPD (uA)
120
Max 85C
100
80
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 18-25:
30
25
IPD (uA)
20
15
10
2
2.5
3
3.5
4
4.5
5
5.5
Typ 25C
2.022
2.247
2.472
2.453
2.433
2.711
2.989
3.112
Max 85C
4.98
5.23
5.49
5.79
6.08
6.54
7.00
7.34
Max 125C
17.54
19.02
20.29
21.50
Max. 85C
22.45
23.30
24.00
Typ. 25C
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
DS41291E-page 285
PIC16F882/883/884/886/887
FIGURE 18-26:
0.8
0.7
0.6
VOL (V)
0.5
Max. 85C
0.4
Typical 25C
0.3
0.2
Min. -40C
0.1
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 18-27:
0.45
0.40
Max. 125C
0.35
Max. 85C
VOL (V)
0.30
0.25
Typ. 25C
0.20
0.15
Min. -40C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
DS41291E-page 286
PIC16F882/883/884/886/887
FIGURE 18-28:
3.5
3.0
Max. -40C
Typ. 25C
2.5
Min. 125C
VOH (V)
2.0
1.5
1.0
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
FIGURE 18-29:
(VDD = 5.0V)
VOH vs. IOH OVER TEMPERATURE
(
,
)
5.5
5.0
Max. -40C
Typ. 25C
VOH (V)
4.5
Min. 125C
4.0
3.5
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
DS41291E-page 287
PIC16F882/883/884/886/887
FIGURE 18-30:
1.7
1.5
VIN (V)
1.3
Typ. 25C
1.1
Min. 125C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-31:
4.0
VIH Max. 125C
3.5
VIN (V)
3.0
2.5
2.0
VIL Max. -40C
1.5
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 288
PIC16F882/883/884/886/887
FIGURE 18-32:
4
5.5
200
278
639
846
V+ input 202
= VCM 531
140
V- input = Transition from VCM + 100MV to VCM - 20MV
1,000
900
800
Max. (125C)
700
600
Note:
500
Max. (85C)
400
300
Typ. (25C)
200
Min. (-40C)
100
0
2.0
2.5
4.0
5.5
VDD (Volts)
FIGURE 18-33:
Vdd
-40C 25C
85C
125C
2
279
327
547
557
600
2.5
226
267
425
440
4
172
204
304
319
5.5
119
142
182
500
400
300
Max. (125C)
Max. (85C)
200
Note:
100
Typ. (25C)
Min. (-40C)
0
2.0
2.5
4.0
5.5
VDD (Volts)
DS41291E-page 289
PIC16F882/883/884/886/887
FIGURE 18-34:
45,000
40,000
Max. -40C
35,000
Typ. 25C
Frequency (Hz)
30,000
25,000
20,000
Min. 85C
Min. 125C
15,000
10,000
5,000
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-35:
8
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
125C
Time (s)
85C
25C
-40C
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 290
PIC16F882/883/884/886/887
FIGURE 18-36:
16
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case) + 3
14
85C
12
25C
Time (s)
10
-40C
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-37:
25
Time (s)
20
15
85C
25C
10
-40C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 291
PIC16F882/883/884/886/887
FIGURE 18-38:
10
9
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
Time (s)
85C
6
25C
5
-40C
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-39:
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 292
PIC16F882/883/884/886/887
FIGURE 18-40:
5
4
Change from Calibration (%)
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-41:
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41291E-page 293
PIC16F882/883/884/886/887
FIGURE 18-42:
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 18-43:
0.65
0.64
0.63
VP6 (V)
0.62
0.61
0.60
0.59
Typical
0.58
0.57
0.56
0.55
2
5.5
VDD (V)
DS41291E-page 294
PIC16F882/883/884/886/887
FIGURE 18-44:
-1
-2
-40
25
85
125
Temperature in Degrees C
FIGURE 18-45:
-1
-2
-40
25
85
125
Temperature in Degrees C
DS41291E-page 295
PIC16F882/883/884/886/887
FIGURE 18-46:
35
Parts=118
Number of Parts
30
25
20
15
10
5
0.690
0.700
0.690
0.700
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
FIGURE 18-47:
40
35
Parts=118
Number of Parts
30
25
20
15
10
5
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
DS41291E-page 296
PIC16F882/883/884/886/887
FIGURE 18-48:
40
35
Parts=118
Number of Parts
30
25
20
15
10
5
0.700
0.690
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
FIGURE 18-49:
30
Parts=118
Number of Parts
25
20
15
10
0.700
0.690
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
DS41291E-page 297
PIC16F882/883/884/886/887
FIGURE 18-50:
30
Number of Parts
25
Parts=118
20
15
10
0.700
0.690
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
FIGURE 18-51:
35
Number of Parts
30
Parts=118
25
20
15
10
5
0.700
0.690
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
DS41291E-page 298
PIC16F882/883/884/886/887
FIGURE 18-52:
30
25
Number of Parts
Parts=118
20
15
10
0.700
0.690
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
FIGURE 18-53:
30
Number of Parts
25
Parts=118
20
15
10
0.700
0.690
0.680
0.670
0.660
0.650
0.640
0.630
0.620
0.610
0.600
0.590
0.580
0.570
0.560
0.550
0.540
0.530
0.520
0.510
0.500
Voltage (V)
DS41291E-page 299
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 300
PIC16F882/883/884/886/887
19.0
PACKAGING INFORMATION
19.1
Example
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F886/SO e3
0710017
Example
28-Lead SSOP
XXXXXXXXXXXX
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YYWWNNN
28-Lead QFN
PIC16F883
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0710017
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*
Note:
PIC16F883
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0710017
16F886
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0710017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS41291E-page 301
PIC16F882/883/884/886/887
19.1
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead QFN
44-Lead TQFP
PIC16F887
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0710017
Example
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Legend: XX...X
Y
YY
WW
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e3
DS41291E-page 302
0710017
Example
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XXXXXXXXXX
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YYWWNNN
Note:
PIC16F885
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PIC16F887
-I/PT e3
0710017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIC16F882/883/884/886/887
19.2
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DS41291E-page 312
PIC16F882/883/884/886/887
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (5/2006)
APPENDIX B:
MIGRATING FROM
OTHER PIC
DEVICES
Revision B (7/2006)
B.1
TABLE B-1:
Revision C
Section 19.0 Packaging Information:
package drawings and added note.
Added PIC16F882 part number.
Replaced PICmicro with PIC.
Replaced
PIC16F87X to PIC16F88X
FEATURE COMPARISON
Feature
Max Operating Speed
Max Program
Memory (Words)
PIC16F87X
PIC16F88X
20 MHz
20 MHz
8192
8192
SRAM (bytes)
368
368
A/D Resolution
10-bit
10-bit
256
256
Timers (8/16-bit)
2/1
2/1
Oscillator Modes
Brown-out Reset
Y (2.1V/4V)
Internal Pull-ups
RB<7:4>
RB<7:0>,
MCLR
Interrupt-on-change
RB<7:4>
RB<7:0>
Comparator
References
CVREF
CVREF and
VP6
ECCP/CCP
Revision D
Replaced Package Drawings (Rev. AM); Replaced
Development Support Section; Revised Product ID
Section.
Revision E (01/2008)
Added Char Data; Removed Preliminary status;
Revised Device Table (PIC16F882, I/O); Revised the
following: Pin Diagram 44 TQFP, pin 30; Table 5, I/O
RA7; Table 1-1, RA1 and RA4; Section 2.2.1; Register
2-3, INTCON; Example 3-1; Section 3.2.2; Example
3-2; Figure 6-1; Section 6.2.2; Section 6.6; Section
8.10.3; Table 9-1; Equation 11-1; Added Figure 11-14
and renumbered remaining Figures; Register 11-3;
Register 13-3; Section 14.0; Section 14.1; Section
14.9; Section 14.10; Section 17.0; Updated Package
Drawings.
0/2
1/1
Ultra Low-Power
Wake-Up
Extended WDT
INTOSC Frequencies
32 kHz-8 MHz
Clock Switching
MSSP
Standard
w/Slave
Address Mask
USART
AUSART
EUSART
14
ADC Channels
Note:
DS41291E-page 313
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 314
PIC16F882/883/884/886/887
INDEX
A
A/D
Specifications.................................................... 263, 264
Absolute Maximum Ratings .............................................. 245
AC Characteristics
Industrial and Extended ............................................ 255
Load Conditions ........................................................ 254
ACKSTAT ......................................................................... 198
ACKSTAT Status Flag ...................................................... 198
ADC .................................................................................... 99
Acquisition Requirements ......................................... 107
Associated Registers ................................................ 109
Block Diagram............................................................. 99
Calculating Acquisition Time..................................... 107
Channel Selection..................................................... 100
Configuration............................................................. 100
Configuring Interrupt ................................................. 103
Conversion Clock...................................................... 100
Conversion Procedure .............................................. 103
Internal Sampling Switch (RSS) Impedance.............. 107
Interrupts................................................................... 101
Operation .................................................................. 102
Operation During Sleep ............................................ 102
Port Configuration ..................................................... 100
Reference Voltage (VREF)......................................... 100
Result Formatting...................................................... 102
Source Impedance.................................................... 107
Special Event Trigger................................................ 102
Starting an A/D Conversion ...................................... 102
ADCON0 Register............................................................. 104
ADCON1 Register............................................................. 105
ADRESH Register (ADFM = 0) ......................................... 106
ADRESH Register (ADFM = 1) ......................................... 106
ADRESL Register (ADFM = 0).......................................... 106
ADRESL Register (ADFM = 1).......................................... 106
Analog Input Connection Considerations............................ 90
Analog-to-Digital Converter. See ADC
ANSEL Register .................................................................. 40
ANSELH Register ............................................................... 48
Assembler
MPASM Assembler................................................... 242
B
Baud Rate Generator ........................................................ 195
BAUDCTL Register ........................................................... 162
BF ..................................................................................... 198
BF Status Flag .................................................................. 198
Block Diagrams
(CCP) Capture Mode Operation ............................... 126
ADC ............................................................................ 99
ADC Transfer Function ............................................. 108
Analog Input Model ............................................. 90, 108
Auto-Shutdown ......................................................... 141
Baud Rate Generator................................................ 195
CCP PWM................................................................. 128
Clock Source............................................................... 61
Comparator C1 ........................................................... 84
Comparator C1 and ADC Voltage Reference ............. 95
Comparator C2 ........................................................... 84
Compare ................................................................... 127
Crystal Operation ........................................................ 64
EUSART Receive ..................................................... 152
EUSART Transmit .................................................... 151
C
C Compilers
MPLAB C18.............................................................. 242
MPLAB C30.............................................................. 242
Capture Module. See Enhanced Capture/Compare/
PWM(ECCP)
Capture/Compare/PWM (CCP)
Associated Registers w/ Capture, Compare
and Timer1 ....................................................... 149
Associated Registers w/ PWM and Timer2 .............. 149
Capture Mode........................................................... 126
CCP Pin Configuration ............................................. 126
Compare Mode......................................................... 127
CCP Pin Configuration ..................................... 127
Software Interrupt Mode ........................... 126, 127
Special Event Trigger ....................................... 127
Timer1 Mode Selection............................. 126, 127
DS41291E-page 315
PIC16F882/883/884/886/887
Prescaler ................................................................... 126
PWM Mode ............................................................... 128
Duty Cycle......................................................... 129
Effects of Reset................................................. 131
Example PWM Frequencies and
Resolutions, 20 MHZ ................................ 130
Example PWM Frequencies and
Resolutions, 8 MHz................................... 130
Operation in Sleep Mode .................................. 131
Setup for Operation........................................... 131
System Clock Frequency Changes................... 131
PWM Period .............................................................. 129
Setup for PWM Operation ......................................... 131
Timer Resources....................................................... 125
CCP1CON (Enhanced) Register....................................... 124
CCP2CON Register .......................................................... 125
Clock Accuracy with Asynchronous Operation ................. 160
Clock Sources
External Modes ........................................................... 63
EC ....................................................................... 63
HS ....................................................................... 64
LP........................................................................ 64
OST..................................................................... 63
RC....................................................................... 65
XT ....................................................................... 64
Internal Modes ............................................................ 65
Frequency Selection ........................................... 67
HFINTOSC.......................................................... 65
HFINTOSC/LFINTOSC Switch Timing ............... 67
INTOSC .............................................................. 65
INTOSCIO........................................................... 65
LFINTOSC .......................................................... 67
Clock Switching................................................................... 69
CM1CON0 Register ............................................................ 88
CM2CON0 Register ............................................................ 89
CM2CON1 Register ............................................................ 91
Code Examples
A/D Conversion ......................................................... 103
Assigning Prescaler to Timer0 .................................... 74
Assigning Prescaler to WDT ....................................... 74
Changing Between Capture Prescalers .................... 126
Indirect Addressing ..................................................... 37
Initializing PORTA ....................................................... 39
Initializing PORTB ....................................................... 47
Initializing PORTC....................................................... 53
Initializing PORTD....................................................... 57
Initializing PORTE ....................................................... 59
Loading the SSPBUF Register ................................. 184
Saving STATUS and W Registers in RAM ............... 223
Ultra Low-Power Wake-up Initialization ...................... 41
Write Verify ............................................................... 120
Writing to Flash Program Memory ............................ 119
Code Protection ................................................................ 227
Comparator
C2OUT as T1 Gate ............................................... 77, 91
Effects of a Reset........................................................ 87
Operation .................................................................... 83
Operation During Sleep .............................................. 87
Response Time ........................................................... 85
Specifications ............................................................ 262
Synchronizing COUT w/Timer1 .................................. 91
Comparator Module ............................................................ 83
Associated Registers .................................................. 97
C1 Output State Versus Input Conditions ................... 85
Comparator Voltage Reference (CVREF)
DS41291E-page 316
Response Time........................................................... 85
Comparator Voltage Reference (CVREF) ............................ 94
Effects of a Reset ....................................................... 87
Specifications ........................................................... 262
Compare Module. See Enhanced Capture/
Compare/PWM (ECCP)
CONFIG1 Register ........................................................... 210
CONFIG2 Register ........................................................... 211
Configuration Bits ............................................................. 210
CPU Features ................................................................... 209
Customer Change Notification Service............................. 323
Customer Notification Service .......................................... 323
Customer Support............................................................. 323
D
Data EEPROM Memory.................................................... 111
Associated Registers ................................................ 121
Code Protection ........................................................ 120
Reading .................................................................... 114
Writing ...................................................................... 114
Data Memory ...................................................................... 22
DC Characteristics
Extended .................................................................. 250
Industrial ................................................................... 249
Industrial and Extended ............................ 247, 248, 251
Development Support ....................................................... 241
Device Overview................................................................. 13
E
ECCP. See Enhanced Capture/Compare/PWM
ECCPAS Register............................................................. 142
EEADR Register ............................................................... 112
EEADR Registers ............................................................. 111
EEADRH Registers........................................................... 111
EECON1 Register..................................................... 111, 113
EECON2 Register............................................................. 111
EEDAT Register ............................................................... 112
EEDATH Register............................................................. 112
EEPROM Data Memory
Avoiding Spurious Write ........................................... 120
Write Verify ............................................................... 120
Effects of Reset
PWM mode ............................................................... 131
Electrical Specifications .................................................... 245
Enhanced Capture/Compare/PWM .................................. 123
Enhanced Capture/Compare/PWM (ECCP)
Enhanced PWM Mode.............................................. 132
Auto-Restart ..................................................... 143
Auto-shutdown.................................................. 141
Direction Change in Full-Bridge Output Mode.. 138
Full-Bridge Application...................................... 136
Full-Bridge Mode .............................................. 136
Half-Bridge Application ..................................... 135
Half-Bridge Application Examples .................... 144
Half-Bridge Mode.............................................. 135
Output Relationships (Active-High and
Active-Low).............................................. 133
Output Relationships Diagram.......................... 134
Programmable Dead Band Delay..................... 144
Shoot-through Current ...................................... 144
Start-up Considerations .................................... 140
Specifications ........................................................... 261
Timer Resources ...................................................... 124
Enhanced Universal Synchronous
Asynchronous Receiver Transmitter (EUSART)....... 151
Errata .................................................................................. 12
PIC16F882/883/884/886/887
EUSART ........................................................................... 151
Associated Registers
Baud Rate Generator........................................ 163
Asynchronous Mode ................................................. 153
12-bit Break Transmit and Receive .................. 169
Associated Registers
Receive..................................................... 159
Transmit.................................................... 155
Auto-Wake-up on Break ................................... 168
Baud Rate Generator (BRG) ............................ 163
Clock Accuracy ................................................. 160
Receiver............................................................ 156
Setting up 9-bit Mode with Address Detect....... 158
Transmitter........................................................ 153
Baud Rate Generator (BRG)
Auto Baud Rate Detect ..................................... 167
Baud Rate Error, Calculating ............................ 163
Baud Rates, Asynchronous Modes .................. 164
Formulas ........................................................... 163
High Baud Rate Select (BRGH Bit) .................. 163
Synchronous Master Mode ............................... 171, 175
Associated Registers
Receive..................................................... 174
Transmit.................................................... 172
Reception.......................................................... 173
Requirements, Synchronous Receive .............. 266
Requirements, Synchronous Transmission ...... 266
Timing Diagram, Synchronous Receive ........... 266
Timing Diagram, Synchronous Transmission ... 266
Transmission .................................................... 171
Synchronous Slave Mode
Associated Registers
Receive..................................................... 176
Transmit.................................................... 175
Reception.......................................................... 176
Transmission .................................................... 175
F
Fail-Safe Clock Monitor....................................................... 71
Fail-Safe Condition Clearing ....................................... 71
Fail-Safe Detection ..................................................... 71
Fail-Safe Operation..................................................... 71
Reset or Wake-up from Sleep..................................... 71
Firmware Instructions........................................................ 231
Flash Program Memory .................................................... 111
Writing....................................................................... 117
Fuses. See Configuration Bits
G
General Call Address Support .......................................... 192
General Purpose Register File............................................ 22
I
I2C (MSSP Module)
ACK Pulse......................................................... 189, 190
Addressing ................................................................ 190
Read/Write Bit Information (R/W Bit) ........................ 190
Reception.................................................................. 190
Serial Clock (RC3/SCK/SCL).................................... 190
Slave Mode ............................................................... 189
Transmission............................................................. 190
I2C Master Mode Reception.............................................. 198
I2C Master Mode Repeated Start Condition Timing.......... 197
I2C Module
Acknowledge Sequence Timing................................ 201
Baud Rate Generator................................................ 195
DS41291E-page 317
PIC16F882/883/884/886/887
RETURN ................................................................... 237
RLF ........................................................................... 238
RRF........................................................................... 238
SLEEP ...................................................................... 238
SUBLW ..................................................................... 238
SUBWF ..................................................................... 239
SWAPF ..................................................................... 239
XORLW ..................................................................... 239
XORWF..................................................................... 239
Summary Table......................................................... 232
INTCON Register ................................................................ 31
Inter-Integrated Circuit. See I2C
Internal Oscillator Block .................................................... 256
INTOSC
Specifications.................................................... 257
Internal Sampling Switch (RSS) Impedance ...................... 107
Internet Address................................................................ 323
Interrupts ........................................................................... 220
ADC .......................................................................... 103
Associated Registers ................................................ 222
Context Saving.......................................................... 223
Interrupt-on-Change.................................................... 47
PORTB Interrupt-on-Change .................................... 221
RB0/INT .................................................................... 220
Timer0 ....................................................................... 221
TMR1 .......................................................................... 78
INTOSC
Specifications ............................................................ 256
INTOSC Specifications ............................................. 256, 257
IOCB Register ..................................................................... 49
L
Load Conditions ................................................................ 254
M
Master Mode ..................................................................... 193
Master Mode Support........................................................ 193
Master Synchronous Serial Port. See MSSP
MCLR ................................................................................ 213
Internal ...................................................................... 213
Memory Organization.......................................................... 21
Data ............................................................................ 22
Program ...................................................................... 21
Microchip Internet Web Site .............................................. 323
Migrating from other PICmicro Devices ............................ 313
MPLAB ASM30 Assembler, Linker, Librarian ................... 242
MPLAB ICD 2 In-Circuit Debugger.................................... 243
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 243
MPLAB Integrated Development Environment Software .. 241
MPLAB PM3 Device Programmer..................................... 243
MPLAB REAL ICE In-Circuit Emulator System................. 243
MPLINK Object Linker/MPLIB Object Librarian ................ 242
MSSP ................................................................................ 179
Block Diagram (SPI Mode) ....................................... 183
I2C Mode. See I2C
SPI Mode .................................................................. 183
SPI Mode. See SPI
MSSP Module
Control Registers ...................................................... 179
I2C Operation ............................................................ 189
SPI Master Mode ...................................................... 185
SPI Slave Mode ........................................................ 186
Multi-Master Communication, Bus Collision and
Bus Arbitration .......................................................... 203
Multi-Master Mode ............................................................ 203
DS41291E-page 318
O
OPCODE Field Descriptions............................................. 231
OPTION Register................................................................ 30
OPTION_REG Register...................................................... 75
OSCCON Register.............................................................. 62
Oscillator
Associated Registers ............................................ 72, 80
Oscillator Module ................................................................ 61
EC............................................................................... 61
HFINTOSC ................................................................. 61
HS............................................................................... 61
INTOSC ...................................................................... 61
INTOSCIO .................................................................. 61
LFINTOSC .................................................................. 61
LP ............................................................................... 61
RC .............................................................................. 61
RCIO........................................................................... 61
XT ............................................................................... 61
Oscillator Parameters ....................................................... 256
Oscillator Specifications.................................................... 255
Oscillator Start-up Timer (OST)
Specifications ........................................................... 259
Oscillator Switching
Fail-Safe Clock Monitor .............................................. 71
Two-Speed Clock Start-up.......................................... 69
OSCTUNE Register............................................................ 66
P
P1A/P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM (ECCP)............................................ 132
Packaging ......................................................................... 301
Marking ............................................................. 301, 302
PDIP Details ............................................................. 303
PCL and PCLATH............................................................... 37
Stack........................................................................... 37
PCON Register ........................................................... 36, 215
PICSTART Plus Development Programmer..................... 244
PIE1 Register...................................................................... 32
PIE2 Register...................................................................... 33
Pin Diagram
PIC16F883/886, 28-pin (PDIP, SOIC, SSOP) .............. 3
PIC16F883/886, 28-pin (QFN)...................................... 4
PIC16F884/887, 40-Pin (PDIP) .................................... 6
PIC16F884/887, 44-pin (QFN)...................................... 8
PIC16F884/887, 44-pin (TQFP).................................. 10
Pinout Descriptions
PIC16F883/886 .......................................................... 16
PIC16F884/887 .......................................................... 18
PIR1 Register ..................................................................... 34
PIR2 Register ..................................................................... 35
PORTA ............................................................................... 39
Additional Pin Functions ............................................. 40
ANSEL Register ................................................. 40
Ultra Low-Power Wake-up............................ 40, 41
Associated Registers .................................................. 46
Pin Descriptions and Diagrams .................................. 42
RA0............................................................................. 42
RA1............................................................................. 43
RA2............................................................................. 43
RA3............................................................................. 44
RA4............................................................................. 44
RA5............................................................................. 45
RA6............................................................................. 45
RA7............................................................................. 46
Specifications ........................................................... 257
PIC16F882/883/884/886/887
PORTA Register ................................................................. 39
PORTB................................................................................ 47
Additional Pin Functions ............................................. 47
ANSELH Register ............................................... 47
Weak Pull-up ...................................................... 47
Associated Registers .................................................. 52
Interrupt-on-Change.................................................... 47
P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM+ (ECCP+).................................. 47
Pin Descriptions and Diagrams................................... 50
RB0 ............................................................................. 50
RB1 ............................................................................. 50
RB2 ............................................................................. 50
RB3 ............................................................................. 50
RB4 ............................................................................. 51
RB5 ............................................................................. 51
RB6 ............................................................................. 51
RB7 ............................................................................. 51
PORTB Register ................................................................. 48
PORTC ............................................................................... 53
Associated Registers .................................................. 56
P1A.See Enhanced Capture/Compare/
PWM+ (ECCP+) ................................................. 53
RC0............................................................................. 54
RC1............................................................................. 54
RC2............................................................................. 54
RC3............................................................................. 55
RC3 Pin..................................................................... 190
RC4............................................................................. 55
RC5............................................................................. 55
RC6............................................................................. 56
RC7............................................................................. 56
Specifications............................................................ 257
PORTC Register ................................................................. 53
PORTD ............................................................................... 57
Associated Registers .................................................. 58
P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM+ (ECCP+).................................. 57
RD0, RD1, RD2, RD3, RD4 ........................................ 58
RD5............................................................................. 58
RD6............................................................................. 58
RD7............................................................................. 58
PORTD Register ................................................................. 57
PORTE................................................................................ 59
Associated Registers .................................................. 60
RE0 ............................................................................. 60
RE1 ............................................................................. 60
RE2 ............................................................................. 60
RE3 ............................................................................. 60
PORTE Register ................................................................. 59
Power-Down Mode (Sleep) ............................................... 226
Power-on Reset (POR) ..................................................... 213
Power-up Timer (PWRT) .................................................. 213
Specifications............................................................ 259
Precision Internal Oscillator Parameters........................... 257
Prescaler
Shared WDT/Timer0 ................................................... 74
Switching Prescaler Assignment................................. 74
Program Memory ................................................................ 21
Map and Stack ............................................................ 21
Map and Stack (PIC16F883/884) ............................... 21
Map and Stack (PIC16F886/887) ............................... 21
Programming, Device Instructions .................................... 231
PSTRCON Register .......................................................... 146
Pulse Steering................................................................... 146
R
RCREG............................................................................. 158
RCSTA Register ............................................................... 161
Reader Response............................................................. 324
Read-Modify-Write Operations ......................................... 231
Register
RCREG Register ...................................................... 167
Registers
ADCON0 (ADC Control 0) ........................................ 104
ADCON1 (ADC Control 1) ........................................ 105
ADRESH (ADC Result High) with ADFM = 0) .......... 106
ADRESH (ADC Result High) with ADFM = 1) .......... 106
ADRESL (ADC Result Low) with ADFM = 0)............ 106
ADRESL (ADC Result Low) with ADFM = 1)............ 106
ANSEL (Analog Select) .............................................. 40
ANSELH (Analog Select High) ................................... 48
BAUDCTL (Baud Rate Control)................................ 162
CCP1CON (Enhanced CCP1 Control) ..................... 124
CCP2CON (CCP2 Control) ...................................... 125
CM1CON0 (C1 Control) ............................................. 88
CM2CON0 (C2 Control) ............................................. 89
CM2CON1 (C2 Control) ............................................. 91
CONFIG1 (Configuration Word Register 1).............. 210
CONFIG2 (Configuration Word Register 2).............. 211
ECCPAS (Enhanced CCP Auto-shutdown Control) . 142
EEADR (EEPROM Address) .................................... 112
EECON1 (EEPROM Control 1) ................................ 113
EEDAT (EEPROM Data) .......................................... 112
EEDATH (EEPROM Data) ....................................... 112
INTCON (Interrupt Control) ........................................ 31
IOCB (Interrupt-on-Change PORTB).......................... 49
OPTION_REG (OPTION)..................................... 30, 75
OSCCON (Oscillator Control)..................................... 62
OSCTUNE (Oscillator Tuning).................................... 66
PCON (Power Control Register)................................. 36
PCON (Power Control) ............................................. 215
PIE1 (Peripheral Interrupt Enable 1) .......................... 32
PIE2 (Peripheral Interrupt Enable 2) .......................... 33
PIR1 (Peripheral Interrupt Register 1) ........................ 34
PIR2 (Peripheral Interrupt Request 2) ........................ 35
PORTA ....................................................................... 39
PORTB ....................................................................... 48
PORTC ....................................................................... 53
PORTD ....................................................................... 57
PORTE ....................................................................... 59
PSTRCON (Pulse Steering Control)......................... 146
PWM1CON (Enhanced PWM Control) ..................... 145
RCSTA (Receive Status and Control) ...................... 161
Reset Values ............................................................ 217
Reset Values (special registers)............................... 219
Special Function Register Map
PIC16F883/884 ............................................ 23, 24
PIC16F886/887 .................................................. 25
Special Function Registers......................................... 22
Special Register Summary
Bank 0 ................................................................ 26
Bank 1 ................................................................ 27
Bank 2 ................................................................ 28
Bank 3 ................................................................ 28
SRCON (SR Latch Control)........................................ 93
DS41291E-page 319
PIC16F882/883/884/886/887
SSPCON (MSSP Control 1)...................................... 181
SSPCON2 (SSP Control 2)....................................... 182
SSPMSK (SSP Mask) ............................................... 208
SSPSTAT (SSP Status) ............................................ 180
STATUS ...................................................................... 29
T1CON ........................................................................ 79
T2CON ........................................................................ 82
TRISA (Tri-State PORTA) ........................................... 39
TRISB (Tri-State PORTB) ........................................... 48
TRISC (Tri-State PORTC) .......................................... 53
TRISD (Tri-State PORTD) .......................................... 57
TRISE (Tri-State PORTE) ........................................... 59
TXSTA (Transmit Status and Control) ...................... 160
VRCON (Voltage Reference Control) ......................... 97
WDTCON (Watchdog Timer Control)........................ 225
WPUB (Weak Pull-up PORTB) ................................... 49
Reset................................................................................. 212
Revision History ................................................................ 313
S
SCK................................................................................... 183
SDI .................................................................................... 183
SDO .................................................................................. 183
Serial Clock, SCK.............................................................. 183
Serial Data In, SDI ............................................................ 183
Serial Data Out, SDO........................................................ 183
Serial Peripheral Interface. See SPI
Shoot-through Current ...................................................... 144
Slave Mode General Call Address Sequence................... 192
Slave Select Synchronization............................................ 186
Slave Select, SS ............................................................... 183
Sleep ................................................................................. 226
Wake-up.................................................................... 226
Wake-up Using Interrupts ......................................... 226
Software Simulator (MPLAB SIM)..................................... 242
SPBRG.............................................................................. 163
SPBRGH ........................................................................... 163
Special Event Trigger........................................................ 102
Special Function Registers ................................................. 22
SPI
Master Mode ............................................................. 185
Serial Clock ............................................................... 183
Serial Data In ............................................................ 183
Serial Data Out ......................................................... 183
Slave Select .............................................................. 183
SPI clock ................................................................... 185
SPI Mode .................................................................. 183
SPI Bus Modes ................................................................. 188
SPI Mode
Associated Registers with SPI Operation ................. 188
Bus Mode Compatibility ............................................ 188
Effects of a Reset...................................................... 188
Enabling SPI I/O ....................................................... 184
Operation .................................................................. 183
Sleep Operation ........................................................ 188
SPI Module
Slave Mode ............................................................... 186
Slave Select Synchronization ................................... 186
Slave Synchronization Timing................................... 186
Slave Timing with CKE = 0 ....................................... 187
Slave Timing with CKE = 1 ....................................... 187
SRCON Register................................................................. 93
SS ..................................................................................... 183
SSP
SSPBUF.................................................................... 185
SSPSR ...................................................................... 185
DS41291E-page 320
T
T1CON Register ................................................................. 79
T2CON Register ................................................................. 82
Thermal Considerations.................................................... 253
Time-out Sequence .......................................................... 215
Timer0................................................................................. 73
Associated Registers .................................................. 75
External Clock............................................................. 74
Interrupt ...................................................................... 75
Operation .............................................................. 73, 76
Specifications ........................................................... 260
T0CKI ......................................................................... 74
Timer1................................................................................. 76
Associated Registers .................................................. 80
Asynchronous Counter Mode ..................................... 77
Reading and Writing ........................................... 77
Interrupt ...................................................................... 78
Modes of Operation .................................................... 76
Operation During Sleep .............................................. 78
Oscillator..................................................................... 77
Prescaler .................................................................... 77
Specifications ........................................................... 260
Timer1 Gate
Inverting Gate ..................................................... 77
Selecting Source .......................................... 77, 91
SR Latch............................................................. 92
Synchronizing COUT w/Timer1 .......................... 91
TMR1H Register ......................................................... 76
TMR1L Register.......................................................... 76
Timer2
Associated Registers .................................................. 82
Timers
Timer1
T1CON ............................................................... 79
Timer2
T2CON ............................................................... 82
Timing Diagrams
A/D Conversion......................................................... 265
A/D Conversion (Sleep Mode) .................................. 265
Acknowledge Sequence Timing ............................... 201
Asynchronous Reception.......................................... 158
Asynchronous Transmission..................................... 154
Asynchronous Transmission (Back to Back) ............ 154
Auto Wake-up Bit (WUE) During Normal Operation . 168
Auto Wake-up Bit (WUE) During Sleep .................... 169
Automatic Baud Rate Calibration.............................. 167
Baud Rate Generator with Clock Arbitration............. 195
BRG Reset Due to SDA Arbitration .......................... 205
Brown-out Reset (BOR)............................................ 258
Brown-out Reset Situations ...................................... 214
Bus Collision
Start Condition Timing ...................................... 204
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 206
Bus Collision During a Repeated Start
Condition (Case2)............................................. 206
Bus Collision During a Start Condition (SCL = 0) ..... 205
PIC16F882/883/884/886/887
Bus Collision During a Stop Condition ...................... 207
Bus Collision for Transmit and Acknowledge............ 203
CLKOUT and I/O....................................................... 257
Clock Timing ............................................................. 255
Comparator Output ..................................................... 83
Enhanced Capture/Compare/PWM (ECCP) ............. 261
EUSART Synchronous Receive (Master/Slave) ....... 266
EUSART Synchronous Transmission
(Master/Slave) .................................................. 266
Fail-Safe Clock Monitor (FSCM) ................................. 72
Full-Bridge PWM Output ........................................... 137
Half-Bridge PWM Output .................................. 135, 144
I2C Bus Data ............................................................. 270
I2C Bus Start/Stop Bits.............................................. 269
I2C Master Mode First Start Bit Timing ..................... 196
I2C Master Mode Reception Timing.......................... 200
I2C Master Mode Transmission Timing..................... 199
I2C Module
Bus Collision
Transmit Timing ........................................ 203
INT Pin Interrupt........................................................ 222
Internal Oscillator Switch Timing................................. 68
Master Mode Transmit Clock Arbitration................... 202
PWM Auto-shutdown
Auto-restart Enabled ......................................... 143
Firmware Restart .............................................. 143
PWM Direction Change ............................................ 138
PWM Direction Change at Near 100% Duty Cycle ... 139
PWM Output (Active-High)........................................ 133
PWM Output (Active-Low) ........................................ 134
Repeat Start Condition.............................................. 197
Reset, WDT, OST and Power-up Timer ................... 258
Send Break Character Sequence ............................. 170
Slave Synchronization .............................................. 186
SPI Master Mode (CKE = 1, SMP = 1) ..................... 267
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram .......................... 185
SPI Mode Timing (Slave Mode with CKE = 0) .......... 187
SPI Mode Timing (Slave Mode with CKE = 1) .......... 187
SPI Slave Mode (CKE = 0) ....................................... 268
SPI Slave Mode (CKE = 1) ....................................... 268
Stop Condition Receive or Transmit ......................... 202
Synchronous Reception (Master Mode, SREN) ....... 174
Synchronous Transmission....................................... 172
Synchronous Transmission (Through TXEN) ........... 172
Time-out Sequence
Case 1 .............................................................. 216
Case 2 .............................................................. 216
Case 3 .............................................................. 216
Timer0 and Timer1 External Clock ........................... 260
Timer1 Incrementing Edge.......................................... 78
Two Speed Start-up .................................................... 70
Wake-up from Interrupt ............................................. 227
Timing Parameter Symbology........................................... 254
Timing Requirements
I2C Bus Data ............................................................. 271
I2C Bus Start/Stop Bits ............................................. 270
SPI Mode .................................................................. 269
TRISA ................................................................................. 39
TRISA Register ................................................................... 39
TRISB ................................................................................. 47
TRISB Register ................................................................... 48
TRISC ................................................................................. 53
TRISC Register ................................................................... 53
TRISD ................................................................................. 57
TRISD Register................................................................... 57
TRISE ................................................................................. 59
TRISE Register................................................................... 59
Two-Speed Clock Start-up Mode........................................ 69
TXREG ............................................................................. 153
TXSTA Register................................................................ 160
BRGH Bit .................................................................. 163
U
Ultra Low-Power Wake-up................................ 16, 18, 40, 41
V
Voltage Reference (VR)
Specifications ........................................................... 262
Voltage Reference. See Comparator
Voltage Reference (CVREF)
Voltage References
Associated Registers.................................................. 97
VP6 Stabilization ........................................................ 94
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 168
Wake-up Using Interrupts ................................................. 226
Watchdog Timer (WDT).................................................... 224
Associated Registers................................................ 225
Clock Source ............................................................ 224
Modes....................................................................... 224
Period ....................................................................... 224
Specifications ........................................................... 259
Waveform for Slave Mode General Call
Address Sequence ................................................... 192
WCOL ............................................................... 196, 198, 201
WCOL Status Flag............................................ 196, 198, 201
WDTCON Register ........................................................... 225
WPUB Register................................................................... 49
WWW Address ................................................................. 323
WWW, On-Line Support ..................................................... 12
DS41291E-page 321
PIC16F882/883/884/886/887
NOTES:
DS41291E-page 322
PIC16F882/883/884/886/887
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
DS41291E-page 323
PIC16F882/883/884/886/887
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Device: PIC16F882/883/884/886/887
Questions:
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4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS41291E-page 324
PIC16F882/883/884/886/887
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
Temperature
Range:
I
E
Package:
ML
P
PT
SO
SP
SS
Pattern:
= -40C to +85C
= -40C to +125C
=
=
=
=
=
=
(Industrial)
(Extended)
Note 1:
2:
DS41291E-page 325
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01/02/08
DS41291E-page 326