RF circuit design: Basics

Akira Matsuzawa
Tokyo Institute of Technology
1

Contents
Building blocks in RF system and basic
performances
Device characteristics in RF application
Low noise amplifier design
Mixer design
Oscillator design

Basic RF circuit block

RF systems are composed of limited circuits blocks.
LNA, Mixer, and Oscillator will be discussed in my talk.
Receiver

1)
Low
Impedance Noise
Matching Amp.

Transmitter

2) Mixer Filter

3) Oscillator
Power
Amp.

Basic functions of RF building blocks

Amplifier, frequency converter (mixer +oscillator), and filer
are basic function blocks in RF system.

2) Mixer+ Oscillator
Undesired
Down conversion
dB

3) Filter

dB

Desired

1) Amplifier

Frequency conversion

Log (f)

Up conversion

Log (f)

RF Amplifier
Gain: Amplify small signal or generate large signal.
Noise: Smaller noise and larger SNR.
Linearity: Smaller non-linearity.
Non-linearity generates undesired frequency components.

vout (t ) = 1vin (t ) + 2 vin2 (t ) + 3vin3 (t ) + .....

(cos(1t ) + cos(2t ))2 = 2 + cos(21t ) + cos(22t ) + cos((1 2 )t ) + cos((1 + 2 )t )

(cos(1t ) + cos(2t ))

1
1
= cos((21 2 )t ) + cos((22 1 )t ) + ....
2
2
5

Input and output characteristics

Distortion and noise are important factors in RF amplifier, as well as power and gain.
Pout
IP3

OIP3
1dB
Pout
(1dB)
IMD3

Fundamental
SFDR

Slope=1

Noise
Floor

SNR min

Slope=3

SNR min

SFDR
BDR
NoiseMDS
Floor

Pin
CP1dB

IIP3
6

Dynamic range
Noise Floor = 174dBm + NF + 10 log BW
kT limitation

Bandwidth

SFDR: Spurious free dynamic range

The input power range over which third order inter-modulation products
are below the minimum detectable signal level.

SFDR =

2
(IIP3 Noise Floor ) SNR min
3

BDR: Blocking dynamic range

BDR = P1dB Noise Floor SNR min

MDS: Minimum detectable signal level= Noise Floor +SNRmin

Non-linearity
CP1dB: The input level at which the small signal gain has dropped by 1dB.
CP1dB = 0.145

1
3

IMD3: The third order inter modulation term

IP3: The metric third order intercept point. It is the point where the amplitude of
third order inter modulation is equal to the that of fundamental.

AIP 3 =

4 1
3 3

IIP3: Input referred intercept point

OIP3: Output referred intercept point

Pout IMD3 = 2 (IIP3 Pin )

MOS transistor
Intrinsic gate voltage and gm are the most important factors in RF CMOS.

Drain
Gate

G
Body

Source
MOS Transistor

rg vg Cgd
Cgs

rds

gmvg

D
Cds
S, B

Equivalent Circuit

Cutoff frequency: fT
For higher fT, increase gm and decrease Cin.
Ii

Io

fT: Frequency at which the current gain is unity.

G
D
Cin

Ii

Vi

gmVi

Ii = Iio sin(t )
Iio
Vi =
cos(t )
Cin

Input current
Gate voltage

gmIio cos(t )
Io = gmVi =
Cin

gm
fT =
2Cin

Output current

Proportional to gm
Inversely proportional to Cin

10

Amplifier gain
For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance
Ig
rs
Vs Vg

Id
Cin

Log (G)

g =

gmVg

ro

1
rsCin
G

G=gmr0

T =
T r 0

rs

0 =
For the larger gain

gmro
r0
= T
rsCin
rs

Fundamentally larger gmr0 G gmro

Higher fT and lower rs

gm
Cin

Ids
Veff

Log (f)

ro

Veff is difficult to reduce

Larger Ids or ro
Larger Q

Q
Qro = Q0L =
0C

Distortion and Cin increase

11

Characteristics of gm (Basic)
Gm is proportional to the Ids and inversely proportional to the Veff.
Veff is proportional to square root of Ids and inversely proportional to
square root of (W/L) ratio.
Square law region

COX W

COX W

(Vgs VT ) =
Veff
2n L
2n L
dI
COX W
gm ds =
Veff
dVgs
n L

Ids =

gm =

2 COX W
Ids
n L

Veff

1
Ids
gm
,
=
gm =
Veff Ids Veff

2
2

Veff =

Ids
= L Jds
W

2n

1 L

Ids
Cox W

Scaling

W/L ratio

Veff is proportional to square root of drain current density.

12

Non-ideal effects to square low region

At larger Veff and lower Veff, two non-ideal effects are not negligible .
Sub-threshold region

Vgs
Ids = Iso exp
nU T
Ids
gm =
nU T

25.083

( Weak inversion)

gm
1
eff( 0.4 , 10 , Veff)
=
eff( 0.2 , 5 , Veff)
Ids nU T
Gm/Ids (S/A)

Low Veff

30

gm
1
=
= const
Ids nUT

25

20

gm
2
=
Ids Veff

15

10

High Veff

Mobility degradation

, 0 + 0
1 + Veff
vcL

1.302

0.2
0.2

0.2

0.4
Veff

Veff (V)

0.6

0.8
1

This effect becomes larger at large Veff and short channel length.
13

Distortion
Lower Veff gives higher gm, bur results in higher distortion.
To obtain lower distortion ( higher IIP3), we must increase Veff.
Higher gm and lower distortion means higher Ids.
3

1 d 3 Ids
+ a3
6 dVeff 3

4 a1
IIP 3 =
3 a3

L=0.1um
L=0.2um
L=0.4um
IIP3

gm/Ids (S/A)

100

10

1
-0.1

Veff (V)

10

IIP3 (V)

Ids = a1Veff + a 2Veff + a 3Veff

2

0.1
0

0.1

0.2

0.3

0.4

0.5

Veff (V)
14

LC resonator
LC resonator can be regarded as resistance at the resonance frequency.

C
L

Substrate

0 =

r0

1
LC

Q
ro = Q 0 L =
0C
15

Substrate effect
Substrate should be treated as resistive network.
This substrate resistance causes RF power loss and noise generation.
Shielding can reduce this effect.
Gate

RF power loss and noise generation

Gate
PAD

S
D
S
D
S

S
D
S
D
S

PAD

Shield layer

16

Power loss in substrate

Very low resistance or high resistance realizes low power loss.
C

Gp

Rp

Higher C and moderate Rsub

results in higher power loss.

Cp

Equivalent

1
R p

= C

1 +

1 +

1
R pC

Gp(mS)

Cp(pF)
1

MOS: 10cm
GaAs: 1Gcm

10

100
Rp(

0.1
1K

10K

17

GHz operation by CMOS

The cutoff frequency of MOS becomes higher than that of Bipolar.
Over several GHz operations have attained in CMOS technology
0.13um
100G

0.18um
0.25um

50G

Frequency (Hz)

0.35um

fT : CMOS
fT : Bipolar (w/o SiGe)
fT /10 (CMOS )

20G

RF circuits

10G
5G

Cellular
Phone

CDMA

5GHz W-LAN

fT /60 (CMOS )

gm
fT
2Cin
vsat
fTpeak
2Leff

Digital circuits

2G
1G

IEEE 1394
D R/C for HDD

500M
200M
100M

1995

2000

2005

Year
18

Effect of parasitic capacitance to fT

fT of actual circuit is reduced by a parasitic capacitance.
There is an optimum gate width to obtain highest fT.
10
60
6 .10
10
5.786 .10

gm
fT
2 (Cgs + Cgd + Cp )
Cin

Vi

4 .10
4010

fti 0.2
, W , 5 .10
gmVi

,0

fti 0.2 , W , 5 .10

, 0.1 .10

12

fti 0.2 , W , 5 .10

, 0.5 .10

12

fT (GHz)

Cp

Ids=5mA
L=0.2um

Cp=0

Cp=0.1pF

(1)
10
2 .1020

(2)

Cin=Cgs+Cgd
Cp=0.5pF
Region(1); Increased by increasing1.576
gm.109
Region(2); Decreased by increasing Cin

00 0
10

200

400

600
W

W(um)

800

1000
1 .10

19

fT: MOS vs. Bipolar

Even if fT of MOS is the same as that of Bipolar,
fT of MOS is easily lowered by a parasitic capacitance.
Because, gm of MOS is to of that of Bipolar at the same current.
Small parasitic capacitance is a key for RF CMOS design.
MOS

gm
fT
2Cin

Ids
gm
Veff

2
Veff min = 2nU T

Ic
gm
UT
UT

n: 1.4

Veff/2: 50-100mV
(actual ckt.)

Bipolar

kT
26mV
q

gmCMOS <

1 1
, gmBip Same operating current
2 4

CinCMOS <

1 1
, CinBip
2 4

Same fT
20

VT mismatch
VT mismatch degrades accuracy; ADC, OP amp, and Mixer.
Larger gate area is needed for small VT mismatch.
Scaling and proper channel structure improves mismatch.

VT (:mV)

15

Tox
VT
LW

0.4um Nch

Larger gate area

0.13um Nch Boron w. Halo*

Tox Scaling

10

0.4um Pch
Channel engineering

0.13um Nch In w/o Halo*

0

0.1

0.2

0.3

0.4

1
( m 1 )
LW

0.5

0.6

0.7

0.8

* Morifuji, et al., IEDM 2000.

21

VT mismatch: Fluctuation of doping

Courtesy of Prof. Taniguchi, Osaka Univ.

VT =

Qdepl
Cox

= Atox

LWd depl N A

Q d depl
- - -- - - - - --

LW
1
NA

= Atox

NA
LW

AVT

tox
LW

AVT = 1V

ddepl
L = W = 0.25 m, tox = 5nm
VT = 20mV

T.Mizuno, J.Okamura and A.Toriumi, Experimental study o f threshold voltage

fluctuation due to statistical variation of channel dopant number in MOSFETs,
IEEE Trans. On Electron Devices, ED-41, 2216 (1994)
22

1/f noise
1/f noise of MOS is larger than that of bipolar.
For the lower 1/f noise, the larger gate area is needed.

Svf f
,
LW f

Svf Tox2
Nch 0.4um/1.0um

1E-13
W/L=800/0.4
Vdd=3V
Id=1mA

1E-14
1E-15

nMOS
1E-16
1E-17

pMOS

1E-18
1E-19
1E+02

Bipolar
1E+03

1E+04

1E+05

1E+06

Frequency (Hz)

1E+07

Input referred noise voltage (V2/Hz)

Input referred noise voltage (V2/Hz)

Nch/Pch 0.4um
1E-13

nMOS
Vdd=3V
Id=1mA

1E-14
1E-15

L=0.4um

1E-16
1E-17

L=1.0um

Vnf2 =

1E-18

Bipolar
1E-19
1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

Frequency (Hz)
23

Noise figure: General

The lower Rnv and Gni realizes the better for a lower noise figure.
Zs

Vn,rs

Vng
Noiseless
Circuit

Ing

Vs

Zs = Rs + jXs

Vng 2 = 4kTRnv , Ing 2 = 4kTGni

Vn2,rs + (Vng + ZsIng )

F=

Rsopt =

Vn2,rs
Vng
Rnv
=
Gni
Ing

= 1+

Rnv
+
Rs

Zs Gni
Rs

1+

Rnv
+ RsGni
Rs

F min 1 + 2 RnvGni
24

Noise figure: MOS transistor

Rnv
F 1+
+ RsGni
Rs
Rnv = Rg + Rgs

W
1
Rg = Rsr tot
L 3N 2

1
gm 0
+ Rs
F 1+

Rs5 gm
5 T

1
Rgs
5 gm

Rsopt

Gni

gm 0

5 T

1 T
1
=

gm 0 Cgs 0

F min 1+ 2

0
T
25

Low noise amplifier design

Narrowband LNA uses inductor degeneration for impedance matching.
Impedance matching

1
gm
Zin s(Ls + Lg ) +
+
L s T L s
sCgs Cgs
0 =

1
Cgs (Ls + Lg )
Z0

M2
Lg

rg
M1
Cpi

Rsub

Cgs rgs

Ls

26

Low NF design
rgs + rg
rgs + rg
0
F 1+
+ 4gmZ 0 1 +
Z0
Z0
T
2

rgs

Low noise figure

rg = Rsr

1) Lower the gate resistance

Reduce parasitic capacitance

Use shield technique to the input bonding PAD.

4) Increase Z0, if possible.

(Veff )
1
rgs

5 gm 10 Ids

Wtot
L

Rsr: Sheet resistance

NThe # of division
Divide the gate

2) Reduce substrate loss

Use high resistive substrate, if possible.

Wtot 1
L 3N 2

rg = Rsr

Dived the gate or lower the gate sheet resistance

3) Increase drain current

1
5 gm

S
D
S

D
S
D
S

27

Ids and Veff optimization

Adjust the Ids and Veff for optimization of gain, noise and distortion.
Dynamic range of LNA is proportional to Ids.

IIP3LNA
DRLNA
gmZ 0Veff IdsZ 0 IIP3 Veff
F 1
Higher Ids
Lower Ids

NF
dB
Gain

3rd distortion
Veff

Veff

Ids
W
28

NF progress in MOS LNA

NF of MOS LNA is reaching 1dB.
8.0
7.0
6.0

NF (dB)

5.0
4.0
3.0
2.0
1.0
0.0
1

0.5

0.35

0.25

0.1

Gate length (m)

29

Mixer
Mixer converts frequency, but image signal is converted to the same frequency.

Vs = As cos(st )

Vs

Vo

Vo = As

cos((s LO )t )

If VLO>>4Veff (Full swing)

VLO

VLO = ALO cos(LOt )

RF spectrum

IF spectrum

FLO
dB

dB

Fimage
Fdes

Freq

Freq
FIF FIF

FIF
30

Image-reject mixers
The quadrature mixing realizes image-suppression.
Gain and phase matching is needed.
LPF
Vin (t)

45

cos(LOt )
+

sin (LOt )
LPF

Vout(t)

45

Vin (t ) = Ades cos(dest ) + Aim cos(imt )

Vout (t ) = AdesAc cos(IFt ) + AimAcIR cos(IFt )
Ac: Conversion gain, IR: Image rejection
IR=0 if I/Q phase difference is 90 and Channel conversion gains are equal.
31

Gain mismatch and phase error

Pspur 1 + 2 2 cos
=
Pdesired 1 + 2 + 2 cos

: Gain ratio

:Phase error

A. Rofougaran, et al.,
IEEE J.S.C. Vol.33, No.4,
April 1998. PP. 515-534.

32

Passive FET mixer

MOS can realize a passive mixer easily.
Ultimately low power, but take care of isolation.
Passive FET mixer
Vin

Lo

Lo

Vo

Vo

Lo

Lo

Low power
High linearity
No 1/F noise
No conversion gain
No isolation, Bi-directional

Vin
33

Active mixers
Single balanced mixer

Double balanced mixer

Very small direct feed through and even order distortion

Vo

ZL

Lo

ZL
Vo
M2

M3

ZL
Vo

Lo
M2 M3

Lo

Vin
M1
Zs

ZL
Vo

M2 M3
Lo

Vin

Lo

Vin
M1
Zs

M1
Zs

34

Active mixer design

The larger Ids is needed for high dynamic range
and shorter switching time for low 1/f noise.
Mixer gain

Gmix =

gm1ZL , or =

2 ZL
Zs

when Zs is used
R : Resistive component in ZL

L
Thermal noise v = 8kTRL1 + 2IRL + gm1RL 8kTR 2gm1
L
ALO

v on2

Veff
2
2
2
2

kT
kT
SSBvin =

2
Ids
gm1
2

1
L
gm
R

A larger dynamic range needs larger current

IIP3 Veff
1/F noise
2
on

1) Switch transistor (M2, M3)

vn , o =

4Ts
vn , sw
TLO

1
vn2 , sw WL

1
Cgs

Ts

TLO

Phase modulation

Shorter switching time or larger Ts/TLo ratio

2) Load transistors

Directly produces
35

Oscillator
There is an optimum Ids for low phase noise.
Vdd
Vo

Vo

-1/gm
C

r0

-1/gm

Vc

1) Amplitude condition
M3

M2

Oscillation
amplitude

Vb

I M1

Vosc =

ro = Q 0 L =

4 Iro

Headroom
limit

Vdd VddoC
=
Iopt =
2 ro
Q

Q
0C

2Vdd

(a)
2) Oscillation condition

gm 2,3 >

2
,
ro

I>

oCVeff , 2,3
Q
36

Phase noise of oscillator

Phase-frequency relation and resonator characteristics determine phase noise.

v(t ) = A cos[ 0t + (t )]

1
2QL
=
Bw 0
R
Z ( j )

d
= j
dt

S (m) = m2 S (m )

S (m)

:Noise spectrum density

on offset angular frequency

S (m )

:Noise spectrum density

on phase

m =
Bw

0.7R

d =

2QL

m
Bw

2QL

0
2

0
S (m )
S (m) =
2QL
2

S (m )

: Offset angular frequency

Phase error between in and out

:Noise spectrum density
on phase error

m < Bw
2

0 1
0
2 S (m ) =
S (m )
S (m) =
2QL m
2QLm
37

Phase noise of oscillator

Z ( 0 + m ) j
L

-1/gm

-1/gm

r0
0L

(Filter action)

0
vn2
in2
2

=
Z = 4kTro
f f
2Qm

R
0.7R

Q=

m << 0

r 0 0
Z ( 0 + m )
2Qm

1
2Q
=
Bw 0
Z ( j )

r0

0L
m
2
0

Bw

Noise spectrum density

2kT
L{m} = 10 log
Psig
Phase noise

2Qm

38

Frequency characteristics of Phase noise in oscillator

1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.

Phase noise spectrum

S (m )

0
1
a 3

2QL m

-9dB/oct
(Slope =-3)

S (m ) =

0 2 FkT 1

2
2
L
Q

Ps m

(Slope=-2)

Thermal

co

Bw =

S (m ) =

2 FkT
Ps

2 FkT
Ps

-6dB/oct
1/f noise

1 0
S (m )
S (m) =
L
m
2
Q

Thermal

2QL

m
39

Up and down converted noise

Noises around N*fo are up and down converted to fo.

Vnoise (V / Hz )

2o

3o

Noise
shaping

P (dBm)

Up-conv.

Down-conv.

40

FoM and minimum phase noise

FoM is basically proportional to Q2.
2

f 0
1
FoM =
fm L( fm)VddI
1 1
L ( fm ) = 2
2 Q

Fm: Offset frequency

L(fm): Phase noise at offset freq.

fo FkT 1 1

= 2
fm PRF 2 Q

8roI
8
F = 2+
+ ro gm1
Vo
9

fo FkT

2
fm Vo
2ro

Iopt =

Vdd
2 ro

4 Q2
1
FoM =
Q2
kT 2 + 4 + 32 Vdd
9
Veff ,1

F: Noise factor

VddoC
Q

Vdd
=
2QoLind

at Iopt

41

Oscillator design
Careful optimization reduces the oscillator phase noise.

oLind 1

2 fo

+
L min( fm) = kT

Vdd 2Q Vdd Veff ,1 fm

1
2
L min( fm) = kT
2 Iopt 2Q

Vo

2 fo
1

+

Vdd Veff ,1 fm
Iopt =

Vo

Vdd
2 ro

Phase noise

Oscillation
amplitude

VddoC
Q

2Vdd

Vdd
2QoLind
Iopt Bias current

Vc
C

M2
Vb

M3

I M1

Larger Vdd
Large Veff1, but take care of Vo reduction
Large L1, W1 to reduce 1/f noise
Enough W/L for M2, M3
Higher Q
Larger QLind for Lower Iopt
42

CMOS oscillator circuits

E. Hegazi, ISSCC 2001
Low power (gm is higher)

Basic

Low noise by filtering

Vo
Vo
Vo

Vo

Vc

Vo

Vo
L

Vc
Vc

Hi-Z at 2fo
Cs
Vb

Lx

Vb
Vb
(a)

Cx

(b)
(c)
43

Filtering of 2fo component in OSC.

Noise filtering of 2fo component reduces the OSC phase noise to -10dB.
E. Hegazi, ISSCC 2001

44

Oscillator phase noise progress

Phase noise in CMOS oscillator becomes lower than that of bipolar.
CMOS
Si-bipolar/BiCMOS

-90.0
[dBc/Hz](@GHz,10mW,600kHz)

SSB Phase Noise

SiGe-BiCMOS

-100.0
-110.0
-120.0
-130.0
-140.0
-150.0

1994 1995 1996 1997 1998 1999 2000 2001 2002

Year
45

Acknowledgment and references

Acknowledgment
I would like to thank Prof. Asad Abidi in UCLA for his advices.

References
Asad A. Abidi, Power-Conscious design of Wireless circuits and
systems, pp.665-695, Trade-offs in Analog Circuit Design, Kluwer
Academic Publishers, 2002. (Edited by Chris Toumanzou, George
Moschytz, and Barrie Gilbert)
Thomas. H. Lee, The design of CMOS RF ICs, Cambridge University
Press, Jan. 1998.
Bezad, Razavi, RF micro-electronics, Prentice Hall, Nov. 1999.
Domine Leenaerts, Johan van der Tang, and Ciero Vaucher, Circuit
Design for RF Transceivers, Kluwer Academic Publishers, 2001.
Charles Chien, Digital Radio Systems on A chip, Kluwer Academic
Publishers, 2001.
E. Hegazi, et. Al., A Filtering Technique to Lower Oscillator Phase
Noise, ISSCC 2001, 23.4, Feb. 2001.

46