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Compaq La-4117p r0.3 Schematics
Compaq La-4117p r0.3 Schematics
Compaq La-4117p r0.3 Schematics
Compal confidential
Schematics Document
Mobile AMD S1G3 CPU with ATI
RS880M(NB) & SB710(SB) core logic
3
2009-03-15
REV:0.3
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Compal Confidential
Thermal Sensor
ADM1032ARMZ
Page 6
Page 30
Fan conn
BANK 0, 1, 2, 3
Clock Generator
SLG8SP626VTR
Page 8, 9
Dual Channel
72QFN
DDR2-SO-DIMM X2
Page 15
Page 4, 5, 6, 7
USB conn x2
LVDS Panel
Interface Page
ATI RS880M
17
CRT
BT Conn
Page 16
DDR2 400MHz
HDMI
USB conn x1
PCI-E BUS*5
ATI SB710
Realtek
Mini-Card*2
8102E(10/100M) WLAN & WWAN
Page 27
Page 25
CardReader Socket
New Module
2
26
Page 17
SATA Master-2
SATA Slave
Express Card
FingerPrinter AES1610
page 35
USBx1
SATA Slave
Page 26
Page 31
USB WebCam
SATA Master-1
Module
Module
Page 26
MDC V1.5
3
Page 31
USB2.0 X12
4X PCI-E
CardReader
JMicron
JMB385-LGEZ0A
daughter board
Mini-Card WWAN
Page
A-Link Express II
Page 18
Page 31
LPC BUS
RJ45/11 CONN
daughter board
Page 34
Audio CKT
Page 25
Page 27
TPA6017A2
Page 28
KBC
ENE KB926-C0
Codec_IDT9271B7
Page 29
Page 33
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*SPDIF
*Headphone/Line Out L/R
*Stereo Mic L/R
*Volume Control
*Consumer IR
*USB x1
*DC JACK
LED
Page 24
P41
Int.KBD
Page 33
Multi-Bay HDD/ODD Option Connector
Page 24
RTC CKT.
Page 19
Consumer IR
Page 34
Power OK CKT.
Issued Date
Page 31
P35
Security Classification
Page 35
e-SATA Connector
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Page 36
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1.0/1.0a
Symbol Note :
Voltage Rails
X MEANS OFF
RP10@
Z ZZ
Layout Notes
PCB-Ripley MB
+5VS
RM10@
Z ZZ
PCB-Rachman UMA MB
DAZ=DAZ03Y00201
DAZ=DAZ03Y00101
+3VS
+1.5VS
power
plane
+0.9V
+VCCP
+5VALW
+CPU_CORE
+1.8V
+B
+3VALW
+VGA_CORE
+2.5VS
State
+1.8VS
+1.2VS
+0.9VGA
S1
S3
U3
RS780
RS780 R1
RS780R1@
RP11@
Z ZZ
RP@
Z ZZ
SMB_EC_CK2
DEVICE
HEX
ADDRESS
SMB_EC_DA2
DDR SO-DIMM 0
A0
10100000
I2C_CLK
DDR SO-DIMM 1
A4
10100100
I2C_DATA
D2
11010010
DDC_CLK0
DDC_DATA0
DDC_CLK1
EC SM Bus1 address
Device
HEX
Address
Smart Battery
16H
0001 011X b
24C16
A0H
1010 000X b
EC SM Bus2 address
Device
CPU
ADI1032-2 CPU
DDC_DATA1
SCL0
HEX
Address
98H
1001 100X b
SCL1
9AH
1001 101X b
SDA1
KB926
KB926
RS780M
RS780M
RS780M
SB700
SDA0
SB700
SCL2
SB700
SDA2
4
PCB-Ripley MB
SMB_EC_DA1
SCL3
SB700
SDA3
2007/08/02
Issued Date
X
X
X
X
X
X
X
X
X
BATT
V
X
X
X
X
X
X
X
X
SERIAL
EEPROM
V
X
X
X
X
X
X
X
X
THERMAL
SENSOR
CPU &
ADM1032
SODIMM
I / II
VCPU
V
ADM1032
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
X
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
CLK CHIP
X
X
X
X
X
V
X
X
X
Security Classification
RM@
Z ZZ
DAZ=DAZ09000102
INVERTER
PCB-Rachman UMA MB
DAZ=DAZ03Y00102
X76
SMB_EC_CK1
PCB-Ripley MB
DAZ=DAZ03Y00203
2.0
SOURCE
3
RM11@
Z ZZ
SB700 R1
SBR1@
1.1
S5 S4/AC
U15
SB700
S0
Title
MINI CARD
Slot 2
X
X
X
X
X
X
V
X
X
X76
PCB-Rachman UMA MB
DAZ=DAZ09100102
LCD
HDMI
X
X
V
X
X
X
X
X
X
X
X
X
V
X
X
X
X
X
G-Sensor
3
X
X
X
X
X
X
X
V
X
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VLDT CAP.
+1.2V_HT
250 mil
1
<10> H_CADIP[0..15]
<10> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
H_CADOP[0..15] <10>
C1
4.7U_0805_10V4Z
H_CADON[0..15] <10>
C2
4.7U_0805_10V4Z
C3
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
C5
180P_0402_50V8J
C6
180P_0402_50V8J
<10>
<10>
<10>
<10>
3
<10>
<10>
<10>
<10>
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
HT LINK
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
AE2 +VLDT_B 1
C7
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
2
4.7U_0805_10V4Z
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
side.
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
+5VS
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<10>
<10>
<10>
<10>
JP2
H_CADIP0
H _CADIN0
H_CADIP1
H _CADIN1
H_CADIP2
H _CADIN2
H_CADIP3
H _CADIN3
H_CADIP4
H _CADIN4
H_CADIP5
H _CADIN5
H_CADIP6
H _CADIN6
H_CADIP7
H _CADIN7
H_CADIP8
H _CADIN8
H_CADIP9
H _CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
D1
D2
D3
D4
1
D1
CH751H-40PT_SOD323-2
<10>
<10>
<10>
<10>
VLDT=500mA
C8
4.7U_0805_10V4Z
C9
0.1U_0402_16V4Z
3
4
GND
GND
1
2
5
6
Athlon 64 S1
Processor Socket
1
2
ACES_88231-02001
CONN@
+VCC_FAN
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
1
2
D Q1
@ D2
G
FAN_PWM
RLZ5.1B_LL34
SI3456BDV-T1-E3_TSOP6
<33>
9/20 SP07000DM00/SP07000EQ00
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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DDR_A_CLK#0
C10
1.5P_0402_50V9C
DDR_A_CLK1
1
DDR_A_CLK#1
C11
1.5P_0402_50V9C
+1.8V
2
DDR_B_CLK0
1
R1
C14
1.5P_0402_50V9C
1K_0402_1%
1
DDR_B_CLK#0
R2
C15
1.5P_0402_50V9C
C12
1K_0402_1%
1
DDR_B_CLK#1
+MCH_REF
DDR_B_CLK1
+0.9V
C13
2
2
1000P_0402_25V8J
0.1U_0402_16V4Z
+0.9V
JCPUB
+1.8V
R4
1
1
R3
39.2_0402_1%
2
2
39.2_0402_1%
T2
<8> DDR_A_ODT0
<8> DDR_A_ODT1
<8> DDR_CS0_DIMMA#
<8> DDR_CS1_DIMMA#
<8> DDR_CKE0_DIMMA
<8> DDR_CKE1_DIMMA
<8> DDR_A_CLK0
<8> DDR_A_CLK#0
<8> DDR_A_CLK1
<8> DDR_A_CLK#1
<8> DDR_A_MA[15..0]
<8> DDR_A_BS#0
<8> DDR_A_BS#1
<8> DDR_A_BS#2
<8> DDR_A_RAS#
<8> DDR_A_CAS#
<8> DDR_A_WE#
PAD
DDR_A_ODT0
DDR_A_ODT1
D10
C10
B10
AD10
VTT1
VTT2
VTT3
VTT4
AF10
AE10
MEMZP
MEMZN
H16
T19
V22
U21
V19
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
T20
U19
U20
V20
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
J22
J20
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
N19
N20
E16
F16
Y16
AA16
P19
P20
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
R20
R23
J21
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
R19
T22
T24
MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9
VTT_SENSE
RSVD_M1
MEMVREF
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
W10
AC10
AB10
AA10
A10
Y10
W17
VTT_SENSE
PAD
T1
PAD
T3
+MCH_REF
B18
W26
W23
Y26
DDR_B_ODT0
DDR_B_ODT1
V26
W25
U22
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
J25
H26
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
P22
R22
A17
A18
AF18
AF17
R26
R25
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
R24
U26
J26
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
U25
U24
U23
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_ODT0 <9>
DDR_B_ODT1 <9>
DDR_CS0_DIMMB# <9>
DDR_CS1_DIMMB# <9>
DDR_CKE0_DIMMB <9>
DDR_CKE1_DIMMB <9>
DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
<9> DDR_B_DM[7..0]
DDR_B_MA[15..0] <9>
DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
MEM:DATA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDR_A_D[63..0] <8>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM[7..0] <8>
DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor
Socket
JCPUC
<9> DDR_B_D[63..0]
DDR_A_CLK0
Athlon 64 S1
Processor Socket
CONN@
CONN@
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
of
56
@ C16
100U_D2_10VM
+1.8V
1
R5
2
10K_0402_5%
R10
2
300_0402_5%
Q3
C
CPU_THERMTRIP#_R
@ R6
1
+2.5VDDA VDDA=300mA
L1
3300P_0402_50V7K
1
2
FBM_L11_201209_300L_0805
1
1
1
1
+
4.7U_0805_10V4Z
C17
C18
C19
0.22U_0603_16V4Z
2
2
2
2
+2.5VS
3
1
PMBT3904_SOT23
1
R16
1
R7
0_0402_5%
2
EN0
2
0_0402_5%
2
0_0402_5%
<37,39>
H_THERMTRIP#_EC <33>
H_THERMTRIP# <20>
JCPUD
1
2
LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#
B7
A7
F10
C6
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
CPU_SIC
CPU_SID
AF4
AF5
AE6
SIC
SID
ALERT_L
R8
169_0402_1%
<15> CLK_CPU_BCLK#
2
3900P_0402_50V7K
C21
Address:100_1100
R13
R14
+1.2V_HT
1
1
2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1
<43> CPU_VDD0_FB_H
<43> CPU_VDD0_FB_L
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CLKIN_H
CLKIN_L
R6
P6
+1.8VS
Close to CPU
LDT_RST#
C22
0.01U_0402_25V4Z
@
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN
+CPU_CORE_0
@ R489 10_0402_5%
1
2 CPU_VDD1_FB_H
1
2 CPU_VDD1_FB_L
@R488 10_0402_5%
R25
2 0_0402_5%
F6
E6
1
2
@
C939 0.1U_0402_16V4Z
2
1
R21
300_0402_5%
<19> H_PWRGD_CPU
@
R175
@ R814
2
CPU_SID
SMB_EC_DA1
3
1
R18
@
Q127
2
1
2.2K_0402_5% FDV301N_NL_SOT23-3
R19
2
1
FDV301N_NL_SOT23-3
2.2K_0402_5%
TEST23
H10
G9
TEST18
TEST19
E9
E8
TDO
TEST9
TEST6
E10
CPU_DBREQ#
AE9
CPU_TDO
+CPU_CORE_NB
VDD_NB_FB_H <43>
VDD_NB_FB_L <43>
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
TEST7
TEST10
C3
K8
TEST8
C4
TEST29_H
TEST29_L
C9
C8
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
VDD_NB_FB_H
VDD_NB_FB_L
R484 10_0402_5%
1
2
1
2
R485 10_0402_5%
Close to CPU
J7
H8
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
C2
AA6
VDD_NB_FB_H
VDD_NB_FB_L
TEST28_H
TEST28_L
TEST25_H
TEST25_L
AB8
AF7
AE7
AE8
AC8
AF8
PAD
PAD
PAD
PAD
PAD
PAD
T5
T6
route as differential
as short as possible
testpoint under package
T7
T8
T10
T12
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
PAD
PAD
T13
T14
H18
H19
AA7
D5
C5
2
CPU_LDT_REQ# <11,19>
+1.8V
+1.8V
1
C26
2
U2
1
THERMDA_CPU 2
C27
C24
0.01U_0402_25V4Z
@
AD7
DBREQ_L
H6
G6
T42
T43
0.1U_0402_16V4Z
+3VS
2
1
VDDNB_FB_H
VDDNB_FB_L
PAD
PAD
SMB_EC_CK1 <32,33,34,37>
C25
0.01U_0402_25V4Z
@
+1.8VS
VDD1_FB_H
VDD1_FB_L
W9
Y9
EC is PU to 5VALW
LDT_STOP#
R30
300_0402_5%
1 SMB_EC_CK1
@ Q129 3
S
CPU_SIC
CPU_LDT_REQ#
THERMDC_CPU
THERMDA_CPU
1K_0402_5%
2
2
1K_0402_5%
+1.8V
R36
300_0402_5%
SMB_EC_DA1
+1.8V
W7
W8
R22
1
1
R23
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
0.1U_0402_16V7K
+1.8VS
CPU_SVC
CPU_SVD
C23
<11,19> LDT_STOP#
+1.8V
DBRDY
TMS
TCK
TRST_L
TDI
34.8K_0402_1%~N
20K_0402_5%
1
+3VS
H_PWRGD_CPU
THERMDC
THERMDA
2
0_0402_5%
+1.8V
@ 300_0402_5%
VDD0_FB_H
VDD0_FB_L
G10
AA9
AC9
AD9
AF9
A3
A5
B3
B5
C1
+1.8VS
1
@ R59
THERMDC_CPU 3
100P_0402_25V8K
4
2200p change to
100p
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
SMB_EC_CK2 <33>
SMB_EC_DA2 <33>
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
6
5
ADM1032ARMZ-2REEL_MSOP8
HDT Connector
JP3
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
26
CPU_TEST27_SINGLECHAIN
R24
2 @ 300_0402_5%
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
R26
R27
R28
R29
R31
R32
R33
R34
R35
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
300_0402_5%
@ 300_0402_5%
300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
+3VS
5
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
T9 PAD
T11 PAD
@ MMBT3904_NL_SOT23-3
Q2
1
H_PROCHOT# <19>
R17
U1
HDT_RST# 4
LDT_RST#
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_MEMHOT#_1.8V
<19>
CPU_TEST23_TSTUPD
PAD
AF6
AC7
AA8
Y
3
R15
300_0402_5%
T4
+CPU_CORE_0
R487 10_0402_5%
1
2 CPU_VDD0_FB_H
1
2 CPU_VDD0_FB_L
R486 10_0402_5%
THERMTRIP_L
PROCHOT_L
MEMHOT_L
CPU_PRO CHOT#_1.8
2
1
@ 220_0402_5% R37
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R39
2
1
@ 220_0402_5% R40
2
1
300_0402_5% R41
CPU_SVC <43>
CPU_SVD <43>
1
@ 10K_0402_5%
2
300_0402_5%
HT_REF0
HT_REF1
CPU_VDD1_FB_H Y6
CPU_VDD1_FB_L AB6
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
SVC
SVD
CPU_SVC
CPU_SVD
A6
A4
2
R11
1
R9
+1.8V
M11
W18
C20
A9
A8
KEY1
KEY2
<15> CLK_CPU_BCLK
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
2 3900P_0402_50V7K
VDDA1
VDDA2
F8
F9
CONN@ SAMTEC_ASP-68200-07
LDT_RST#
SB_PWRGD <20,33,43>
@ NC7SZ08P5X_NL_SC70-5
9/20 SP020016900
Address:100_1101
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
of
56
VDD(+CPU_CORE) decoupling.
01/18 Change the net name from +CPU_CORE_1 to
+CPU_CORE_0
C30
330U_X_2VM_R6M
+CPU_CORE_0
+CPU_CORE_0
C31
330U_X_2VM_R6M
C29
330U_X_2VM_R6M
C32
22U_0805_6.3V6M
+CPU_CORE_0
C33
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
L
1
C36
22U_0805_6.3V6M
2
+CPU_CORE_0
C38
22U_0805_6.3V6M
+CPU_CORE_NB
C41
0.01U_0402_25V4Z
C42
180P_0402_50V8J
C43
0.22U_0603_16V4Z
C44
0.01U_0402_25V4Z
+1.8V
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
3A/120mil/6vias
C45
180P_0402_50V8J
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
K16
M16
P16
T16
V16
C39
22U_0805_6.3V6M
+CPU_CORE_0
C40
0.22U_0603_16V4Z
C37
22U_0805_6.3V6M
4A/160mil/8vias
+CPU_CORE_0
JCPUE
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
C28
330U_X_2VM_R6M
JCPUF
18A/720mil/36vias
+CPU_CORE_0
1
1
+CPU_CORE_0
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
+1.8V
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
CONN@
+CPU_CORE_NB
VDDIO decoupling.
+CPU_CORE_NB
+1.8V
C52
22U_0805_6.3V6M
2
1
C46
22U_0805_6.3V6M
C47
22U_0805_6.3V6M
C48
C49
C50
C53
22U_0805_6.3V6M
1 @
C54
22U_0805_6.3V6M
2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
C51
CONN@
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2
2
2
2
+0.9V
decoupling.
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
VTT decoupling.
+ C59
220U_Y_4VM
2
C55
0.22U_0603_16V4Z
C56
0.22U_0603_16V4Z
C57
0.22U_0603_16V4Z
+1.8V
C61
0.01U_0402_25V4Z
C58
0.22U_0603_16V4Z
1
+1.8V
C60
0.01U_0402_25V4Z
C62
180P_0402_50V8J
C63
180P_0402_50V8J
C64
180P_0402_50V8J
C67
4.7U_0805_10V4Z
C68
0.22U_0603_16V4Z
C69
0.22U_0603_16V4Z
C70
1000P_0402_25V8J
C71
1000P_0402_25V8J
C72
180P_0402_50V8J
C73
180P_0402_50V8J
+0.9V
+1.8V
C66
4.7U_0805_10V4Z
C79
4.7U_0805_10V4Z
C80
4.7U_0805_10V4Z
C81
0.22U_0603_16V4Z
C82
0.22U_0603_16V4Z
C83
1000P_0402_25V8J
C84
1000P_0402_25V8J
C85
180P_0402_50V8J
C86
180P_0402_50V8J
1
1
1
C74
4.7U_0805_10V4Z
1
C75
4.7U_0805_10V4Z
1
C76
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
+ C78
220U_Y_4VM
@
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
of
56
+V_DDR_MCH_REF
+1.8V
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_A_DM[0..7]
DDR_A_DM[0..7] <5>
DDR_A_DM0
D DR_A_DQS[0..7]
DDR_A_D6
DDR_A_D7
DDR_A_DQS#[0..7]
8
7
6
5
DDR_A_DQS[0..7] <5>
DDR_A_MA[0..15]
DDR_A_D12
DDR_A_D13
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_D[0..63] <5>
DDR_A_MA[0..15] <5>
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_DQS#[0..7] <5>
DDR_A_DM1
DDR_A_CLK0 <5>
DDR_A_CLK#0 <5>
DDR_A_D14
DDR_A_D15
+1.8V
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
2
DDR_A_D26
DDR_A_D27
<5> DDR_CKE0_DIMMA
<5> DDR_A_BS#2
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5> DDR_A_BS#0
<5> DDR_A_WE#
<5> DDR_A_CAS#
<5> DDR_CS1_DIMMA#
<5> DDR_A_ODT1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
<9,15,20,30> SMB_CK_DAT0
<9,15,20,30> SMB_CK_CLK0
+3VS
1
C103
0.1U_0402_16V4Z
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
+V_DDR_MCH_REF
+V_DDR_MCH_REF <9>
DDR_A_DM2
DDR_A_D22
DDR_A_D23
C95
C96
2
1000P_0402_25V8J
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
R44
1K_0402_1%
DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4
DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_WE#
DDR_A_CAS#
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <5>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
1
C88
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
1
C90
1
C89
1
C91
1
C92
1
C93
1
C94
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4
1
C100
1
C99
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP7
DDR_CS0_DIMMA#
8
1
DDR_A_RAS#
7
2
DDR_A_MA13
6
3
DDR_A_ODT0
5
4
1
C102
1
C101
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C98
1
47_0804_8P4R_5%
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
3
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
FOX_AS0A426-N8RN-7F
CONN@
9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
1
C87
C97
0.1U_0402_16V4Z
DDR_A_D30
DDR_A_D31
47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4
47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
R43
1K_0402_1%
DDR_A_D20
DDR_A_D21
1
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_A_DQS#2
DDR_A_DQS2
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
2
3
4
47_0804_8P4R_5%
RP3
8
1
7
2
6
3
5
4
DDR_A_MA4
DDR_A_MA2
DDR_A_BS#1
DDR_A_MA0
DDR_A_D16
DDR_A_D17
+1.8V
+0.9V
RP1
D DR_A_D[0..63]
DDR_A_D4
DDR_A_D5
DDR_A_D10
DDR_A_D11
+1.8V
JP4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Title
R ev
0.3
Sheet
E
of
56
+1.8V
DDR_B_D0
DDR_B_D1
1
2
1000P_0402_25V8J
+1.8V
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+1.8V
+0.9V
JP5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<8> +V_DDR_MCH_REF
C104
D DR_B_D[0..63]
DDR_B_D4
DDR_B_D5
DDR_B_DM[0..7]
DDR_B_DM0
D DR_B_DQS[0..7]
DDR_B_D6
DDR_B_D7
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_D12
DDR_B_D9
RP8
DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#
DDR_B_D[0..63] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS[0..7] <5>
8
7
6
5
1
2
3
4
2
C105
1
C106
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C108
1
C107
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C109
1
C110
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C111
1
C112
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C114
1
C113
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C116
1
C115
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C118
1
C117
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
DDR_B_MA[0..15] <5>
RP9
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4
DDR_B_DQS#[0..7] <5>
8
7
6
5
DDR_B_DM1
1
2
3
4
47_0804_8P4R_5%
DDR_B_CLK0 <5>
DDR_B_CLK#0 <5>
RP10
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_D14
DDR_B_D15
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
DDR_B_D21
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
2
<5> DDR_CKE0_DIMMB
<5> DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<5> DDR_B_BS#0
<5> DDR_B_WE#
<5> DDR_B_CAS#
<5> DDR_CS1_DIMMB#
<5> DDR_B_ODT1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
<8,15,20,30> SMB_CK_DAT0
<8,15,20,30> SMB_CK_CLK0
+3VS
4
C119
0.1U_0402_16V4Z
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_B_D20
DDR_B_D16
RP11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_DM2
DDR_B_D22
DDR_B_D23
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
RP12
DDR_B_D28
DDR_B_D29
DDR_B_MA10
DDR_B_BS#0
DDR_B_MA1
DDR_B_MA3
DDR_B_DQS#3
DDR_B_DQS3
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_D30
DDR_B_D31
RP13
DDR_CKE1_DIMMB
DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#
DDR_CKE1_DIMMB <5>
DDR_B_MA15
DDR_B_MA14
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
RP14
DDR_B_RAS#
DDR_B_BS#1
DDR_B_ODT0
DDR_B_MA13
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VS
TYCO_292527-4
CONN@
9/20 SP07000ET00/SP07000GN00
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
of
56
U3B
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
<26> PCIE_PTX_C_IRX_P5
<26> PCIE_PTX_C_IRX_N5
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
PCIE I/F
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
TMDS_B_DATA2 <18>
TMDS_B_DATA2# <18>
TMDS_B_DATA1 <18>
TMDS_B_DATA1# <18>
TMDS_B_DATA0 <18>
TMDS_B_DATA0# <18>
TMDS_B_CLK <18>
TMDS_B_CLK# <18>
1
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
C152
C153
C154
C155
C156
C157
C158
C159
PCIE_ITX_PRX_P5
PCIE_ITX_PRX_N5
C160 1
C161
1
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R55
R56
C162
C163
C164
C165
C166
C168
C169
C167
1
1
1
1
1
1
1
1
1
1
2
2
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2
1
1
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
2
1
1
1
1
1
2
2
2
2
2
2
2
2
1.27K_0402_1%
2K_0402_1%
CardReader
WLAN
LAN10/100
<4> H_CADOP[0..15]
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
New Card
<26>
<26>
<27>
<27>
<26>
<26>
<25>
<25>
PCIE_ITX_C_PRX_P5 <26>
PCIE_ITX_C_PRX_N5 <26>
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
TV Tuner<4>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
H_CADOP[0..15]
H_CADIP[0..15]
H_CADON[0..15]
H_CADIN[0..15]
H_CADIP[0..15] <4>
H_CADIN[0..15] <4>
U3A
+1.1VS
RS880M_FCBGA528
RS780M Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
DP1
AUX1 and HPD1
H_CADON[0..15]
<4>
<4>
<4>
<4>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<4>
<4>
<4>
<4>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1 R57
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
M22
M23
R21
R20
2 301_0402_1% C23
A24
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
<26>
<26>
<27>
<27>
<26>
<26>
<25>
<25>
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H _CADIN0
H_CADIP1
H _CADIN1
H_CADIP2
H _CADIN2
H_CADIP3
H _CADIN3
H_CADIP4
H _CADIN4
H_CADIP5
H _CADIN5
H_CADIP6
H _CADIN6
H_CADIP7
H _CADIN7
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H _CADIN8
H_CADIP9
H _CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
H24
H25
L21
L20
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
<4>
<4>
<4>
<4>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<4>
<4>
<4>
<4>
1 R58
B24
B25
2 301_0402_1%
RS880M_FCBGA528
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
10
of
56
+3VS
L2
AVDD=100mA
1
2 +AVDD1
BLM18PG121SN1D_0603
1
L4
+AVDD2
C170
+1.8VS
2.2U_0603_6.3V4Z
0_0603_5%
1
2
L6
C172
1
2 +AVDDQ
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
U3C
2
F12 AVDD1(NC)
1
E12 AVDD2(NC)
C175
F14 AVDDDI(NC)
2.2U_0603_6.3V4Z
G15
AVSSDI(NC)
2
H15 AVDDQ(NC)
H14 AVSSQ(NC)
TV_CRMA
T46
PAD
E17
C_Pr(DFT_GPIO5)
TV_LUMA
T47
PAD
F17 Y(DFT_GPIO2)
TV_COMPS
T48
PAD
F15 COMP_Pb(DFT_GPIO4)
R ED
2
R ED
150_0402_1%
G18 RED(DFT_GPIO0)
<16> RED
GREEN
2
G17 REDb(NC)
GREEN
150_0402_1%
E18 GREEN(DFT_GPIO1)
<16> GREEN
BLUE
2
F18 GREENb(NC)
BLUE
150_0402_1%
E19 BLUE(DFT_GPIO3)
<16> BLUE
F19 BLUEb(NC)
+1.8VS
NB_ALLOW_LDTSTOP
0_0402_5%
1
R62
1
@ R63
1
@ R64
@
+1.1VS
+1.8VS
L9
1
2
BLM18PG121SN1D_0603
1
L7
C178
1
2
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
R65
1
2
L10
C176
+NB_PLLVDD
1
2
+NB_HTPVDD
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
+1.8VS
L11
C179
1
2
+VDDA18HTPLL
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
+1.8VS
C180
2.2U_0603_6.3V4Z
CR T_HSYNC
CRT_VSYNC
<14,16> CRT_HSYNC
<14,16> CRT_VSYNC
<16> UMA_CRT_CLK
<16> UMA_CRT_DAT
2 715_0402_1% G14
A12
D14
B12
H17
+VDDA18PCIEPLL
D7
E7
R66 0_0402_5%
NB_RESET#
1
2
D8
<14,19,25,26,27,32,33> PLT_RST#
NB_PWRGD
A10
<20> NB_PWRGD
NB_LDTSTOP#
C10
NB_ALLOW_LDTSTOP C12
1
2
+1.8VS
R371
300_0402_5%
C25
<15> CLK_NBHT
C24
<15> CLK_NBHT#
E11
F11
<15> NB_OSC_14.318M
+1.1VS
A11
B11
F8
E8
1
2
R71
4.7K_0402_5%
1
2
R72
4.7K_0402_5%
T2
T1
<15> NBGFX_CLK
<15> NBGFX_CLK#
U1
U2
<15> CLK_SBLINK_BCLK
<15> CLK_SBLINK_BCLK#
<17> LCD_DDC_CLK
<17> LCD_DDC_DAT
<18> HDMIDAT_UMA
<18> HDMICLK_UMA
<14> RS780_DFT_GPIO_0
+3VS
Strap pin
2
1
R88 10K_0402_5%
AUX_CAL
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL
VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN
A22
B22
A21
B21
B20
A20
A19
B19
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2-
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
+VDDLTP18
A15
B15
A14
B14
+VDDLT18
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
<17>
<17>
<17>
<17>
<17>
<17>
PA_RS780A4
placement close to NB ball
LVDS_ACLK+ <17>
LVDS_ACLK- <17>
1
C173
0.1U_0402_16V4Z
L3
1
2
BLM18PG121SN1D_0603
+1.8VS
C171
C1120
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
2
2
L5
1
2
+1.8VS
BLM18PG121SN1D_0603
1
C174
4.7U_0805_10V4Z
0.08A/10mil/1vias
0_0402_5%
UMA_ENVDD <17>
0_0402_5%
ENBKL <33>
NB_PWM <17>
R73
1
R1072
@ R1085 1
2
100K_0402_5%
0_0402_5%
ENBKL
3
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
C8
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
DAC_RSET(PWM_GPIO1)
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
B10
Strap pin
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
V4
V3
G11
<14>
CRT/TVOUT
PLL PWR
LVTM
R68
<6,19> CPU_LDT_REQ#
PART 3 OF 6
PM
NB_LDTSTOP#
0_0402_5%
CLOCKs
R67
1
<6,19> LDT_STOP#
1
@ R1086
MIS.
TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
STRP_DATA
RSVD
TESTMODE
D9
D10
HPD
D12
SUS_STAT_R# <14>
SUS_STAT# <20>
1
2
R77
0_0402_5%
AE8 NB_THERMAL_DA
AD8 NB_THERMAL_DC
D13
AUX_CAL(NC)
PAD
PAD
T49
T50
2
100K_0402_5%
<18>
Strap pin
NB temp to SB
1
2
R80
1.8K_0402_5%
RS880M_FCBGA528
R
Veri-Bright
R73
R1072
R1085
@
R1086
@
Non Veri-Bright
@
@
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
11
of
56
U3D
U61
L2
L3
MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
BA0
BA1
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
MEM_DQ12
MEM_DQ13
MEM_DQ9
MEM_DQ14
MEM_DQ15
MEM_DQ8
MEM_DQ10
MEM_DQ11
MEM_DQ5
MEM_DQ2
MEM_DQ6
MEM_DQ1
MEM_DQ0
MEM_DQ4
MEM_DQ3
MEM_DQ7
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
R91
100_0402_1%
MEM_CLKN
MEM_CLKP
K8
J8
MEM_CKE
K2
MEM_CS#
L8
MEM_WE#
K3
MEM_RAS#
K7
MEM_CAS#
L7
MEM_DM0
MEM_DM1
F3
B3
MEM_ODT
K9
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
+1.8V_MEM_VDDQ
MEM_DQS_P1
MEM_DQS_N1
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0
MEM_BA1
MEM_BA2
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT
W12
Y12
AD18
AB13
AB18
V14
V15
W14
MEM_COMP_P
1
40.2_0402_1%
MEM_COMP_N
1
40.2_0402_1%
2
R92
2
R93
AE12
AD12
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1
W17
AE19
MEM_DM0
MEM_DM1
AE23
AE24
+NB_IOPLLVDD
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
L13
1
+MEM_VREF1
+1.8V_IOPLLVDD
1
2
0_0603_5%
C181
2.2U_0603_6.3V4Z
+1.1VS
1
1
C182
0.1U_0402_16V4Z
0_0603_5%
C183
2.2U_0603_6.3V4Z
C184
RS880M_FCBGA528
+1.8V_MEM_VDDQ
+VDDL
J1
J7
2
LDQS
LDQS
VDD
VDD
VDD
VDD
VDD
A1
E1
J9
M9
R1
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
MEM_CLKP
MEM_CLKN
ODT
F7
E8
MEM_BA2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDDL
VSSDL
MEM_DQS_P0
MEM_DQS_N0
+MEM_VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
+1.8V_MEM_VDDQ
PAR 4 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
SBD_MEM/DVO_I/F
MEM_BA0
MEM_BA1
1U_0603_10V6K
A3
E3
J3
N1
P9
HY5PS561621AFP-25_FBGA84
+1.8VS
1
C203
2
22U_0805_6.3V6M
C202
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C201
2
C607
C608
2
1
1K_0402_1%
R99
0.1U_0402_16V4Z
1U_0402_6.3V4Z
L15
1U_0402_6.3V4Z
2
R97
1
+1.8V_MEM_VDDQ
+MEM_VREF1
C200
1K_0402_1%
C199
0.1U_0402_16V4Z
R98
1
2
+MEM_VREF
1K_0402_1%
0.1U_0402_16V4Z
1
C196
+1.8V_MEM_VDDQ
1K_0402_1%
C195
0.1U_0402_16V4Z
R96
1
2
+1.8V_MEM_VDDQ
2
0_0805_5%
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
12
of
56
U3F
+VDDHT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C2081
1 C206 1
1
1
C210
U3E
1
C236
1
C237
1
C238
1
C239
4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
F9
G9
AE11
AD11
+1.8VS
+1.8VS
2 +1.8V_VDD_SP
0_0603_5%
1
R1051
C251
1U_0402_6.3V4Z
+1.8VS
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
RS880M_FCBGA528
1
+
C234
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
PART 6/6
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
RS880M_FCBGA528
+1.8VS
0.15A/30mil/2vias
C249
C248
C597
C598
C599
2
2
2
2
2
1
1
1
1
1
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
+3VS
C252
1U_0402_6.3V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
C250
2
C253
U64
2
1
3
R1015
1K_0402_1%
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
@ 10U_0805_10V4Z
VDD33_1(NC)
VDD33_2(NC)
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
C1064
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
330U_D2E_2.5VM_R15
C245
1
C246
7A/280mil/16vias VDD_CORE=5A
C233
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
10U_0805_10V4Z
0_0805_5%
C235
4.7U_0805_10V4Z
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
+NB_VDDC
C232
+VDDA18PCIE
2
PAD-OPEN 4x4m
10U_0805_10V4Z
0.25A/30mil/2vias
2A
L22
2
+1.8VS
+1.1VS
C244
4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
0.1U_0402_16V4Z
PJP604
C231
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C229
2
2
2
2
1
1
C230
1
C228
1
1
1
1
2
2
0.1U_0402_16V4Z
1
C227
C220
C219
C222
C221
C224
C223
C243
1
C226
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
10U_0805_10V4Z
C212
0.1U_0402_16V4Z
1
C225
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
10U_0805_10V4Z
C211
C242
+VDDHTTX
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
+1.1VS
+VDDA11PCIE
0.1U_0402_16V4Z
0.5A/50mil/4vias
0_0805_5%
H18
G19
F20
E21
D22
B23
A23
0.1U_0402_16V4Z
PART 5/6
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
C241
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
0.1U_0402_16V4Z
C216
2
2
2
0.1U_0402_16V4Z
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
L17
1
2
FBMA-L11-201209-221LMA30T_0805
0.7A/60mil/4vias
VDDA_12=2.5A
C240
J17
K16
L16
M16
P16
R16
T16
+VDDHTRX
2A
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.45A/40mil/3vias
L19
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
1 C217 1
1
C214
C218
C215
4.7U_0805_10V4Z
C207
C247
2A
0_0805_5%
+1.2V_HT
L18
1
0.1U_0402_16V4Z
C209
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0_0805_5%
POWER
0.6A/50mil/4vias
2A
L16
2
+1.1VS
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
GROUND
TP
+3VS
5
7
C1065
8
9
@ 1U_0603_10V6K
@ G2992F1U_SO8
+VREF1.35V
+1.35VS
2
@ 0_0402_5%
2
G
2
@ 3K_0402_5%
2
1
R1017
VLDT_EN#
<36>
R1016
1
Q163
@ 2N7002_SOT23-3
C1068
@ 0.1U_0402_16V7K
C1066
C1067
@ 10U_0805_10V4Z
@ 0.1U_0402_16V7K
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
13
of
56
2
R101
2
R102
1
1K_0402_5%
1
@ 1K_0402_5%
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
+3VS
DFT_GPIO1: LOAD_EEPROM_STRAPS
1
@ R104
<11> AUX_CAL
RS780 DFT_GPIO1
D4
2
<11> SUS_STAT_R#
2
150_0402_1%
@ CH751H-40PT_SOD323-2
1
PLT_RST#
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
<11> RS780_DFT_GPIO_0
2
@ R105
1
1K_0402_5%
<11,16> CRT_HSYNC
2
R1064
1
3K_0402_5%
1
+3VS
3K_0402_5%
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
14
of
56
+3VS_CLK
+3VS
R167
1
2
0_0805_5%
+VDDCLK_IO
+1.2V_HT
R168
1
2
0_0805_5%
0.1U_0402_16V4Z
1
C452
10U_0805_10V4Z
C453
2
0.1U_0402_16V4Z
1
C454
C455
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C456
1
C444
10U_0805_10V4Z
C457
2
0.1U_0402_16V4Z
C445
0.1U_0402_16V4Z
C446
0.1U_0402_16V4Z
C447
0.1U_0402_16V4Z
C448
0.1U_0402_16V4Z
C449
0.1U_0402_16V4Z
1
@ C451
C450
0.1U_0402_16V4Z
1U_0402_6.3V4Z
2
1
C458
C459
C460
C461
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
22P_0402_50V8J
U10
GND
<8,9,20,30> SMB_CK_CLK0
<8,9,20,30> SMB_CK_DAT0
+3VS_CLK
PA_RS7X0A1
<11> CLK_SBLINK_BCLK#
<11> CLK_SBLINK_BCLK
SB LINK
+VDDCLK_IO
MiniCard_1
MiniCard_2
<26> CLK_PCIE_MCARD1#
<26> CLK_PCIE_MCARD1
<26> CLK_PCIE_MCARD2#
<26> CLK_PCIE_MCARD2
+3VS_CLK
+3VS_CLK
1
R174
2
+3VS_CLK
8.2K_0402_5%
1
R946
CLK_CPU_BCLK#_R 1
R945
SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CLK_14M_SB <19>
CLK_CPU_BCLK_R
RX780
1.8V 75R/100R
RS780
1.1V 200R/100R
NB
C1075
12P_0402_50V8J
CLK_CPU_BCLK <6>
2
0_0402_1%
2
0_0402_1%
1U_0402_6.3V4Z
R186
@ 261_0402_1%
CPU
+3VS_CLK
CLK_CPU_BCLK# <6>
VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
C1106
0.1U_0603_25V7K
+3VS_CLK
+VDDCLK_IO
CLKREQ_NCARD#
CLKREQ_MCARD2#
CLKREQ_NCARD# <26>
CLKREQ_MCARD2# <26>
+3VS_CLK
CLK_SBSRC_BCLK <19>
CLK_SBSRC_BCLK# <19>
+3VS_CLK
CLKREQ_MCARD1#
CLKREQ4
1
2
R372
10K_0402_5%
SB SRC
PA_RS7X0A1
CLKREQ_MCARD1# <26>
+3VS_CLK
+3VS_CLK
+VDDCLK_IO
3
SLG8SP626VTR_QFN72_10x10
CLKREQ_MCARD2#
CLKREQ_LAN#
CLKREQ4
NBGFX_CLK <11>
NBGFX_CLK# <11>
CLKREQ_LAN#
R180
8.2K_0402_5%
1
R181
8.2K_0402_5%
+3VS_CLK
+VDDCLK_IO
CLKREQ_MCARD1#
SEL_SATA
27M_SEL
1
SEL_SATA
0
1 *
CLK_PCIE_MCARD0 <27>
CLK_PCIE_MCARD0# <27>
CLKREQ_LAN# <25>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
* default
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
@ 8.2K_0402_5%
+3VS_CLK
GLAN
CLK_PCIE_NCARD <26>
CLK_PCIE_NCARD# <26>
New Card
Card Reader
RX780
RS780
HT_REFCLKP
100M DIFF
100M DIFF
100M DIFF
100M DIFF
REFCLK_N
14M SE (1.8V)
NC
14M SE (1.1V)
v r ef
GFX_REFCLK
100M DIFF
100M DIFF(IN/OUT)*
REFCLK_P
27M_SEL
configure as normal SRC(SRC_6) output
1
R324
1
R325
1
R326
1
R1039
1
R1045
NB GFX
HT_REFCLKN
4
C1076
CLKREQ_NCARD#
+3VS_CLK
2
12P_0402_50V8J
C1123
2
C1074
12P_0402_50V8J
+3VS_CLK
@ R179
8.2K_0402_5%
CLK_14M_SIO
CLK_NBHT <11>
CLK_NBHT# <11>
VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC
+3VS_CLK
+VDDCLK_IO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
90.9_0402_1%
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
22P_0402_50V8J
2
NB_OSC_14.318M <11>
1 R380
R1105 175_0402_1%
2
R1106
110_0402_5%
VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#
C464
73
1
14.31818MHZ_20P_6X1430004201
1
C465
CLK_XTAL_OUT
CLK_XTAL_IN
CLK_48M_USB_R
Y2
NB_OSC_14.318M_R
SEL_SATA
27M_SEL
CLK_XTAL_IN
2
158_0402_1%
R379
+3VS_CLK
CLK_XTAL_OUT
NB_OSC_14.318M
OSC_14M_NB
CLK_48M_USB <20>
R170 1
2007/08/02
Issued Date
0*
configure as differential 100MHz output
* default
Security Classification
NB_OSC_14.318M
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
Title
R ev
0.3
Sheet
E
15
of
56
CRT CONNECTOR
+5VS
+R_CRT_VCC
@ D35
@ D37
+CRT_VCC
F2
D36
@ D34
RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z
+3VS
DAN217_SC59DAN217_SC59
DAN217_SC59
JCRT
C858
GREEN_L
H S YNC
BLUE_L
1
C476
2
1
C472
2
6P_0402_50V8K
1
C469
D_DDCDATA
6P_0402_50V8K
R217
1
C859
6P_0402_50V8K
C471
R211
2
R214
75_0402_1%
BLUE
75_0402_1%
<11>
BLUE
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RED_L
6P_0402_50V8K
GREEN
GREEN
6P_0402_50V8K
<11>
6P_0402_50V8K
RED
75_0402_1%
<11>
L47
1
2
BLM15AG121SN1D_0402
L48
1
2
BLM15AG121SN1D_0402
L49
1
2
BLM15AG121SN1D_0402
R ED
+CRT_VCC
VSYNC
D_DDCCLK
16
17
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
+CRT_VCC
1
C1107
0.1U_0603_25V7K
GND
GND
CONN@ SUYIN_070546FR015S263ZR
RED_L
<35>
GREEN_L <35>
BLUE_L
+3VS
<35>
+CRT_VCC
6.8K_0402_5%
6.8K_0402_5%
D_DDCDATA
Q10A
2N7002DW-7-F_SOT363-6
1
2
@ R1023
0_0402_5%
v0.2 ADD
4
3
Q10B
2N7002DW-7-F_SOT363-6
<11,14> CRT_HSYNC
5
1
D_HSYNC <35>
D_HSYNC
U14
SN74AHCT1G125GW_SOT353-5
D_DDCDATA <35>
3
R218
D_VSYNC <35>
R240 1
2 0_0603_5%
H S YNC
R241 1
2 0_0603_5%
VSYNC
<11> UMA_CRT_DAT
R100
1
2
C473
0.1U_0402_16V4Z
P
OE#
R238
4.7K_0402_5%
+CRT_VCC
R237
4.7K_0402_5%
2 470P_0402_50V8J
5
1
<11,14> CRT_VSYNC
@ C856
v0.2 ADD
D_VSYNC
U13
SN74AHCT1G125GW_SOT353-5
1
@ C474
@ C470
10P_0402_50V8J
470P_0402_50V8J
1
2
@ C477
0.1U_0402_16V4Z
2 A
P
OE#
@ C857
2
0_0402_5%
D_DDCCLK <35>
10P_0402_50V8J
@ R1022
D_DDCCLK
1
<11> UMA_CRT_CLK
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
16
of
56
VIN
VOUT
R891
@ 215K_0402_1%
2
C719
EN
BP
GND
U54
PJP6
PAD-OPEN 2x2m
2
C720
RT9193-39GB_SOT23-5
C718
10U_0805_10V4Z
+USB_CAM
PJP4
PAD-OPEN 2x2m
+5VS
+5VALW
R1013
0.1U_0402_16V4Z
0_0402_5%
R892
10U_0805_10V4Z
@ 100K_0402_1%
Close to JLVDS
D22
@ R1014
1
2
0_0402_5%
+USB_CAM
CAM_SHDN# <21>
USB20_N5
VIN
IO1
USB20_P5
IO2 GND
@ PRTR5V0U2X_SOT143-4
+3VS
R224
1M_0402_5%
80mil
3
6 2
R225
220_0402_5%
2 @ 10P_0402_50V8J
LVDS_A2+
LVDS_A1-
C1057
2 @ 10P_0402_50V8J
LVDS_A1+
LVDS_A0-
C1058
2 @ 10P_0402_50V8J
LVDS_A0+
LVDS_ACLK- C1059
2 @ 10P_0402_50V8J
<20>
<20>
LVDS_ACLK+
C481
+3VS
680P_0402_50V7K
+LCDVDD
1
C487
4.7U_0805_10V4Z
C491
0.1U_0402_16V4Z
Q45B
2N7002DW-7-F_SOT363-6
LVDS CONN
680P_0402_50V7K
USB20_P5
USB20_N5
JLVDS
USB20_P5
USB20_N5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+
LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_ACLK- <11>
LVDS_ACLK+ <11>
DMIC_DAT
DMIC_CLK
DMIC_DAT <28>
DMIC_CLK <28>
INV_PWM
BKOFF#
DAC_BRIG
9/20 SP02000EA00/SP02000BW00
R1084 1
20_0402_5%
@ R1078 1
20_0402_5%
NB_PWM
INV_PWM
3
<33>
EC_PWM
+5VS
R491
1
2 100_0805_5%
BKOFF#
<33>
DAC_BRIG <33>
LCD_DDC_CLK
LCD_DDC_DAT
ACES_88242-4001
CONN@
<11>
+USB_CAM
+3VS
LCD_DDC_CLK <11>
LCD_DDC_DAT <11>
2
@
C483
680P_0402_50V7K
C480
C482
680P_0402_50V7K
C1056
R276
2.2K_0402_5%
C1108
680P_0402_50V7K
C867
680P_0402_50V7K
2
1
LVDS_A2-
C866
680P_0402_50V7K
2
1
L44
1
2
FBMA-L11-201209-221LMA30T_0805
80mil
1000P_0402_50V7K
680P_0402_50V7K
C479
<11> UMA_ENVDD
C863
B+
R222
1
2
100K_0402_5%
INVPWR_B+
SI2301BDS-T1-E3_SOT23-3
Q43
Q45A
2N7002DW-7-F_SOT363-6
+LCDVDD
+5VALW
+LCDVDD
BKOFF#
1
@ 4.7K_0402_5%
2
R483
LCD_DDC_CLK 1
4.7K_0402_5%
2
R274
LCD_DDC_DAT 1
4.7K_0402_5%
2
R275
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
17
of
56
+HDMI_5V_OUT
+3VS
R176
4.7K_0402_5%
HDMI_HPD
U39
SN74AHCT1G125GW_SOT353-5
R628
100K_0402_5%
<11>
1
HPD
+3VS
2.2K_0402_5%
P
OE#
1
R615
1
6
Q134A
2N7002DW-7-F_SOT363-6
@ R1019
1
2
0_0402_5%
4
3
Q134B
2N7002DW-7-F_SOT363-6
<11> HDMIDAT_UMA
R236
6.8K_0402_5%
HDMI_SDATA
5
1
0.1U_0402_16V4Z
R210
6.8K_0402_5%
+HDMI_5V_OUT
C851
R209
4.7K_0402_5%
2
C850
0.1U_0402_16V4Z
<11> HDMICLK_UMA
HDMI_SCLK
v0.2 ADD
@ R1018
1
2
0_0402_5%
v0.2 ADD
1
@ R112
2
0_0402_5%
HDMI_R_CK+
D10
1
4
<10> TMDS_B_CLK#
<10> TMDS_B_CLK
C507 1
C508 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_CLKHDMI_CLK+
<10> TMDS_B_DATA0#
<10> TMDS_B_DATA0
C655 1
C675 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX0HDMI_TX0+
<10> TMDS_B_DATA1#
<10> TMDS_B_DATA1
C804 1
C827 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX1HDMI_TX1+
C852 1
C853 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX2HDMI_TX2+
HDMI_CLK-
1
@ R115
4
HDMI_TX0-
HDMI_TX1HDMI_TX1+
HDMI_TX1+
715_0402_1%
R304
R139
715_0402_1%
1
3
S 2N7002_SOT23-3
Q173
1
@ R117
HDMI_R_CK-
+HDMI_5V_OUT
JHDMI
18 +5V
16 SDA
15 SCL
19 HP_DET
3
HDMI_R_D0-
HDMI_R_D1+
2
3
WCM-2012-900T_4P
1
2
@ R118
0_0402_5%
0.1U_0402_16V4Z
HDMI Connector
2
0_0402_5%
C468
HDMI_R_D0+
L87
715_0402_1%
R141
HDMI_TX1-
2
G
WCM-2012-900T_4P
1
2
@ R116
0_0402_5%
1
1
715_0402_1%
R297
1
1
+5VS
R172
715_0402_1%
2
2
2
2
R307
715_0402_1%
R173
715_0402_1%
1
2
R315
715_0402_1%
HDMI_TX2HDMI_TX2+
2
2
HDMI_TX0HDMI_TX0+
2
1
HDMI_CLKHDMI_CLK+
1
1
2
0_0402_5%
+HDMI_5V_OUT
L86
1
<10> TMDS_B_DATA2#
<10> TMDS_B_DATA2
1
RB491D_SOT23
WCM-2012-900T_4P
1
2
@ R113
0_0402_5%
HDMI_TX0+
+5VS
L85
HDMI_SDATA
HDMI_SCLK
HDMI_HPD
CEC
Reserved
13
14
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND
2
5
8
11
20
21
22
23
17
12
10
9
7
6
4
3
1
CKCK+
D0D0+
D1D1+
D2D2+
CONN@ SUYIN_100042MR019S153ZL
HDMI_R_D1-
1
@ R119
2
0_0402_5%
HDMI_R_D2+
L88
1
R1104
100K_0402_5%
HDMI_TX2-
WCM-2012-900T_4P
1
2
@ R120
0_0402_5%
HDMI_R_D2-
03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
18
of
56
2 NB_RST#_R
@ 8.2K_0402_5%
U15A
1
33_0402_5%
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
+1.2V_HT
C492
C493
C494
C495
C496
C497
C498
C499
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
V23
V22
V24
V25
U25
U24
T23
T22
U22
U21
U19
V19
R20
R21
R18
R17
R305
R306
+PCIE_VDDR
L53
1
2
BLM18PG121SN1D_0603
1
C504
10U_0805_10V4Z
2
2
1 562_0402_1%
1 2.05K_0402_1%
T25
T24
+SB_PCIEVDD
P24
P25
C505
1U_0402_6.3V4Z
SB700
A_RST#
Part 1 of 5
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_CALRP
PCIE_CALRN
PCIE_PVDD
PCIE_PVSS
Close to SB
K23
K22
M24
M25
P17
M18
M23
M22
J19
J18
L20
L19
@ R314 20M_0402_5%
1
2
M19
M20
C643
SB_32KHI
2
Y3
4
R389
1
20M_0402_5%
NC
OSC
NC
3
2
<15> CLK_14M_SB
1
R1107
2
0_0402_5%
L18
2
@ R1108
1
0_0402_5%
J21
CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
25M_48M_66M_OSC
14M_X1
32.768KHZ_12.5PF_Q13MC14610050_10PPM
C652
1
OSC
N22
P22
NB_HT_CLKP
NB_HT_CLKN
SB_32KHO
2
@ R1109
1
1K_0402_5%
J20
14M_X2
18P_0402_50V8J
1 CPU_LDT_REQ#
@ 10K_0402_5%
+3VS
2
R319
H_PROCHOT#
1
10K_0402_5%
<6,11> CPU_LDT_REQ#
<6> H_PROCHOT#
<43> H_PWRGD
<6,11> LDT_STOP#
<6>
LDT_RST#
R311
2
H_PWRGD_SB
0_0402_5%
CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD
F23
F24
F22
G25
G24
X2
ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
N1
R301 1
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
PAD
T15
PAD
PAD
T16
T17
AD3
AC4
AE2
AE3 PCI_PIRQH#
LPCCLK1
R967 2
1 0_0402_5%
G22 CLK_PCI_EC_R
E22 LPCCLK1
H24
H23
J25
J24
H25
PAD T18
H22
AB8
AD7
V15
C3
C2
B2
12P_0402_50V8J
2
CLK_PCI_EC
C1087
1
12P_0402_50V8J
2
2 33_0402_5% CLK_PCI_SIO
CLK_PCI_EC <23,33>
<32,33>
STRAP PIN
+3VL
+SB_VBAT
+SB_VBAT
+RTCVCC_R
C509
W=20mils
C510
2
1U_0402_6.3V4Z
+RTCVCC
R317
120_0402_5%
1
2
+RTCBATT
D42
2
R876
1
3
1
2
W=20mils
DAN202U_SC70
1K_0402_5%
JBATT1
W=20mils
J1
@ JUMP_43X39
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
1
2
3
4
1
2
GND
GND
CONN@ ACES_85205-02001
+RTCBATT_R
9/20 SP020008T00
LPC_DRQ# <32>
SIRQ
Security Classification
CLK_PCI_SIO <32>
STRAP PIN
EC & Debug
0.1U_0402_16V4Z
C1086
1
LPCCLK1 <23>
LPC_AD0 <32,33>
LPC_AD1 <32,33>
LPC_AD2 <32,33>
LPC_AD3 <32,33>
LPC_FRAME# <32,33>
RTC_CLK <23>
CLK_PCI_SIO
ACCEL_INT <30>
33_0402_5%
2 CLK_PCI_EC
12P_0402_50V8J
2
R308 1
R316
120_0402_5%
1
2
@ C1085
1
PCI_SERR# <33>
0_0402_5%
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
CLK_PCI_SIO2
R302
RTCCLK
INTRUDER_ALERT#
VBAT
Issued Date
PCICLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
0_0402_5% PCI_CLK3
R1079
1
<43> H_PWRGD
B3
PCIRST#
CLK_PCI_SIO_R
RTC
<6> H_PWRGD_CPU
SB_32KHO
X1
L PC
2
R318
A3
C PU
+1.8VS
SB_32KHI
RTC XTAL
Close to SB
P4
P3
P1
P2
T4
T3
18P_0402_50V8J
NB_DISP_CLKP
NB_DISP_CLKN
PCI INTERFACE
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
CLO CK GENERATOR
N25
N24
<15> CLK_SBSRC_BCLK
<15> CLK_SBSRC_BCLK#
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41
N2
NB_RST#_R
@ NC7SZ08P5X_NL_SC70-5
3
2
R312
1
R300
PLT_RST# <11,14,25,26,27,32,33>
4 PLT_RST#
Y
A
PC I CLKS
U16
NB_RST#_R
@ 0.1U_0402_16V4Z
2
+3VALW
C506
Title
R ev
0.3
Sheet
E
19
of
56
R1052
<11> NB_PWRGD
1 NBPWRGD
0_0402_5%
R1053 2
1
@ 100_0402_5%
U15D
+3VALW
1
R320
1
R321
1
R322
<33>
<33>
<33>
<33>
SB_TEST2
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
SB_TEST1
SB_TEST0
<6> H_THERMTRIP#
+3VS
1
2 1.2K_0402_5%
SMB_CK_CLK0
R329
2 1.2K_0402_5%
SMB_CK_DAT0
CH751H-40PT_SOD323-2
1
2
D58
<39,41> 3/5V_OK
+3VALW
R332
<33> EC_RSMRST#
2 2.2K_0402_5%
SMB_CK_CLK1
2 2.2K_0402_5%
SMB_CK_DAT1
+3VALW
R327
2.2K_0402_5%
1
2
10K_0402_5%
E6
E7
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1
SB_GPIO5
AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5
SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#
R337
R338
<34> HDA_SYNC_MDC
<28> HDA_SYNC_CODEC
R339
R340
<28> HDA_RST#_CODEC
<34> HDA_RST#_MDC
<23,33> HDARST#
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#
INTEGRATED uC
33_0402_5%
33_0402_5%
R335
R336
STRAP PIN
C1088
1
82P_0402_50V8J
HDA_BITCLK_CODEC
2
C1089
1
82P_0402_50V8J
HDA_BITCLK_MDC
2
C1090
1
82P_0402_50V8J
HDA_SDOUT_MDC
2
C1091
1
82P_0402_50V8J
HDA_SDOUT_CODEC
2
H19
H20
H21
F25
D22
E24
E25
D23
PS2_DAT
PS2_CLK
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3
PS2KB_DAT
PS2KB_CLK
PS2M_DAT
PS2M_CLK
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
E11
F11
USB20_P10
USB20_N10
USB20_P8
USB20_N8
USB_HSD7P
USB_HSD7N
G11
H12
USB20_P7
USB20_N7
USB_HSD6P
USB_HSD6N
E12
E14
USB20_P6
USB20_N6
C12
D12
USB20_P5
USB20_N5
USB20_P8 <26>
USB20_N8 <26>
USB-8 MiniCard(WLAN)
USB20_P7 <31>
USB20_N7 <31>
USB-7 Fingerprint
USB20_P6 <31>
USB20_N6 <31>
USB-6 Bluetooth
USB20_P5 <17>
USB20_N5 <17>
H14
H15
USB20_P2
USB20_N2
USB_HSD1P
USB_HSD1N
A13
B13
USB20_P1
USB20_N1
USB_HSD0P
USB_HSD0N
B14
A14
USB20_P0
USB20_N0
KSO_16
KSO_17
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17
A18
B18
F21
D21
F19
E20
E21
E19
D19
E18
KSI_0
KSI_1
KSI_2
KSI_3
KSI_4
KSI_5
KSI_6
KSI_7
G20
G21
D25
D24
C25
C24
B25
C23
KSO_0
KSO_1
KSO_2
KSO_3
KSO_4
KSO_5
KSO_6
KSO_7
KSO_8
KSO_9
KSO_10
KSO_11
KSO_12
KSO_13
KSO_14
KSO_15
B12
A12
G12
G14
USB_HSD3P
USB_HSD3N
USB20_P10 <26>
USB20_N10 <26>
C10
D10
USB_HSD4P
USB_HSD4N
USB20_P11 <26>
USB20_N11 <26>
A11
B11
USB_HSD8P
USB_HSD8N
USB_HSD5P
USB_HSD5N
2
R323
F7
E8
USB20_P11
USB20_N11
USB_HSD2P
USB_HSD2N
USB OC
R333
<28> HDA_BITCLK_CODEC
R334
<34> HDA_BITCLK_MDC
<34> HDA_SDOUT_MDC
<28> HDA_SDOUT_CODEC
<28> HDA_SDIN0
<34> HDA_SDIN1
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#
INTEGRATED uC
<26> MINI_PCIE_WAKE#
B9
B8
A8
R82 0_0402_5%
A9
<33> EC_LID_OUT#
EXP_CPPE#
1
2
E5
<26> EXP_CPPE#
CR_CPPE#
1
2
F8
<27> CR_CPPE#
R81
0_0402_5% E4
1
2
HDABITCLK
1
2
1
2 HDA_BITCLK
33_0402_5%
R1080 0_0402_5%
1
2
M1
HDA_SDOUT
33_0402_5%
1
2
M2
HDA_SDIN0
J7
HDA_SDIN1
J8
L8
M3
HDA_SYNC
33_0402_5%
1
2
L6
33_0402_5%
1
2
M4
L5
HDARST#
33_0402_5%
1
2
33_0402_5%
1
2
PAD T41
CLK_48M_USB <15>
USB_RCOMP 1
11.8K_0402_1%
H11
J10
RSMRST#
H D AUDIO
PCIE_WAKE#
1
47_0402_5%
1
@ 0_0402_5%
2
R993
2
R994
<25> LAN_PCIE_WAKE#
USB_FSD12P
USB_FSD12N
USB_HSD9P
USB_HSD9N
R540
10K_0402_5%
D3
EC_RSMRST#
<28> SB_SPKR
<8,9,15,30> SMB_CK_CLK0
<8,9,15,30> SMB_CK_DAT0
<26> SMB_CK_CLK1
<26> SMB_CK_DAT1
+3VS
R83
EC_RSMRST#
R328
R331
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
USB_FSD13P
USB_FSD13N
USB MISC
SUS_STAT#
G8
U SB 2.0
2
4.7K_0402_5%
C8
USB_RCOMP
GPIO
1
R388
USBCLK/14M_25M_48M_OSC
<33> SLP_S3#
<33> SLP_S5#
<33> PWRBTN_OUT#
<6,33,43> SB_PWRGD
<11> SUS_STAT#
+3VS
Part 4 of 5
SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD
U SB 1.1
E1
E2
H7
F5
G1
H2
H1
SUS_STAT#
K3
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
Y15
W15
K4
K24
F1
PAD T19
J2
PCIE_WAKE#
H6
F2
H_THERMTRIP# J6
NBPWRGD
W14
USB20_P3 <35>
USB20_N3 <35>
USB-3 Dock
USB20_P2 <31>
USB20_N2 <31>
USB20_P1 <31>
USB20_N1 <31>
USB20_P0 <31>
USB20_N0 <31>
STRAP PIN
STRAP PIN
GPIO16 <23>
GPIO17 <23>
B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18
+3VS
HDABITCLK
6
@ R1081
2
1 5
10K_0402_5%
1
@C1122
4
0.1U_0402_16V4Z
CLKOUT
CLKIN
NC
HDA_BITCLK
4
SSON
NC
GND
SS
ASM3P623S00BF-08TR_TSSOP8
@ U66
7 VDD
4
@ R1082
2
1
10K_0402_5%
+3VS
@ R1083
10K_0402_5%
Security Classification
2007/08/02
2008/08/02
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Issued Date
R ev
0.3
Sheet
E
20
of
56
Y4
SATA_X1
1 C516
1
10P_0402_50V8J 2
R341
10P_0402_50V8J 2
10M_0402_5%
25MHz_20pF_6X25000017
1 C517
SATA_X2
U15B
SATA_TXP1
SATA_TXN1
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
<31>
<31>
SATA_TXP2
SATA_TXN2
C520
C521
1
1
2 1000P_0402_50V7K
2 1000P_0402_50V7K
<24> SATA_RXN0_C
<24> SATA_RXP0_C
SATA_STX_DRX_P1
SATA_STX_DRX_N1
SATA_STX_DRX_P2
SATA_STX_DRX_N2
C518
C519
SATA_TXP3
SATA_TXN3
SATA_STX_DRX_P3
SATA_STX_DRX_N3
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
1
1
<24> SATA_RXN3_C
<24> SATA_RXP3_C
2
R342
R343 10K_0402_5%
1
2
+3VS
SATA_RX0N
SATA_RX0P
AE10
AD10
SATA_TX1P
SATA_TX1N
AB12
AC12
SATA_TX2P
SATA_TX2N
SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N
AB14
AC14
SATA_RX3N
SATA_RX3P
AE14
AD14
SATA_TX4P
SATA_TX4N
AD15
AE15
SATA_RX4N
SATA_RX4P
AB16
AC16
SATA_TX5P
SATA_TX5N
AE16
AD16
SATA_RX5N
SATA_RX5P
SATA_CAL
1
1K_0402_1%
SATA_X1
V12
SATA_CAL
Y12
SATA_X1
SATA_X2
AA12
SATA_X2
SATA_ACT#/GPIO67
W12
C523
1U_0402_6.3V4Z
+3VS
L55
2
1
BLM18PG121SN1D_0603
3
C524
1U_0402_6.3V4Z
+XTLVDD_SATA
2
PLLVDD_SATA
XTLVDD_SATA
IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30
SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32
G6
D2
D1
F4
F3
LAN_RST#/GPIO13
ROM_RST#/GPIO14
U15
J1
Hynix
Qimonda
Samsung
+3VALW
CR_WAKE# <27>
P5
P8
R8
C6
B6
A6
A5
B5
TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64
A4
B4
C4
D4
D5
D6
A7
B7
VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60
+3VALW
M8
M5
M7
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
HW MONITOR
2
C522
1U_0402_6.3V4Z
AA11
AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49
SATA PWR
+PLLVDD_SATA
LFB_ID2
R344 1
2 1K_0402_5%
LFB_ID1
R367 1
2 10K_0402_5%
R345 1
2 10K_0402_5%
R1032
L54
2
1
BLM18PG121SN1D_0603
AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24
IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#
Part 2 of 5
SATA_RX1N
SATA_RX1P
AD13
AE13
W11
<34> SATA_LED#
+1.2V_HT
AB10
AC10
AE12
AD12
<31> SATA_RXN2_C
<31> SATA_RXP2_C
<24>
<24>
SATA_TX0P
SATA_TX0N
AD11
AE11
<24> SATA_RXN1_C
<24> SATA_RXP1_C
SB700
AD9
AE9
F6
AVDD
G7
AVSS
+3VALW
HDD_HALTLED# <34>
SB_INT_FLASH_SEL
THERMAL_DC R1062
2 0_0402_5%
WLOFF# <26>
BT_COMBO_EN# <26>
WWOFF# <26>
EC_THERM# <33>
AC_IN_SB
BT_OFF
<31>
CAM_SHDN# <17>
LFB_ID0
LFB_ID1
LFB_ID2
R1071
150K_0402_5%
2
1
AC_IN
D56
CH751H-40PT_SOD323-2
<33,38>
+SB_AVDD
1
1
2
C525
0.1U_0402_16V4Z
1
2
@ 1K_0402_5%
LFB_ID0
1
2
@ 1K_0402_5%
R1033
<24>
<24>
C514
C515
SATA_STX_DRX_P0
SATA_STX_DRX_N0
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ATA 66/100/133
1
1
SPI ROM
C512
C513
SERIAL ATA
SATA_TXP0
SATA_TXN0
<24>
<24>
+3VALW
L56
2
1
BLM18PG121SN1D_0603
C526
2.2U_0603_6.3V4Z
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
21
of
56
U15C
@ 0_0603_5%
1
2
C543
C544
C547
C536
Y20
AA21
AA22
AE25
VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4
+3.3V_SB_IDE
1
1
1
@ 22U_0805_6.3V6M
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z
C552
C553
C555
C554
C558
C557
C560
P18
P19
P20
P21
R22
R24
R25
1
1
1
1
1
1
2
2
2
2
2
2
4.7U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
C566
C567
C568
C571
C572
2
2
2
2
2
2
2
2
2
2
0.3A/30mil/2vias
C546
C545
C548
C551
C550
U15E
2
+1.2VALW
@ 0_0805_5%
2
+1.2V_HT
0_0805_5%
2
C529
C532
1
C534
1
C538
1
C537
1
C527
1
C540
1
L60
2
1
0_0805_5%
+1.2V_CKVDD
1
1
2
2
1
2
2
1
1
2
SB700
T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8
+1.2V_HT
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
22U_0805_6.3V6M
1U_0805_16V7K
1U_0805_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7
A17
A24
B17
J4
J5
L1
L2
+S5_3V
S5_1.2V_1
S5_1.2V_2
G2
G4
+S5_1.2V
1
2
R564
0_0805_5%
1
2
22U_0805_6.3V6M
C556
1U_0402_6.3V4Z 2
C559
1
1U_0402_6.3V4Z 2
C561
1
1U_0402_6.3V4Z 2
C562
1
0.1U_0402_16V4Z 2
C563
1
0.1U_0402_16V4Z 2
C564
1
0.1U_0402_16V4Z 2
C565
1
+1.2VALW
L64
+1.2VALW
+1.2_USB
USB_PHY_1.2V_1
USB_PHY_1.2V_2
+3VALW
0.1A/30mil/2vias ?
A10
B10
L65
0_0603_5%
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z 2
1 C569
1 C570
0_0603_5%
1
10U_0805_10V4Z
1U_0402_6.3V4Z 2
1U_0402_6.3V4Z 2
AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
2
C573
C574
C575
1
1
A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
+AVDD_USB
L66
2
1
0_0805_5%
+3VALW
<1.25A/50mil/4vias?
1
1
1
1
C576
C577
C580
C581
C583
C582
C584
1
1
1
1
1
1
1
2
2
2
2
2
2
2
A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5
V5_VREF
AVDDCK_3.3V
PLL
AA14
AB18
AA15
AA17
AC18
AD17
AE17
SATA I/O
<1.25A/50mil/4vias
USB I/O
1
10U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.2V_SATA
L63
2
1
0_0805_5%
+1.2V_HT
1
R592
1
R593
POWER
L61
2
1
0_0805_5%
0.8A/50mil/4vias
0.6A/50mil/4vias
+1.2V_SB_CORE
+PCIE_VDDR
L21
L22
L24
L25
0.45A/30mil/3vias
+1.2V_HT
CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4
CORE S0
2
2
2
2
2
2
2
2
Part 3 of 5
CLKGEN I/O
+3VS
1
1
1
1
1
1
1
1
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3.3V_S5 I/O
R12
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
L15
M12
M14
N13
P12
P14
R11
R15
T16
CORE S5
C528
C531
C530
C533
C549
C535
C539
C541
C542
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
PCI/GPIO I/O
SB700
L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21
IDE/FLSH I/O
+3VS
0.45A/40mil/3vias ?
A-LINK I/O
AVDDCK_1.2V
AVDDC
AE7
+V5_VREF
J16
+AVDDCK_3.3V
K17
C578
+AVDDCK_1.2V0.1U_0402_16V4Z
E9
+AVDDC
1K_0402_5% 2
2
C579
1U_0603_10V4Z
1
L67
2
1
0_0805_5%
2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z
1 R346
+5VS
+3VS
D14
H18
J17
J22
K25
M16
M17
M21
P16
CH751H-40PT_SOD323-2
F9
+3VALW
1
C585
C586
PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC
GROUND
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
Part 5 of 5
AVSSCK
A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24
P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
3
L17
+AVDDCK_1.2V
L68
2
1
0_0805_5%
2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z
+AVDDCK_3.3V
+1.2V_HT
1
C587
C588
L69
2
1
0_0805_5%
2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z
+3VS
1 C589
1 C590
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
22
of
56
REQUIRED STRAPS
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
AZ_RST_CD#
BOOTFAIL
TIMER
ENABLED
USE
DEBUG
STRAPS
RESERVED
RESERVED
ENABLE PCI
MEM BOOT
LPC_CLK1
RTC_CLK
LPC_CLK0
CLKGEN
ENABLED
INTERNAL
RTC
EC
ENABLED
GP17
BOOTFAIL
TIMER
DISABLED
IGNORE
DEBUG
STRAPS
DISABLE PCI
MEM BOOT
CLKGEN
DISABLED
DEFAULT
DEFAULT
DEFAULT
DEFAULT
Internal pull up
R355
10K_0402_5%
2
1
+3VALW
R354
10K_0402_5%
2
1
+3VALW
R353
10K_0402_5%
2
1
+3VALW
R352
10K_0402_5%
2
1
+3VALW
R351
10K_0402_5%
2
1
+3VALW
R350
10K_0402_5%
2
1
+3VS
DEFAULT
R349
10K_0402_5%
2
1
+3VS
EC
DISABLED
R348
10K_0402_5%
2
1
+3VS
EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)
R347
10K_0402_5%
2
1
+3VS
GP16
H,H = Reserved
DEFAULT
PULL
LOW
+3VALW
PULL
HIGH
R356
2.2K_0402_5%
2
<19>
PCICLK2
<19> PCI_CLK3
<19>
PCI_CLK4
<19>
PCI_CLK5
<19,33> CLK_PCI_EC
<19>
LPCCLK1
<19>
RTC_CLK
<20,33> HDARST#
<20>
GPIO17
<20>
GPIO16
R366
2.2K_0402_5%
2
1
R365
2.2K_0402_5%
2
1
R364
10K_0402_5%
2
1
R363
2.2K_0402_5%
2
1
R362
10K_0402_5%
2
1
R360
10K_0402_5%
2
1
R361
10K_0402_5%
2
1
R359
10K_0402_5%
2
1
R358
10K_0402_5%
2
1
R357
10K_0402_5%
2
1
DEBUG STRAPS
PULL
LOW
PCI_AD24
PCI_AD23
USE IDE
PLL
USE DEFAULT
PCIE STRAPS
RESERVED
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
USE
SHORT
RESET
BYPASS
PCI PLL
BYPASS
ACPI
BCLK
BYPASS IDE
PLL
USE EEPROM
PCIE STRAPS
R378
2.2K_0402_5%
2
1
R377
2.2K_0402_5%
2
1
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R373
2.2K_0402_5%
2
1
<19>
<19>
<19>
<19>
<19>
<19>
PCI_AD25
USE ACPI
BCLK
R376
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD26
USE PCI
PLL
R375
2.2K_0402_5%
2
1
PCI_AD28
PCI_AD27
USE
LONG
RESET
R374
2.2K_0402_5%
2
1
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
23
of
56
HDD Connector
JP9
1
C594
1
C591
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
10U_0805_10V4Z
C1032
@
1
@ C1033
2
0.1U_0402_16V4Z
1
@ C1034
C1035
0.1U_0402_16V4Z
+3VS_HDD1
@R1009
1
2
0_0805_5%
2
2 @
0.1U_0402_16V4Z
SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K
1 C592 SATA_RXN0_C
1 C596 SATA_RXP0_C
SATA_TXP0 <21>
SATA_TXN0 <21>
1
SATA_RXN0_C <21>
SATA_RXP0_C <21>
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
C595
0.1U_0402_16V4Z
C593
10U_0805_10V4Z
+5VS
+3VS_HDD1
+5VS
CONN@ SUYIN_127072FR022G523_RV
Multi-Bay Connector-option
2
+5VS
Max 3A
1
C600
10U_0805_10V4Z
1
C601
2
@ 150U_Y_6.3VM
PA@
PA@ 1
1
1
C604
C602
C603
PA@
PA@
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+5VS
CONN@ JP10
2
4
6
8
10
12
14
16
18
VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND
GND
TX+
TXGND
RXRX+
GND
GND
GND
GND
1
3
5
7
9
11
13
15
SATA_TXP1
SATA_TXN1
0.01U_0402_16V7K
SATA_RXN1
2
SATA_RXP1
2
0.01U_0402_16V7K
1 C605 SATA_RXN1_C
1 C606 SATA_RXP1_C
SATA_TXP1 <21>
SATA_TXN1 <21>
SATA_RXN1_C <21>
SATA_RXP1_C <21>
17
TYCO_2023087-3
CD-ROM Connector
JP11
+5VS
1
C615
10U_0805_10V4Z
1U_0603_10V4Z
1
C614
C613
0.1U_0402_16V4Z
GND
A+
AGND
BB+
GND
C616
10U_0805_10V4Z
DP
V5
V5
MD
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
SATA_TXP3
SATA_TXN3
0.01U_0402_16V7K
SATA_RXN3
2
SATA_RXP3
2
0.01U_0402_16V7K
R970 0_0402_5%
1
2
1 C612 SATA_RXN3_C
1 C611 SATA_RXP3_C
SATA_TXP3 <21>
SATA_TXN3 <21>
SATA_RXN3_C <21>
SATA_RXP3_C <21>
+5VS
CONN@ SUYIN_127382FR013G509ZR
4
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
24
of
56
1
@ R1067
+3VALW
1
R1055
2
3.6K_0402_5%
2
0_0805_5%
+3V_LAN
S
40 mils
1
+3V_LAN
2
LAN_DI
@ C1077
1
LAN_CS
@ R1056
100K_0402_5%
1
R1057
<33> LAN_POWER_OFF
2
0_0402_5%
Q144
SI2301BDS-T1-E3_SOT23-3
0.1U_0402_16V4Z
2
R1058
1 0.1U_0402_16V7K PCIE_PTX_IRX_P3
20
HSOP
<10> PCIE_PTX_C_IRX_N3
C488 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_N3
21
HSON
15
<10> PCIE_ITX_C_PRX_P3
16
<10> PCIE_ITX_C_PRX_N3
<15> CLK_PCIE_LAN
<15> CLK_PCIE_LAN#
17
18
<15> CLKREQ_LAN#
25
<11,14,19,26,27,32,33> PLT_RST#
27
R1059 1
R1060
1K_0402_1%
2 2.49K_0402_1%
<20> LAN_PCIE_WAKE#
26
28
ISOLATEB
LAN_X1
LAN_X2
ISOLATEB
46
41
42
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
HSIP
LED0
HSIN
RTL8102EL
REFCLK_P
REFCLK_M
CLKREQB
PERSTB
RSET
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
NC
LANWAKEB
ISOLATEB
VCTRL12A
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
CKXTAL1
CKXTAL2
R1061
15K_0402_5%
NC
23
24
NC
NC
NC
VCTRL12D
7
14
31
47
GND
GND
GND
GND
22
GNDTX
33
34
35
32
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS
38
LAN_ACTIVITY#
2
3
5
6
8
9
11
12
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
C628
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C631
C620
C621
C622
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to Pin48
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to Pin45
4
48
VCTRL12
VCTRL12
19
30
36
13
10
+LAN_VDD12
0.1U_0402_16V4Z
1
+EVDD12
+LAN_VDD12
C1080
C1079
2
1
@ 10U_0805_10V4Z
39
44
45
VDD33
VDD33
29
37
AVDD33
NC
NC
1
40
43
1
C632
0.1U_0402_16V4Z
C633
@ 10U_0805_10V4Z
+LAN_VDD12
+3V_LAN
Close to Pin19
+EVDD12
1
1
C630
Y5
2
+3V_LAN
C629
RTL8103EL-GR_LQFP48_7X7
LAN_X1
Close to Pin1,37,29
+LAN_VDD12
Close to Pin10,13,30,36
U44
<10> PCIE_PTX_C_IRX_P3
+3VS
1
10K_0402_5%
2
C1081
1U_0402_6.3V4Z
C1082
0.1U_0402_16V4Z
LAN_X2
25MHz_20pF_6X25000017
1
C653
C654
27P_0402_50V8J
2 27P_0402_50V8J
2
LAN Conn.
U19
C648 1
C647 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
LAN_MDI0+
LAN_MDI0LAN_CT0
LAN_CT1
LAN_MDI1+
LAN_MDI1-
1
2
3
4
5
6
7
8
RD+
RDCT
NC
NC
CT
TD+
TD-
JRJ45
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0RJ45_CT0
RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-
RJ45_MIDI0+ <35>
RJ45_MIDI0- <35>
C1083 1
C1084 1
LAN_ACTIVITY#
2 0.01U_0603_100V7-M RJ45_CT0_C
2 0.01U_0603_100V7-M RJ45_CT1_C
RJ45_MIDI1+ <35>
RJ45_MIDI1- <35>
75_0402_1%
1 R394
2
1
2
R396
75_0402_1%
RJ45_GND
2
C658
1000P_1206_2KV7K
NS681680
R391
+3V_LAN
13
1 300_0402_5%
14
8
C656
@68P_0402_50V8K
RJ45_MIDI1-
6
5
LAN_ACTIVITY#
LAN_SK_LAN_LINK#
RJ45_MIDI0-
RJ45_MIDI0+
@C657
+3V_LAN
68P_0402_50V8K
LAN_SK_LAN_LINK#1 R395
2
1 300_0402_5%
RJ45_MIDI1+
12
Yellow LEDSHLD1
PR4DETECT PIN1
16
9
PR4+
PR2PR3PR3+
PR2+
PR1DETCET PIN2
PR1+
SHLD1
10
15
Green LED+
Green LED-
FOX_JM36113-P1122-7F
CONN@
1
1
C661
C662
@ D55
PACDN042Y3R_SOT23-3
11
Yellow LED+
0.1U_0402_16V4Z
LANGND
4.7U_0805_10V4Z
9/20 DC234001G00
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
25
of
56
+3VS_WLAN
Max 1A
+1.5VS
2 R407 1
0_0805_5%
R406 2
1
0_0805_5%
C665
0.1U_0402_16V4Z
C666
C668
4.7U_0805_10V4Z
0.01U_0402_16V7K
2
C669
C670
4.7U_0805_10V4Z
+3VALW
+3VS
+1.5VS
Max 2.7A
+3VS_MINI PA@
+3VALW_WWAN
+3VS_MINI
PA@
R971 0_0603_5%
L78
4.7U_0805_10V4Z
2
1
1
2 0.01U_0402_16V7K
@ R972 0_0603_5%
0_1206_5%
PA@ 1
PA@ 1
PA@ 1
2
1
C785
C786
C787
1
1
PA@C671
@ C784
0.1U_0402_16V7K
2
2
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
JP14
MINI_PCIE_WAKE#
CH_DATA
CH_CLK
<15> CLK_PCIE_MCARD2#
<15> CLK_PCIE_MCARD2
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
<10> PCIE_PTX_C_IRX_N2
<10> PCIE_PTX_C_IRX_P2
<10> PCIE_ITX_C_PRX_N2
<10> PCIE_ITX_C_PRX_P2
R47
1 R49
<21> BT_COMBO_EN#
2 0_0603_5%
CH_CLK
1
0_0402_5%
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_WLAN
53
54
55
56
R48
1
3
5
7
9
11
13
15
<20> MINI_PCIE_WAKE#
<15> CLKREQ_MCARD1#
<15> CLK_PCIE_MCARD1#
<15> CLK_PCIE_MCARD1
WL_OFF#
PLT_RST#
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
+3VALW_WLAN
Max 0.3A
SMB_CK_CLK1
SMB_CK_DAT1
<10> PCIE_PTX_C_IRX_N5
<10> PCIE_PTX_C_IRX_P5
USB20_N8 <20>
USB20_P8 <20>
WL_LED#
<10> PCIE_ITX_C_PRX_N5
<10> PCIE_ITX_C_PRX_P5
WL_LED# <34>
+3VS_MINI
WL_OFF#
2
1
D59
CH751H-40PT_SOD323-2
PA@
R401 1
2 0_0603_5%
1
WLOFF#
<21>
PA@ C738
39P_0402_50V8J
CONN@
FOX_AS0B226-S99N-7F
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
4.7K_0402_5%
53
54
55
56
9/20 SP01000HS00/SP01000LX00
+1.5VS_MINI
4.7U_0805_10V4Z
PA@ 1
C782
PA@
C783
2
1
0.01U_0402_16V7K
0.1U_0402_16V4Z
JP13
+1.5VS_WLAN
G1
G2
G3
G3
+3VS_WLAN
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
Max 0.5A
PA@
L79
2
1
0_0805_5%
PA@ 1
C781
2
4
6
8
10
12
14
16
+3VS_MINI
UIM_PWR
1
UIM_DATA
UIM_CLK
UIM_RST
PA@
2
UIM_VPP
C1092
39P_0402_50V8J
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+1.5VS_MINI
1
PA@
C1093
39P_0402_50V8J
WW_OFF#
PLT_RST#
Max 0.3A
+3VALW_WWAN
SMB_CK_CLK1
SMB_CK_DAT1
PA@ C1094
39P_0402_50V8J
USB20_N10 <20>
USB20_P10 <20>
WW_LED#
WW_LED# <34>
G1
G2
G3
G3
<31>
CH_DATA
<31>
CH_CLK
<15> CLKREQ_MCARD2#
1
3
5
7
9
11
13
15
+3VALW
+3VALW_WLAN
+3VS_WLAN
@ R1043 0_0603_5%
1
2
R1042 0_0603_5%
1
2
1
C667
+1.5VS_WLAN
Max 0.5A
CONN@
FOX_AS0B226-S99N-7F
PA@ C1095
39P_0402_50V8J
PA@
C1096
39P_0402_50V8J
9/20 SP01000HS00/SP01000LX00
WW_OFF# 2
1
D60
CH751H-40PT_SOD323-2
New Card
WWOFF# <21>
RP@ U21
12 1.5Vin
14 1.5Vin
RP@ C681
2
1 0.1U_0402_16V4Z
+3VS
3
5
+3VS_PEC
@ R1087
1
<33,36,40> SYSON
20
1
EXP_CPPE#
9
18
3.3Vout
3.3Vout
+3VS_MINI
AUX_IN
AUX_OUT
SYSRST#
OC#
SHDN#
PERST#
STBY#
NC
CPPE#
GND
SI2301BDS-T1-E3_SOT23-3
Max 1.3A
15
+3V_PEC
19
8
PERST#
<33> WWAN_POWER_OFF
16
7
CPUSB#
THERMAL_PAD
RCLKEN
21
+3VS_MINI
JP6
R5538D001-TR-F_QFN20_4X4~D
UIM_PWR
UIM_DATA
UIM_CLK 1
2 UIMCLK
33_0402_5% UIM_RST
UIM_VPP
9/20 SP02000B000
R421
+3VS_PEC
JEXP
USB20_N11
USB20_P11
EXP_CPPE#
<20> SMB_CK_CLK1
<20> SMB_CK_DAT1
+1.5VS_PEC
SMB_CK_CLK1
SMB_CK_DAT1
MINI_PCIE_WAKE#
+3V_PEC
PERST#
+3VS_PEC
<15> CLKREQ_NCARD#
<15> CLK_PCIE_NCARD#
<15> CLK_PCIE_NCARD
<10> PCIE_PTX_C_IRX_N0
<10> PCIE_PTX_C_IRX_P0
<10> PCIE_ITX_C_PRX_N0
<10> PCIE_ITX_C_PRX_P0
CLKREQ_NCARD#
EXP_CPPE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
4.7U_0805_10V4Z
1
RP@
C677
RP@
C678
1
2
3
4
5
6
7
1
2
3
4
5
6
7
9/20 SP02000IQ00
G1
G2
8
9
ACES_88266-07001
CONN@
2
0.1U_0402_16V4Z
R1037
+1.5VS_PEC
UIM_DATA
RP@
C683
UIM_PWR
@ 10K_0402_5%
4.7U_0805_10V4Z
1
1
RP@
C682
0.1U_0402_16V4Z
1 PA@ 1 PA@
C1070 C1071
2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
4
+3V_PEC
4.7U_0805_10V4Z
1
RP@
C684
CONN@ SANTA_130801-5_LT
3.3Vin
3.3Vin
USE TI TPS2231MRGPR
<20>
<20>
0_0603_5%
2
+3VALW
Max 0.65A
2
G
17
<28,33,36,38,41> SUSP#
<20> EXP_CPPE#
+1.5VS_PEC
@ Q167
2
4
10
3
11
13
RP@ C679
2
1 0.1U_0402_16V4Z
RP@
2
1 0.1U_0402_16V4Z
Max 0.275A
C680
+3VALW
RP@
PLT_RST# 1 R54
2
<11,14,19,25,27,32,33> PLT_RST#
0_0402_5%
1.5Vout
1.5Vout
RP@
C685
2
0.1U_0402_16V4Z
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
R ev
0.3
Sheet
E
26
of
56
+VCC_OUT
+VCC_4IN1
+VCC_4IN1
JREAD
U22
IN
EN
1
5
OUT
OUT
GND
@ G5250C2T1U_SOT23-5
@ C896
SDCMD_MSBS_XDWE#34
XDWP#_SDWP#
33
XD_ALE
35
XD_CD#
40
XD_RB#
39
XD_RE#
38
XDCE#
37
XD_CLE
36
@ R123
1U_0603_10V4Z
150K_0402_5%
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
+VCC_4IN1
21
28
7 IN 1 CONN
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW
20
14
12
30
29
27
23
18
16
25
1
SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
SD-WP-SW
XDWP#_SDWP#
11
31
7IN1 GND
7IN1 GND
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
26
17
15
19
24
22
13
MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#
41
42
7IN1 GND
7IN1 GND
+VCC_4IN1
MSCLK
2
@ C902
100P_0402_25V8K
2
@ C901
100P_0402_25V8K
D40
XD_CD#
1
3
C696
270P_0402_50V7K
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
@ C900
100P_0402_25V8K
1
R86
200K_0402_5%
XD_RE#
+1.8VS
+1.8VS_OUT
1
R1020
20mil
R124
R111 4.7K_0402_5%
1
DAN202U_SC70
+3VS
C892
0.1U_0402_16V4Z
1
C688
1U_0402_6.3V4Z
1
1
C687
2
2
10U_0805_10V4Z
2 2
G
10K_0402_5%
C893
2
1
0_0603_5%
@
2
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z C695
Q54
1
CPPE#
Power Circuit
0_0402_5%
1
2
R369
+3VS_CR
+3VS
2N7002_SOT23-3
CR_WAKE#
XDCD1#_MSCD# 2
@ R411
100_0402_5%
@ R412
100_0402_5%
@ R413
100_0402_5%
<21>
2
1
R106 10K_0402_5%
XDCE#
2
SDCLK
C694
0.1U_0402_16V4Z
1
C689
10U_0805_10V4Z
CR_CPPE#
R121 4.7K_0402_5%
XDCD0#_SDCD#2
1
CONN@ TAITW_R015-B10-LM
R383 2
1
0_0805_5%
<20>
XD_RB#
+3VS_CR
10K_0402_5%
1
SD-VCC
MS-VCC
XD-VCC
32
10
9
8
7
6
5
4
@ 0.1U_0402_16V4Z
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
3
4
1
C895
+VCC_4IN1
40mil
+3VS
R45
XDWP#_SDWP# 2
XDCD0#_SDCD#
<15> CLK_PCIE_MCARD0#
<15> CLK_PCIE_MCARD0
3
4
<10> PCIE_ITX_C_PRX_N1
<10> PCIE_ITX_C_PRX_P1
9
8
C693 1
C697 1
<10> PCIE_PTX_C_IRX_N1
<10> PCIE_PTX_C_IRX_P1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1
2 R114
1
8.2K_0402_5%
APREXT
12mil
2 R409
1
10K_0402_5%
+3VS_CR
+5VS_LED
APCLKN
APCLKP
APVDD
APV18
1mA TAV33
58mA
APRXN
APRXP
11
12
45mA DV33
DV33
DV33
25mA DV18
DV18
APTXN
APTXP
APREXT
38
39
PCIES_EN
PCIES
JMB385
R370
1
2
<11,14,19,25,26,32,33> PLT_RST#
XRSTN
XTEST
470_0402_5%
CPPE#
PAD T45
D5
HT-F196BP5_WHITE
2
+VCC_OUT
0_0402_5%
@ Q53
2
G
2N7002_SOT23-3
CR_LED#
At least 20mils
SEEDAT
SEECLK
15
16
NC
NC
NC
CR1_CD1N
CR1_CD0N
APGND
17
CR1_PCTLN
GND
GND
GND
GND
CR1_LEDN
Ripple 100mV
19
20
44
18
37
Ripple 250mV
48
47
46
45
43
42
41
40
29
28
27
26
25
23
22
C691
Ripple 100mV
2 R1021 1
0_0603_5%
C692
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
Ripple 250mV
+1.8VS_OUT
1
XD_SD_MS_D0
C686
XD_SD_MS_D1
0.1U_0402_16V4Z
2
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
R457 2
XDWP#_SDWP#
R456 2
XD_CLE
R455 2
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE
C690
0.1U_0402_16V4Z
1 22_0402_5%
1 22_0402_5%
1 22_0402_5%
SDCLK
MSCLK
XDCE#
34
35
36
6
24
31
32
33
1 R1070
XDCD1#_MSCD#
XDCD0#_SDCD#
13
14
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
5
10
30
J MB385-LGEZ0A_LQFP48_7X7
@ R454
4.7K_0402_5%
2
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
27
of
56
CODEC POWER
+3VS_HDA
+3VDD_CODEC
R885
1
2
BLM18BD601SN1D_0603
+3VS
C734
+3VS
C733
+VDDA_CODEC
R978
1
2
BLM18BD601SN1D_0603
0.1U_0402_16V4Z
1
+VDDA_CODEC_R
R979
1
2
0_0603_5%
C1046
C730
0.1U_0402_16V4Z
1U_0603_10V4Z
+5VALW
W=40Mil
1
C728
C731
1U_0603_10V4Z
+VDDA_CODEC
U32
2
0.1U_0402_16V4Z
<26,33,36,38,41> SUSP#
IN
OUT
5
1
GND
SHDN
BYP
C729
G9191-475T1U_SOT23-5 1
0.1U_0402_16V4Z
(4.75V(4.56~4.94V))
300mA
2.2U_0805_16V4Z
C732
0.1U_0402_16V4Z
U27
+VDDA_CODEC_R
HDA_BITCLK_CODEC
DVDD_CORE
VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2
25
AVDD1*
38
AVDD2**
GPIO 3
VREFOUT-E / GPIO 4
3
+3VS_HDA
R525
@ 47_0402_5%
2
32
1
C745
@ 33P_0402_50V8K
DVDD_CORE*
HDA_BITCLK_CODEC
<20> HDA_BITCLK_CODEC
HDA_SDOUT_CODEC
<20> HDA_SDOUT_CODEC
2
R522 1
<20> HDA_SDIN0
<20> HDA_SYNC_CODEC
<20> HDA_RST#_CODEC
<17>
EC_BEEP
R563 1
<20>
SB_SPKR
R524 1
2 47K_0402_5%
R523 1
2 10K_0402_5%
2 33_0402_5%
8
10
HDA_RST#_CODEC
11
2 @ 47K_0402_5%
HD A_SYNC_CODEC
DMIC_CLK
<33>
C956
RP@
R230 1
2 0.1U_0402_16V4Z
22_0402_5%
2
46
R982 1
RP@R910 1
2 5.1K_0402_1%
2 39.2K_0402_1%
RP@ C979
0.1U_0402_16V4Z
SENSEB#
1
34
37
18
19
20
27
26
42
7
31
43
GPIO 6
44
45
SPDIF_OUT
SPDIF_OUT <35>
PAD
48
T21
SDO
SDI_CODEC
VREFOUT-B
SYNC
VREFOUT-C
28
VREFOUT_B
SENSE_A
13
SENSE
PORTA_R
41
HP_OUTR
PORTA_L
39
HP_OUTL
22
MIC_EXTR
21
MIC_EXTL
PORTB_R
PORTB_L
PORTC_R
NC
PORTC_L
NC
PORTD_R
NC
VREFFILT
PORTE_R
AVSS1*
PORTE_L
24
MIC_INR
23
MIC_INL
1
1
1
1
2
2
2
2
1
5.1K_0402_1%
20K_0402_1%
39.2K_0402_1%
10K_0402_1%
0.1U_0402_16V4Z
HP_OUTR <29>
EXTMIC_DET# <29>
JACK_DET# <29,35>
INTMIC_DET# <29>
HP_OUTL <29>
1
C981
1
C982
SENSE_B / NC
NC
+VDDA_CODEC_R
R548
R569
R571
R570
C951
DMIC_CLK
NC / OTP
VREFOUT_B <29>
29
RESET#
PORTD_L
10U_0805_10V4Z
VC_REFA
C744 1
2
DMIC_DAT <17>
30
MONO_OUT
SPDIF OUT0
EAPD_CODEC <33>
GPIO 5
BITCLK
EAPD_CODEC
DVDD_IO
2
1
33
C913
1U_0603_10V4Z CAP2
MONO_INR
2
12 PCBEEP
0.1U_0402_16V4Z
C955
40
+VDDA_CODEC_R
<35> SENSE_B#
47
MIC_EXT_R <29>
1U_0603_10V6K
2
1U_0603_10V6K
PRM@ C983
1
0.022U_0603_25V7K
2
Jack MIC
MIC_EXT_L <29>
MIC_IN_R <29>
36
LINE_OUT_R
35
LINE_OUT_L
15
DOCK_MICR
14
DOCK_MICL
PRM@ C984
1
LINE_OUT_R <29>
Internal MIC
MIC_IN_L <29>
Internal SPKR.
LINE_OUT_L <29>
1
RP@C985
1
RP@C986
RM@
R911
0_0603_5%
0.022U_0603_25V7K
2
1
2
PR@R422 0_0603_5%
2
+3VDD_CODEC
DOCK_MIC_R <35>
1U_0603_10V6K
DOCK MIC
DOCK_MIC_L <35>
1U_0603_10V6K
AVSS2**
PORTF_R
17
PORTF_L
16
DVSS**
92HD71B7X5NLGXA1X8_QFN48_7X7
@ C746
1
2
0.1U_0402_16V4Z
@ C747
1
2
0.1U_0402_16V4Z
SENSE A
@ C748
1
2
0.1U_0402_16V4Z
SENSE B
@ C749
1
2
0.1U_0402_16V4Z
Port
Resistor
Port
Resistor
39.2K
39.2K
@ R1006
1
2
0_0402_5%
20K
20K
@R195
1
2
0_0805_5%
10K
10K
R198
1
2
0_1206_5%
5.11K
H
A
5.11K
GND
Security Classification
GNDA
GNDA
B
Use an 80mil to
connection or place
a 1206 resistor under
CODEC with double
vias.
<29>
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
R ev
0.3
Sheet
28
of
56
+5VAMP
+5VS
C766
10U_0805_10V4Z
C767
C1051
SPEAKER
R594
1
2
0_1206_5%
0.1U_0402_16V4Z
1
GAIN0
GAIN1
6dB
10dB
JP20
Av(inv)
SPKRSPKR+
SPKLSPKL+
1
2
3
4
+5VS
0.1U_0402_16V4Z
15.6dB
1
VDD
PVDD1
PVDD2
2
2 0.022U_0603_25V7K
2
47P_0402_50V8J
1
1
2 0.022U_0603_25V7K
2
47P_0402_50V8J
C1055
0_0402_5%
ROUT-
2
1
21.6dB
2
3
18
SPKR+
14
SPKR-
SPKL+
SPKL-
R1003
R1004
@ 100K_0402_5%
LIN+
100K_0402_5%
LOUT+
LINLOUT-
R906
2
1
PRM@1K_0402_5%
+VDDA_CODEC
MIC_IN_L
R905
PR@
4.7K_0402_5%
2
10
1
BYPASS
<28>
<28>
C1044
1U_0805_50V4Z
MIC_IN_L
MIC_IN_R
MIC_IN_L
MIC_IN_R
PRM@ D61
PSOT24C_SOT23-3
2
1
+3VS
PRM@ R955 10K_0402_5%
INTMIC IN
R951
PR@
100K_0402_5%
JP42
1 1
2 2
3 3
4 4
5
6
<33> ANA_MIC_DET
1
21
20
13
11
1
+VDDA_CODEC
PRM@ C743
1U_0603_10V4Z
1
2
PRM@R904
4.7K_0402_5%
MIC_IN_R
12
SHUTDOWN
GND1
GND2
GND3
GND4
19
THERMAL PAD
NC
EC_MUTE#
<33> EC_MUTE#
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
<28> LINE_OUT_L
C1041
ROUT+
1
1
C1054
RIN-
GND1
GND2
CONN@ E&T_3806-F04N-02R
C1040
R1005
17
GAIN1
C1053
2 0.022U_0603_25V7K
2
47P_0402_50V8J
GAIN0
5
6
1
C763
0_0402_5%
1
1
RIN+
C1050
R1001
100K_0402_5%
2 0.022U_0603_25V7K
2
47P_0402_50V8J
15.6dB
1
C762
<28> LINE_OUT_R
1
1
C1052
R1000
@ 100K_0402_5%
C1049
R1002
1
C761
2
100P_0402_50V8J
16
15
6
1
U28
1
C760
1
2
3
4
TPA6017A2_TSSOP20
D
ACES_88231-04001
CONN@
2
G
S
R103
10K_0402_5%
PA@
2
G
9/20 SP02000H700/SP02000H900
PR@Q160
2N7002_SOT23-3
PR@Q151
2N7002_SOT23-3
<28> INTMIC_DET#
GND1
GND2
R909
C742 1
1
R907
R908
MIC_EXT_R
<28>
MIC_EXT_L
4.7K_0402_5%
2
4.7K_0402_5%
<28>
1U_0603_10V4Z
2
1
0_0402_5%
<28> VREFOUT_B
R125
2
1
0_0402_5%
GNDA_DOCK_2
R126
2
1
0_0402_5%
GNDA_DOCK_1
GNDA_DOCK_2 <35>
MIC_EXT_R
RP@R977
1
EXTMIC IN
MIC_EXT_L
0_0603_5%
GNDA_DOCK
2
JP43
MIC_EXT_R
MIC_EXT_L
GNDA_DOCK_1 <35>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HP_OUT_R
HP_OUT_L
3
B+
RP@
S Q161
2N7002_SOT23-3
+5VL
CONN@ ACES_87213-1400G
Q147B
3
DOCK_LOUT_R
RP@
C775 150U_Y_6.3VM
DOCK_LOUT_CR_R
1
2
DOCK_LOUT_L
RP@
C776 150U_Y_6.3VM
DOCK_LOUT_CR_L
1
2
RP@R968
1
2 DOCK_LOUT_C_R
60.4_0603_1%
DOCK_LOUT_C_R <35>
RP@R969
1
2 DOCK_LOUT_C_L
60.4_0603_1%
DOCK_LOUT_C_L <35>
Q148B
3
RP@2N7002DW-7-F_SOT363-6
C773 150U_Y_6.3VM
HP_OUT_R
1
2
+
RP@ 2N7002DW-7-F_SOT363-6
HP_OUTL
6
RP@2N7002DW-7-F_SOT363-6
RP@2N7002DW-7-F_SOT363-6
<28>
Q148A
HP_OUTR
Q147A
9/20 SP02000H800
RP@
2N7002DW-7-F_SOT363-6
Q145B
4
5
RP@
2N7002DW-7-F_SOT363-6
Q145A
1
HP_DET#
<28>
CIR_IN
CIR_IN
2
G
<33,35>
RP@
R975
330K_0402_5%
EXTMIC_DET#
HP_DET#
RP@
R974
10K_0402_5%
6 1
RP@
R973
10K_0402_5%
RM@
R414
0_0402_5%
+3VALW
+3VALW
<28,35> JACK_DET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C774 150U_Y_6.3VM
HP_OUT_L
1
2
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
29
of
56
ACCELEROMETER
+3VS
+3VS_ACL
RP@
D44
2
RP@
R959
1
+3VS_ACL_IO
0_0603_5%
2
CH751H-40PT_SOD323-2
RP@ C1030
1 RP@
C1031
10U_0805_6.3V6M
0.1U_0402_16V4Z
SMB_CK_CLK0
+3VS_ACL_IO
1
RP@
R997
0_0402_5%
1
2
2
3
4
5
6
Vdd_IO
0011101b
SDA / SDI / SDO
GND
SDO
Reserved
Reserved
GND
GND
GND
INT 2
Vdd
INT 1
13
SMB_CK_DAT0
12
RP@ R998
0_0402_5%
1
2
11
SMB_CK_DAT0 <8,9,15,20>
10
9
HDD_HALTLED <34>
ACCEL_INT <19>
CS
+3VS_ACL
SCL / SPC
SMB_CK_CLK0 <8,9,15,20>
14
RP@
U63
LIS302DLTR_LGA14_3x5
RP@
2
R999
1
10K_0402_5%
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
30
of
56
Left side
4.7U_0805_10V4Z
+
2
C1121
0.1U_0402_16V4Z
TPS2061IDGN_MSOP8~N
1000P_0402_50V7K
C791
W=100mils
8
7
6
5
OUT
OUT
OUT
OC#
0.1U_0402_16V4Z
C790
GND
IN
IN
EN#
C789
150U_D_6.3VM
1
2
3
4
Max 0.5A
+USB_VCCA
D11
Max 2.5A
+USB_VCCA
U40
C788
USB CONNECTOR
+5VALW
1
VIN
IO1
IO2 GND
USB20_P2_R
<20>
@ PRTR5V0U2X_SOT143-4
L51
4
USB20_N2
<20>
USB20_P2
<21>
<21>
SATA_TXP2
SATA_TXN2
D12
+USB_VCCA
SATA_TXN2
4
3
VIN
1
2
3
4
USB20_N2_R
USB20_P2_R
WCM-2012-900T_4P
IO1
IO2 GND
SATA_TXP2
@ PRTR5V0U2X_SOT143-4
C792
C793
1
1
VBUS
DD+
GND
5
6
7
8
9
10
11
SATA_TXP2
SATA_TXN2
<21> SATA_RXN2_C
<21> SATA_RXP2_C
JP47
2 1000P_0402_50V7KSATA_RXN2
2 1000P_0402_50V7KSATA_RXP2
USB_EN#
USB
USB_EN#
<33> USB_EN#
<20> USB20_N0
<20> USB20_P0
GND
A+
ESATA
AGND
BB+
GND
12
13
14
15
1
2
3
4
5
6
7
8
9
10
+5VALW
JESAT
<20>
<20>
USB20_N1
USB20_P1
1
2
3
4
5
6
7
8
9
10
+5VALW
11
12
GND
GND
GND
GND
C1109
820P_0402_25V7K
GND1
GND2
ACES_87213-1000G
9/20 SP02000DX00
CONN@
CONN@ TYCO_1759576-1
JST_SM06B-XSRK-ETB(HF)
GND 8
GND 7
6 6
5 5
4 4
3 3
2 2
1 1
BT Connector
Finger printer
+3VAUX_BT
2
USB20_P6
USB20_N6
BT_LED
CONN@ JP55
CONN@ JP32
Q31
+3VS_FB
1
1
G
USB_EN#
@ D21
4 VIN
USB20_N7
IO1
USB20_P7
USB20_P6 <20>
USB20_N6 <20>
BT_LED <34>
CH_DATA <26>
CH_CLK <26>
1K_0402_5%
1K_0402_5%
2
2
D16
ACES 87213-0800G
1
2
3
4
5
6
GND
GND
+3VAUX_BT
USB20_N6
9/20 SP02000HC00/SP02000HB00
VIN
IO1
IO2 GND
USB20_P6
2
1
@ PRTR5V0U2X_SOT143-4
+3VS
Q24
ACES_85201-06051
CONN@
+3VAUX_BT
SI2301BDS-T1-E3_SOT23-3
9/20 SP01000B000
C798
R519
1U_0603_10V4Z
100K_0402_5%
C799
0.1U_0402_16V4Z
PRTR5V0U2X_SOT143-4
+3VAUX_BT
USB20_P6
USB20_N6
BT_LED
@ R517 1
@ R518 1
IO2 GND
JP39
1
2
3
4
5
6
7
8
10
9
8
7
6
5
4
3
2
1
+3VS_FB
R581
1
2
0_0603_5%
C832
0.1U_0402_16V4Z
USB20_N7
USB20_P7
<20> USB20_N7
<20> USB20_P7
GND2
GND1
8
7
6
5
4
3
2
1
+3VS
@ SI2301BDS-T1-E3_SOT23-3
+3VALW
C800
0.01U_0402_16V7K
C801
2
4.7U_0805_10V4Z
R520
<21>
BT_OFF
1
2
10K_0402_5%
1
C802
2
0.1U_0402_16V4Z
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
31
of
56
C484
+3VAL
2
0_0402_5%
<6,33,34,37> SMB_EC_CK1
<6,33,34,37> SMB_EC_DA1
20mils
CONN@
U29
8
0.1U_0402_16V4Z
2
0_0402_5% 1
C803
0.1U_0402_16V4Z
+3VL
<33>
U31
8
7
6
5
<33>
SPI_CS#
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
SPI_CLK
<33> EC_SO_SPI_SI
SPI_CS#
1
R221
1
R227
2
R229
INT_SPI_CS#
2
0_0402_5%
SPI_CLK_R
2
0_0402_5%
1 EC_SO_SPI_SI_R
0_0402_5%
45@ &U29
VSS
7
R521
100K_0402_5%
VCC
1
@ R995
+3VALW
1
R996
+3VL
HOLD
SA00001IT00
EC_SI_SPI_SO_R
2
R223
1
0_0402_5%
EC_SI_SPI_SO <33>
L
1
@ AT24C16AN-10SI-2.7_SO8
R526
100K_0402_5%
<19,33> SIRQ
<19,33> LPC_AD3
<19,33> LPC_AD1
LPC_DRQ#
SIRQ
PLT_RST#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#
10
CLK_PCI_SIO
LPC_DRQ# <19>
PLT_RST# <11,14,19,25,26,27,33>
LPC_AD2 <19,33>
LPC_AD0 <19,33>
CLK_PCI_SIO <19>
<19,33> LPC_FRAME#
H31
+3VALW
@ DEBUG_PAD
@ R232
22_0402_5%
1
9/20 ??????
@ C486
22P_0402_50V8J
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
32
of
56
Keyboard Connector
JP33
+3VL_EC
2
2
0.1U_0402_16V4Z
C808
+3VL
C809
2
2
1000P_0402_50V7K
+3VL_EC
R527
1
2
0_0805_5%
<20>
GATEA20
<20>
KB_RST#
<19,32> SIRQ
<19,32> LPC_FRAME#
<19,32> LPC_AD3
<19,32> LPC_AD2
<19,32> LPC_AD1
<19,32> LPC_AD0
<19,23> CLK_PCI_EC
<11,14,19,25,26,27,32> PLT_RST#
2
47K_0402_5%
<20>
EC_SCI#
<20,23> HDARST#
R533 1
C811
<34>
<34>
R538
10K_0402_5%
ESB_CLK
ESB_DAT
ESB_CLK
ESB_DAT
@ C1104
33P_0402_50V8K
LID_SW#
R1076
1
1
R1077
1
0_0402_5%
2 EC_CLK
2 EC_DAT
0_0402_5%
+3VL
R529
R531
R532
R513
<6,32,34,37>
<6,32,34,37>
<6>
<6>
2
R515
1 EC_DAT
4.7K_0402_5%
+3VL_EC
R543
4.7K_0402_5% <36>
ON/OFF#
<35> DOCK_SLP_BTN#
77
78
79
80
1
R542
E51_TXD
E51_RXD
ON /OFF#
2
1
R1063 10K_0402_5%
1
<34>
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
EC_CLK
EC_DAT
WL_BLUE_BTN
H_THERMTRIP#_EC
SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
<34> WL_BLUE_BTN
<6> H_THERMTRIP#_EC
<35>
CONA#
VLDT_EN
4.7K_0402_5%
2 EC_CLK
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
<20>
<20>
<20>
<34>
+3VL
R514
1
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
<36>
<34>
2
0_0402_5%
DIM_LED
NUM_LED#
C813
15P_0402_50V8J
1
2
RP@
C R Y2
Y7
NC
OUT
NC
IN
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
G PO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
XCLK1
XCLK0
V18R
@
R545
20M_0402_5%
32.768KHZ_12.5PF_Q13MC30610003
1
122
123
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
DA Output
IREF/DA2/GPIO3E
KSI0/GPIO30
DA3/GPIO3F
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
S M Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
AD
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
R528
+3VS
4.7K_0402_5%
2
1 SMB_EC_DA1
4.7K_0402_5%
2
1 SMB_EC_CK1
4.7K_0402_5%
2
1 SMB_EC_DA2
4.7K_0402_5%
2
1 SMB_EC_CK2
10K_0402_5%
1
2 WL_BLUE_BTN
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
1
0.1U_0402_16V4Z
+3VL_EC
2
12
13
37
20
38
PWM Output
GND
GND
GND
GND
GND
+3VL_EC
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
21
23
26
27
EC_PWM
FAN_PWM
EC_BEEP
ACOFF
63
64
65
66
75
76
BATT_TEMP
BATT_OVP
68
70
71
72
83
84
85
86
87
88
EC_PWM <17>
FAN_PWM <4>
EC_BEEP <28>
ACOFF
<38>
0.01U_0402_16V7K
ECAGND
C812
1
2
BATT_TEMP <37>
BATT_OVP <37>
ADP_I
<38>
ADP_ID
<37>
TP_BTN# <34>
ANA_MIC_DET <29>
TP_BTN#
TP_CLK
TP_DATA
R46
100
101
102
103
104
105
106
107
108
EC_RSMRST#
124
R516
150_0603_1%
JP48
5
6
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN_EC
SB_PWRGD
BKOFF#
TP_LED#
CIR_IN
<29,35>
NB_OTP <37>
FSTCHG <38>
STD_ADP <38>
CAPS_LED# <34>
BAT_LED# <34>
ON/OFFBTN_LED# <34>
SYSON
<26,36,40>
2
C814
1
2
3
4
+3VS
+5VL
DOCK_VOL_UP#
R589
10K_0402_5%
2
1
DOCK_VOL_DWN# 2
1
R590
10K_0402_5%
2
1
R541 10K_0402_5%
<43>
<21,38>
EC_RSMRST# <20>
EC_LID_OUT# <20>
EC_ON
<36,39>
WL_BLUE_LED# <34>
SB_PWRGD <6,20,43>
BKOFF# <17>
WWAN_POWER_OFF <26>
TP_LED# <34>
ENBKL
<11>
EAPD_CODEC <28>
EC_THERM# <21>
SUSP#
<26,28,36,38,41>
PWRBTN_OUT# <20>
R534
10K_0402_5%
1
2
R535
10K_0402_5%
TP_DATA
1
2
+5V_TP
TP_CLK
SUSP#
PWRBTN_OUT#
NMI_DBG#
1
2
3
4
9/20 SP01000KC00/SP010009O10
VR_ON
2
1
AC_IN
D54
CH751H-40PT_SOD323-2
2
1
+3VL_EC
R1040
150K_0402_5%
1
2
C1073
100P_0402_50V8J
G1
G2
ACES_85201-04051
CONN@
2 10K_0402_5%
+5VS_LED
EC_SI_SPI_SO <32>
EC_SO_SPI_SI <32>
SPI_CLK <32>
SPI_CS# <32>
CIR_IN
NB_OTP
FSTCHG
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
9/20 SP01000FF00/SP01000G300
2
100K_0402_5%
73
74
89
90
91
92
93
95
121
127
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GND1
GND2
AC_LED# <37>
DOCK_VOL_UP# <35>
DOCK_VOL_DWN# <35>
VGATE
<43>
R1044
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ACES_85201-24051
CONN@
EC_MUTE# <29>
USB_EN# <31>
I2C_INT
<34>
MUTE_LED <35>
TP_CLK
<34>
TP_DATA <34>
119
120
126
128
110
112
114
115
116
117
118
25
26
DAC_BRIG <17>
VCTRL
<38>
IREF
<38>
AC_SET
<38>
IR EF
97
98
99
109
AGND
2
@ 33_0402_5%
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
69
1
2
3
4
5
7
8
10
For EMI
@ C213
@ C609
@ C754
@ C756
@ C757
@ C758
@ C759
@ C764
@ C768
@ C769
@ C822
@ C823
@ C824
@ C825
@ C826
@ C875
@ C876
@ C877
@ C878
@ C884
@ C885
@ C886
@ C887
@ C888
<43>
SYSON
R536
100K_0402_5%
R547
1
SUSP#
R539
100K_0402_5%
PCI_SERR# <19>
0_0402_5%
1
4.7U_0805_10V4Z
+3VS
KB926QFC0_LQFP128_14X14
TP_BTN#
R1050
1
2
10K_0402_5%
C R Y1
+3VL_EC
1
C815
15P_0402_50V8J
ECAGND
R530
2
@ 15P_0402_50V8J
GATEA20
KB_RST#
SIRQ
LPC_LFRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
C1105
22U_A_4VM
@
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
U33
11
24
35
94
113
C810
1
+EC_AVCC
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
C807
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C806
+3VL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C805
1000P_0402_50V7K
67
0.1U_0402_16V4Z
1
9
22
33
96
111
125
0.1U_0402_16V4Z
1
1
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
+EC_AVCC
L80
0_0603_5%
EC DEBUG port
<25> LAN_POWER_OFF
LAN_POWER_OFF
E51_RXD
R544
1
C816
2
0.1U_0402_16V4Z
L81
1
2
0_0603_5%
0_0402_5%
E51_TXD
2007/08/02
Issued Date
0_0603_5%
Security Classification
2
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
Title
R ev
0.3
Sheet
33
of
56
TP ON/OFF
5
6
TP_BTN#
JP37
TP_BTN#
5
6
5
6
1000P_0402_50V7K
0.1U_0402_16V4Z
1
R1046 1
R1048 1
R1049 1
I2C_INT
YELLOW
2
D
1
2
RP@R42
0_0402_5%
2
G
EC_DA1
I2C_INT
2
1
RM@R558 10K_0402_5%
PRM@
D19
+3VL
C256
0.1U_0402_16V4Z
1
2
EC_CK1
ESB_CLK1
ESB_DAT1
I2C_INT
JP36
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_85201-1005N
CONN@
9/20 SP01000H400
+3VL_CAP
@ PJP605
PAD-OPEN 2x2m
HT-297UY5/BP5_YELLOW-WHITE
HDD_HALTLED# <21>
1
10K_0402_5%
3
1
1
2
3
WHITE
HDD_HALTLED <30>
@ 2N7002_SOT23-3S
2
G
Q153 S
2N7002_SOT23-3
3
2
6
1
2N7002DW-7-F_SOT363-6
HT-297UY5/BP5_YELLOW-WHITE
PA@
D17
WHITE
<21> SATA_LED#
3
2N7002DW-7-F_SOT363-6
Q156
@ R985
YELLOW
D18
5
Q7A
HT-297UY5/BP5_YELLOW-WHITE
+5VS
WHITE
Q7B
+3VL
NUM_LED#
2
0_0402_5%
R983
200_0402_5%
YELLOW
10K_0402_5%
200_0402_5%
ESB
S MB_EC
2 RP@ 0_0402_5%
2 RP@47_0402_5%
2 RP@47_0402_5%
RP@C254
0.047U_0402_16V7K
+5VS_LED
R20
ENE
CY
+5VS_LED +3VS
R984
200_0402_5%
<33>
1
R1047
RP@
<6,32,33,37> SMB_EC_DA1
R988
RP@
200_0402_5%
RM@ 0_0603_5%
+5VS_LED
+3VL_R
2 RM@ 0_0402_5%
2 RM@ 0_0402_5%
@ 10P_0402_50V8J
<33>
R987
R555
RP@ 0_0603_5%
2
R1034 1
WL_BLUE_LED# R1035 1
<33> WL_BLUE_BTN
C777
<6,32,33,37> SMB_EC_CK1
<33>
ESB_CLK
<33>
ESB_DAT
+5VS
EC_CK1
EC_DA1
2 RM@ 0_0402_5%
2 RM@ 0_0402_5%
RP@ C1119
0.1U_0402_16V4Z
C780
@4.7U_0805_10V4Z
HDD/G-Sensor LED
R554
ON/OFFBTN_LED# R1065 1
ON /OFF#
R1066 1
<35,36,42> SYSON#
R496
@ 10_0402_5%
ACES_88020-12101
CONN@
@ C1103
2
1
+3VL_CAP +5VALW_LED
RP@C255
0.047U_0402_16V7K
@ R1075
2
1
47_0402_5%
ESB_DAT1
SWITCH BOARD.
@ C821
2 100P_0402_50V8J
33P_0402_50V8K
@ Q85
SI2301BDS-T1-E3_SOT23-3
GND
GND
GND
GND
GND
GND
1
C779
2
33P_0402_50V8J
HDA_BITCLK_MDC <20>
13
14
15
16
17
18
1
C778
2
RP@C1102
2
1
+3VS
+3VS
RP@R1074
2
1
0_0402_5%
ESB_CLK1
+3VS
G
1 R495
2HDA_SDIN1_MDC
33_0402_5%
<33>
<33>
<20> HDA_SDOUT_MDC
<20> HDA_SYNC_MDC
<20> HDA_SDIN1
<20> HDA_RST#_MDC
2
4
6
8
10
12
TP_CLK
TP_DATA
+5V_TP
0_0603_5%
2
3
2
4
6
8
10
12
TP_CLK
TP_DATA
@ C820
100P_0402_50V8J 2
Max 0.5A
R235
1
JP25
1
3
5
7
9
11
1
2
3
4
1
2
3
4
9/20
SP01000KC00/SP01E000900
+5VALW
1
3
5
7
9
11
G1
G2
ACES_85201-04051
CONN@
9/20 SP01000J100
9/20 STANDOFF (H= 5.0 mm) ES000000800
<33>
ACES_85201-04051
CONN@
D31
PSOT24C_SOT23-3
0.1U_0402_16V4Z
C257
G1
G2
1
2
3
4
SW1
SMT1-05-A_4P
3
1
4.7U_0603_6.3V6K
C1098
1
ON /OFF#
2
ON/OFFBTN_LED# 3
4
C819
0.1U_0402_16V4Z
R1038
@ 10K_0402_5%
2
JP1
+5VALW_LED
TP_DATA
TP_CLK
Max 0.5A
+5V_TP
M/B TO TP/B
+3VALW
<33>
ON/OFF#
<33> ON/OFFBTN_LED#
TP_LED#
TP_LED#
<33>
WHITE
+3VS
R989
D6
1
<33> BAT_LED#
1 R550
2
200_0402_5%
WL_BLUE_LED#
R552
2
HT-F196BP5_WHITE
2
G
1
R1007
2
0_0402_5%
WL_LED# <26>
1
PA@R1008
2
0_0402_5%
WW_LED# <26>
<33>
+3VL
JP40
1
+5VALW_LED
R1025
D8
1
C1100
0.1U_0402_16V4Z
100K_0402_5%
2
1 R549
2
200_0402_5%
G1
G2
5
6
C1101
10P_0402_50V8J
ON/OFFBTN_LED#
1
2
3
4
ACES_85201-04051
CONN@
BT_LED <31>
470_0402_5%
WHITE
1
2
3
4
LID_SW#
D7
POWER LED
D
Q55
2N7002_SOT23-3
+5VS_LED
WHITE
WL/WW_LED#
2
1
D57
CH751H-40PT_SOD323-2
<33> WL_BLUE_LED#
+3VS
47K_0402_5%
HT-F196BP5_WHITE
<33> CAPS_LED#
R1041
2
1
@ 10K_0402_5%
HT-F196BP5_WHITE
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.3
Sheet
E
34
of
56
RP@
C831
1000P_0402_50V7K
DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on
<16> RED_L
<16> GREEN_L
<16> BLUE_L
<16> D_DDCDATA
<16> D_DDCCLK
<16> D_HSYNC
<16> D_VSYNC
<20> USB20_N3
<20> USB20_P3
<25>
<25>
<25>
<25>
RP@
PJP5
+5VS
+3VALW
RP@
2
2
1K_0402_5%
2
1K_0402_5%
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+
+V_BATTERY
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+
B+
1
R586
1
R585
D_DDCDATA
D_DDCCLK
D_HSYNC
D_VSYNC
USB20_N3
USB20_P3
D43
CRT_Red
CRT_Green
CRT_Blue
DDC_DATA
DDC_Clock
Hsync
Vsync
USBUSB+
Digital gnd
MDI3MDI3+
MD2IMDI2+
MDI1MDI1+
MDI0MDI0+
Battery out
Battery out
45
46
GND
GND
Digital gnd
TV Luma
TV chroma
TV composite
TV ground
CIR input
PWR_ON
Mute_LED
Sleep Botton
Jack Detect
VOL_up
VOL_down
SPDIF
Audio Output gnd
Right headphone
Left headphone
Mic_Right
Mic_Left
Mic gnd
Dock_present
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
GND
GND
GND
GND
41
42
43
44
PAD-OPEN 2x2m
1
38
40
34
36
30
32
26
28
22
24
18
20
14
16
10
12
6
8
2
4
DOCK_PWR_ON
TV_LUMA_L
TV_CRMA_L
TV_COMPS_L
PAD
PAD
PAD
CIR_IN
DOCK_PWR_ON
MUTELED
DOCK_SLP_BTN# RP@
JACK_DET#
R_VOL_UP#
RP@
R_VOL_DWN#
RP@
SPDIFO_L
AUDIO_OGND
DOCK_LOUT_C_R
DOCK_LOUT_C_L
DOCK_MIC_R_C
DOCK_MIC_L_C
AU DIO_IGND
DOCK_PRESENT
T51
T52
T53
CIR_IN
1
<29,33>
2
R591
MUTE_LED <33>
DOCK_SLP_BTN# <33>
JACK_DET# <28,29>
DOCK_VOL_UP# <33>
DOCK_VOL_DWN# <33>
1K_0402_5%
R567 1
R568 1
DOCK_VOL_UP#
DOCK_VOL_DWN#
2 200_0402_5%
2 200_0402_5%
DOCK_LOUT_C_R <29>
DOCK_LOUT_C_L <29>
+DOCKVIN
3
CONN@ FOX_QL1122L-H212AR-9F
DAN202U_SC70
R_VOL_UP#
1
RP@
C843
1000P_0402_50V7K
2
G
<33>
Q33
2N7002_SOT23-3
RP@
RP@
C943
RP@R417 0_0603_5%
GNDA_DOCKA
1
2
RP@ 1
C944
R992
SPDIFO_L
AU DIO_IGND
1
RP@
2
0_0603_5%
2
220_0402_5%
SPDIF_OUT <28>
0.1U_0402_16V7K
R573
RP@
110_0402_5%
RP@
RP@
L94
FCM1608KF-601T02_2P
R942 10K_0402_5%
DOCK_MIC_R_C
1 DOCK_MIC_R_R 1
2
R943 10K_0402_5%
DOCK_MIC_L_C
2
1 DOCK_MIC_L_R
1
2
FCM1608KF-601T02_2P
RP@
L93
1
1
RP@
R980
1.21K_0402_1%
RP@
C921
RP@
C922
2 220P_0402_50V7K
220P_0402_50V7K 2
2
<28> DOCK_MIC_R
RP@
<28> DOCK_MIC_L
1
RP@
R944
1.21K_0402_1%
2
H41
@ H_2P8
H40
@ H_2P8
RP@
R647
1
1
1
H39
@ H_2P8
RP@
C945
2
MIC_Dock
GNDA_DOCK_2
<29> GNDA_DOCK_2
H37
@ H_2P8
220P_0402_50V7K
R128
0_0402_5%
GNDA_DOCK_1
<29> GNDA_DOCK_1
2
B
2
220P_0402_50V7K
1
H36
@ H_2P8
H35
@ H_2P8
C
Q149
@ MMBT3904_NL_SOT23-3
DOCK_LOUT_C_L
2
H34
@ H_2P8
R646
1
2
@ 0_0402_5%
AUDIO_OGND
2
0_0603_5%
1
RP@R418
R127
0_0402_5%
H33
@ H_2P8
R976
@ 33_0402_5%
DOCK_LOUT_C_R
2
220P_0402_50V7K
R566
2K_0402_5%
RP@
H32
@ H_2P8
SPDIF
+1.5VS
RP@
C942
1
1
CONA#
RP@
C844
1000P_0402_50V7K
2
R565
10K_0402_5%
RP@
DOCK_PRESENT 1
2
R572
22_0402_5%
RP@
1 1
+3VL_EC
R_VOL_DWN#
Q36
2N7002_SOT23-3
RP@
R588
10K_0402_5%
RP@
2
G
<34,36,42> SYSON#
RP@
AU DIO_IGND
2
1
AU DIO_IGND
H51
@ H_6P0X5P0N
H56
H_2P5N
C978
RP@
S
RP@
Close
Q18
2N7002_SOT23-3
2N7002_SOT23-3
to CODEC U27
RP@R415
0_0402_5%
1U_0603_10V6K
RP@
H57
H_2P8
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
47K_0402_5%
RP@R913
4
Q100
GNDA_DOCKA
2
B
2
2
G
DOCK_MIC_L_C
H52
@ H_1P5N
2
G
2 3
RP@
R912
1
2
10K_0402_5%
H55
@ H_5P6N
RP@ Q16
PMBT3904_SOT23
H53
H54
@ H_3P3X0P6N @ H_3P3X0P6N
SENSE_B# <28>
H48
@ H_3P3
RP@
R915
10K_0402_5%
1
R914
RP@
10K_0402_5%
H46
@ H_4P2
H44
@ H_4P2
H47
@ H_3P3
H43
@ H_4P2
H42
@ H_2P8
+3VS
Title
R ev
0.3
Sheet
E
35
of
56
DIM LED
+5VALW_LED
SI4800BDY_SO8
1U_0402_6.3V4Z
SI4800BDY_SO8
1
C1113
0.1U_0603_25V7K
C1112
0.1U_0603_25V7K
RU NON
C864
4.7U_0805_10V4Z
2 C840
4.7U_0805_10V4Z
@ R587
10K_0402_5%
1U_0402_6.3V4Z
RU NON
2 R152
1
B+
330K_0402_5%
1
D
SUSP
C834
Q17
2
2
2N7002_SOT23-3
G
S
1
@ C836
0.1U_0402_16V4Z
C1110
0.1U_0603_25V7K
DIM_LED#
<33>
DIM_LED
DIM_LED
@ Q51
2N7002_SOT23-3
2
G
+5VS_LED
@ Q166
PJP8
SI2301BDS-T1-E3_SOT23-3
1
1
@ C1069
0.1U_0402_16V4Z
PAD-OPEN 2x2m
+5VS
+1.8V TO +1.8VS
Q4
IRF8113PBF_SO8
8
7
6
5
1
2
3
+1.2V_HT
Q11
IRF8113PBF_SO8
C1114
0.1U_0603_25V7K
8
7
6
5
C846
1
2
3
1.8VS_ENABLE
R138 2
1
B+
330K_0402_5%
0.01U_0402_25V7K
750K_0402_5%
2
C1115
0.1U_0603_25V7K
2 R233
1
330K_0402_5%
1
1
1
R234
750K_0402_5%
0.01U_0402_25V7K 2
R137
4.7U_0805_10V4Z
B+
+5VL
Q12
VLDT_EN#
2
G
2N7002_SOT23-3
R598
SUSP
2
G
Q13
2N7002_SOT23-3
100K_0402_5%
2
C847
C837
4.7U_0805_10V4Z
1
C849
C1117
0.1U_0603_25V7K
4
1
C842
2
1U_0402_6.3V4Z
1
2
R420 0_0603_5%
4.7U_0805_10V4Z
1
C862
1U_0402_6.3V4Z
1
C1116
0.1U_0603_25V7K
+1.2VALW
10U_0805_10V4Z
1
2
C848
C841
DIM_LED#
+1.2VALW TO +1.2V_HT
+1.8VS
+1.8V
1
2
3
4
S
S
S
G
PAD-OPEN 2x2m
D
D
D
D
8
7
6
5
C1111
0.1U_0603_25V7K
SI2301BDS-T1-E3_SOT23-3
1
2
3
4
S
S
S
G
C839
0.01U_0402_25V7K
C833
D
D
D
D
Q14
+5VALW
4.7U_0805_10V4Z
1
C838
Q35
8
7
6
5
4.7U_0805_10V4Z
1
C835
@ Q32
PJP7
+5VS
+3VS
+3VALW
+5VALW
R419 0_0603_5%
1
2
+3VALW TO +3VS
+5VALW TO +5VS
2
1
S
Q42
@ 2N7002_SOT23-3
S 2N7002_SOT23-3
SUSP
Q50
2
G
S 2N7002_SOT23-3
SUSP
Q52
2
G
<26,33,40> SYSON
S 2N7002_SOT23-3
FM2
1
FM3
1
CF1
CF2
1
D
Q38
SYSON 2
G
2N7002_SOT23-3 S
2
1
SUSP
100K_0402_5%
SUSP
Q39
2
G
2N7002_SOT23-3
SUSP#
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CF3
1
B
<42>
<13>
VLDT_EN#
<26,28,33,38,41><33>
VLDT_EN
Issued Date
FM1
2
1
Security Classification
SYSON#
<34,35,42> SYSON#
R597
100K_0402_5%
Q49
R294
470_0805_5%
S 2N7002_SOT23-3
1
SYSON# 2
G
Q47
2
G
1
SUSP
R596
100K_0402_5%
R293
470_0805_5%
R292
470_0805_5%
R288
470_0805_5%
R595
+1.1VS
+5VL
+1.5VS
+5VL
+0.9V
+3VS
+5VL
Title
VLDT_EN#
1
2
G
EC_ON#
Q41
S 2N7002_SOT23-3
SYSON# 2
G
@ 470_0805_5%
1
Q37
S 2N7002_SOT23-3
VLDT_EN#2
G
R368
1
Q48
S 2N7002_SOT23-3
2
G
+1.2VALW
R284
470_0805_5%
R280
470_0805_5%
1
SUSP
Q46
S 2N7002_SOT23-3
2
G
+1.8V
2
R279
470_0805_5%
R239
470_0805_5%
SUSP
+1.2V_HT
2
+1.8VS
Q44
2N7002_SOT23-3
Discharge circuit
+5VS
2
G
<33,39> EC_ON
EC_ON#
VLDT_EN 2
G
Q40
2N7002_SOT23-3
R ev
0.3
Sheet
E
36
of
56
BATT1
+3VALW
PQ3
TP0610K-T1-E3_SOT23-3
+3VL
PR9
1
2
100K_0402_5%
2
BATT
499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2
ADPIN
PL2
SMB3025500YA_2P
2
1
PC13
390P_0402_50V7K
2
1
PC7
2200P_0402_50V7K
2
1
PC3
1000P_0402_50V7K
PC5
1000P_0402_50V7K
2
1
PC4
100P_0402_50V8J
2
1
@PJSOT24C_SOT23-3
2
1
PC2
100P_0402_50V8J
PD1
PC14
820P_0402_50V7K
2
1
PJP1
8
2
0
-
PU1A
LM358ADT_SO8
PR5
10K_0402_5%
2
1
3
PL1
SMB3025500YA_2P
1
2
105K_0402_1%
PR6 1
2
5
4
3
2
1
+DOCKVIN
0.01U_0402_25V7K
PC6
2
1
5
4
3
2
1
VIN
RLZ3.6B_LL34
1
2
PR3
10K_0402_5%
+5VALW
BATT_OVP <33>
ADP_SIGNAL
@1000P_0402_50V7K
PC15 0.1U_0402_16V7K
1
2
ACES_88334-057N
PC12
PD4
PR2
10K_0402_5%
2
PR8
2K_0402_5%
2 1
ADP_ID <33>
AC_LED# <33>
0.01U_0402_25V7K
PC1
2
1
VMB
BATT
PJP2
PR7
604K_0402_1%
1
2
+5VS
PD2
@SM05_SOT23
1
PC9
0.01U_0402_50V4Z
PH1
PC8
1000P_0402_50V7K
10KB_0603_1%_TH11-3H103FT
8
PR15
150K_0402_1%
2
2
1
1
2
O
IN-
EN0
PQ2
SSM3K7002FU_SC70-3
2
G
NB_OTP <33>
PQ4
@SSM3K7002FU_SC70-3
S
PC17
@1000P_0402_50V7K
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
<6,39>
@LMV331IDCKRG4_SC70-5
Security Classification
PC11
1000P_0402_50V7K
2
G
3
PR22
@150K_0402_1%
IN+
PQ1
@SSM3K7002FU_SC70-3
2
G
2
1
PR21
@2.21K_0402_1%
PC16
@0.22U_0603_10V7K
1
3
1
2
PR20
@150K_0402_1%
PR23
@10K_0402_5%
PU2
2
1
+5VALW
PR19
@15K_0402_1%
1
2
@10KB_0603_1%_TH11-3H103FT
PH2
BATT_TEMP <33>
@0.01U_0402_25V7K
PC18
2
1
+5VALW
PU1B
LM358ADT_SO8
+3VL
+5VS
+3VL
PR24
@100K_0402_5%
PR18
@47K_0402_1%
1
2
0
-
<38>
PR17
1K_0402_5%
2
2
PR11
150K_0402_1%
PR12
2.21K_0402_1%
SMB_EC_CK1 <6,32,33,34>
+5VS
PR16
6.49K_0402_1%
1
2
PC10
0.22U_0603_10V7K
SMB_EC_DA1 <6,32,33,34>
2
2
SMB_EC_DA1
SMB_EC_CK1
BAT_ID
+5VALW
PD3
@SM24.TC_SOT23-3
1
PR14
100_0402_5%
PR13
100_0402_5%
ENTRIP1 <39>
PR10
200K_0402_1%
1
2
SUYIN_200275MR008GXOLZR
1
2
CPU
1
2
PL4
HCB2012KF-121T50_0805
EC_SMD
EC_SMC
8
7
6
5
4
3
2
1
9
10
8
7
6
5
4
3
2
1
GND
GND
Title
R ev
0.1
Sheet
E
37
of
56
P4
B+
BATT
VI N
P2
PQ102
FDS6675BZ_SO8
R E GN 2
13
EXTPWR
LODRV
23
DPMDET
3
2
1
PC119
1U_0603_10V6K
1
2
BQ24740VREF
47K_0402_5%
PR119
2
G
BAT_ID
D
PQ111
SSM3K7002FU_SC70-3
PC118
0.1U_0402_10V7K
21
20
19
18
17
PR117
100K_0402_5%
1
2
PC121
100P_0402_50V8J
2
1
PQ110
FDS6690AS_SO8
CELLS
SRP
SRN
BAT
IADAPT
22
<37>
BATT
ADP_I
PC120
0.22U_0603_10V7K
2
1
<33>
16
15
PR118
10K_0402_5%
1
2
Charge Detector
2
1
3
D L _CHG
IAD APT
PR116
15K_0402_1%
PGND
SRSET
ISYNSET
14
PR115
100K_0402_1%
PC130
680P_0402_50V7K
PC129
1200P_0402_50V7K
2
1
5
6
7
8
PR139
4.7_1206_5%
PC117
1U_0603_10V6K
PC128
220P_0402_50V7K
2
1
1
2
PC105
4.7U_0805_25V6-K
2
1
1
1
PC132
4.7U_0805_25V6-K
24
PR112
0.015_1206_1%
1
2
PC116
4.7U_0805_25V6-K
2
1
REGN
PH
VADJ
VDAC
PQ106
DTC115EUA_SC70-3
BATT
PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2
PC115
4.7U_0805_25V6-K
2
1
LX_CHG
D H _C HG
25
AC OFF <33>
PQ108
AO4466_SO8
26
PC111
0.1U_0402_10V7K
1
2
4
3
2
1
HIDRV
BST_CHG
PC114
4.7U_0805_25V6-K
PU101
BQ24740RHDR_QFN28_5X5
VREF
27
28
BTST
PC113
4.7U_0805_25V6-K
2
1
PVCC
AGND
PC110
1U_0805_25V6K
1
2
PC131
680P_0603_50V7K
IADSLP
29
5
6
7
8
CHGEN
ACP
ACN
4
LPMD
ACDET
7
LPREF
ACSET
TP
1 1
VCTRL
CHG_B+
1SS355_SOD323-2
<33>
VI N
PR105
10K_0402_5%
AC OFF#
1SS355_SOD323-2
PR114
@0_0402_5%
1
2
PR103
47K_0402_5%
1
2
PR108
10_1206_5%
1
2
PD102
12
8
7
6
5
CHG_B+
PC104
4.7U_0805_25V6-K
1
2
2
PC109
@0.1U_0603_25V7K
PC103
4.7U_0805_25V6-K
1
2
PC108
0.1U_0603_25V7K
PC102
1U_0603_6.3V6M
1
2
2
1
VA DJ
PR113
143K_0402_1%
1
2
3
PL101
HCB2012KF-121T50_0805
2
+3VL
11
PQ109
SSM3K7002FU_SC70-3
3
10
1U_0603_6.3V6M
2
G
PD101
AC OFF#
C H GEN#
BQ24740VREF
PC112
1
2
PACIN_1 <39>
PR110
0_0402_5%
1
2
PR111
3K_0402_1%
1
2
PA CIN
PR140
100K_0402_5%
PC107
@0.01U_0402_16V7K
PR109
<26,28,33,36,41> SUSP#
150K_0402_5%
PQ107
SSM3K7002FU_SC70-3
AC SET
1
AC_SET
PC106
0.47U_0603_16V7K
2
1
2
G
ACD ET
PR104
0_0402_5%
1
2
2
1
PR106
200K_0402_5%
1
2
PR102
0.012_2512_1%
1
2
DTA144EUA_SC70-3
PQ104
PQ105
DTC115EUA_SC70-3
<33>
PQ103
SI4835BDY-T1-E3_SO8
1
8
2
7
3
6
5
PR101
47K_0402_5%
1
2
PC101
47P_0402_50V8J
PR107
47K_0402_1%
1
2
PQ101
SI4835BDY-T1-E3_SO8
1
2
3
8
7
6
5
PC122
@0.1U_0603_25V7K
1
2
1
2
<33>
PC124
0.1U_0603_25V7K
I R EF
PR121
200K_0402_1%
PR122
681K_0402_1%
1
2
PR123
1M_0402_5%
1
2
PR120
2
1
133K_0402_1%
PC123
0.1U_0402_10V7K
PD104
1SS355_SOD323-2
VI N
VIN_1
+3VL
PR124
1K_0402_5%
1
2
VI N
VI N
PU102A
LM393DG_SO8
PACIN
LM393DG_SO8
PR133
10K_0603_0.1%
PU102B
8
P
PR134
10K_0402_5%
PD103
RLZ4.3B_LL34
S
FSTCH G#
1
FSTCHG
STD_ADP <33>
PR136
60.4K_0402_1%
1
2 VIN_1
D
PQ113
SSM3K7002FU_SC70-3
2
G
3
<33>
1.24VREF
<21,33>
PQ112
SSM3K7002FU_SC70-3
3
2
G
PR135
10K_0603_0.1%
O
-
1
P
PC126
0.047U_0402_16V7K
AC_IN
PR127
10K_0402_1%
C H GEN#
PR130
2.15K_0402_1%
1
2
PR132
100K_0402_5%
2
1
PC125
0.1U_0603_25V7K
+3VL
PR131
133K_0402_1%
PR129
10K_0402_1%
2
1
VI N
PR126
100K_0402_1%
PR128
10K_0402_5%
2
1
PR125
47_1206_5%
+3VL
S
PU103
4
ACD ET
1.24VREF
ANODE
NC
2
4
APL1431LBBC-TR_SOT23-5
Security Classification
Issued Date
2007/05/29
Deciphered Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
Document Number
R ev
0.1
LA-3941P
Date:
CATHODE
NC
22P_0402_50V8J
100K_0402_1%
PR138
PC127
PR137
20K_0402_1%
REF
Sheet
38
of
56
2VREF_51125
PR302
30.9K_0402_1%
2
PR303
20K_0402_1%
1
2
PR304
20K_0402_1%
2
DRVL1
LX_5V
19
LG_5V
5
6
7
8
PC313
4.7U_0805_25V6-K
1
2
3
2
1
+5VALWP
PR317
100K_0402_5%
PC319
@22U_0805_6.3V6M
PC310
150U_D_6.3VM
PC315
680P_0603_50V8J
PQ304
SI4894BDY-T1-E3_SO8
VL
PR311
191K_0402_1%
1 2
PR316
4.7_1206_5%
+3VL
PU301
TPS51125RGER_QFN24_4X4
3
2
1
<6,37> EN0
PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
20
VCLK
18
VREG5
VIN
16
17
GND
EN0
PR312
1
2
1M_0402_1%
21
DRVL2
22
4
PR308
PC308
2.2_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2
12
LL1
23
PQ302
AO4466_SO8
5
6
7
8
LL2
PC305
4.7U_0805_25V6-K
2
1
1
ENTRIP1
VFB1
VREF
DRVH1
B++
PC314
@680P_0603_50V8J
VBST1
DRVH2
24
11
VBST2
13
9
10
PGOOD
15
PR315
@4.7_1206_5%
VO1
VREG3
PC309
3/5V_OK <20,41>
PC311
10U_0805_10V6K
150U_D_6.3VM
1 2
UG_3V
LG_3V
+3VALWP
1
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V
BST_3V
TONSEL
VO2
8
PR309
0_0402_5%
1
2
6
7
VFB2
P PAD
PR307
PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1
ENTRIP2
25
SKIPSEL
PC306
10U_0805_6.3V6M
14
8
7
6
5
1G
1S/2D
1S/2D
1S/2D
UG1_3V
D1
D1
G2
S2
AO4932_SO8
@22U_0805_6.3V6M
PR306
113K_0402_1%
2
PQ301
1
2
3
4
PC320
1
2
PC303
4.7U_0805_25V6-K
PR305
140K_0402_1%
1
B++
PC304
2200P_0402_50V7K
2
1
+3VLP
PC301
2200P_0402_50V7K
2
1
PC316
@0.1U_0402_25V4K
2
1
PC322
390P_0402_50V7K
2
1
PC321
2200P_0402_50V7K
2
1
PL301
HCB2012KF-121T50_0805
<BOM Structure>
1
2
ENTRIP1
B++
B+
ENTRIP2
PR301
13.7K_0402_1%
1
PC317
@0.1U_0402_25V4K
2
1
PC302
0.22U_0603_10V7K
B++
ENTRIP1
<37>
1
2
G
D
PQ305
SSM3K7002FU_SC70-3
PC312
0.1U_0603_25V7K
2VREF_51125
ENTRIP2
PQ306
SSM3K7002FU_SC70-3
2
G
PJP301
+5VALW
+3VALW
PAD-OPEN 2x2m
PAD-OPEN 4x4m
PJP303
VL
PQ307
SSM3K7002FU_SC70-3
2
G
+3VALWP
+5VL
VL
PJP304
PAD-OPEN 4x4m
EC_ON <33,36>
1
PAD-OPEN 2x2m
+5VALWP
<38> PACIN_1
PQ308
@SSM3K7002FU_SC70-3
1
2
2
G
PR318
@604K_0402_1%
PR313
100K_0402_5%
2
+3VL
+3VLP
PJP302
PC318
@0.047U_0603_16V7K
PR314
100K_0402_5%
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.1
Sheet
E
39
of
56
PR401
0_0402_5%
1
2
PL401
B+
2200P_0402_50V7K
PC405
4.7U_0805_25V6-K
PC404
2
1
HCB1608KF-121T30_0603
1
2
PC406
470P_0402_50V7K
2
LL
12
LX_1.8V
TRIP
11
V5DRV
10
1
+5VALW
DH_1.8V_1
PQ401
AO4466_SO8
PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
2
PR406
10.7K_0402_1%
PR407
@4.7_1206_5%
1
+
PC415
4.7U_0805_10V6K
2 2
DRVL
PR410
1
2
0_0402_5%
TPS51117RGYR_QFN14_3.5x3.5
DL_1.8V
3
2
1
2
PC412
@680P_0603_50V7K
PC408
220U_D2_4VY_R25M
DH _1.8V
13
3
2
1
14
15
TP
1
2
14.3K_0603_0.1%
DRVH
PGOOD
5
6
7
8
VFB
PC402
0.1U_0402_10V7K
V5FILT
VBST
PR408
VOUT
2
+1.8VP
PGND
PC409
1U_0603_10V6K
TON
2
2
1
0_0402_5%
EN_PSV
PU401
PR404
255K_0402_1%
1
2
PR405
BST1_1.8V 1
PR402
0_0402_5%
PR403
316_0402_1%
+1.8VP
1.8V_B+
4.7U_0805_25V6-K
PC403
2
1
BST_1.8V1
GND
1+5VALW
+5VALW
@0.1U_0402_25V4K
PC414
2
1
5
6
7
8
PC401
@1000P_0402_50V7K
<26,33,36> SYSON
+1.8VP
PQ402
SI4894BDY-T1-E3_SO8
1
2
PC413
@10P_0402_50V8J
PR409
10K_0603_0.1%
PJP401
+1.8VP
+1.8V
PAD-OPEN 4x4m
Security Classification
Issued Date
2007/05/29
Deciphered Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Size
Document Number
R ev
0.1
LA-3941P
D ate:
Sheet
D
40
of
56
+1.1VSP
PR501
11.5K_0402_1%
1
2
PR517
10_0402_5%
PR502
24.9K_0402_1%
PR503
18.7K_0402_1%
PR504
11.5K_0402_1%
B+++
B+
PL502
HCB2012KF-121T50_0805
2
1
PR505
0_0402_5%
+1.2VALWP
+1.1VSP
LX_1.1V
11
LL2
LG_1.1V
12
VBST1
22
BST_1.2V
DR VH2
DR VH1
21
UG_1.2V
LL1
20
LX_1.2V
19
LG_1.2V
2
UG1_1.2V
1
PR509
0_0402_5%
PR510
10.5K_0402_1%
PR512
33K_0402_5%
2
+5VALW
1
2
PC514
1U_0603_10V6K
PR514
3.3_0402_5%
PC513
0.1U_0402_10V7K
PC515
4.7U_0805_10V6K
PJP501
1
1 2
PC512
0.1U_0402_16V7K
+1.1VSP
<26,28,33,36,38> SUSP#
1K_0402_5%
PC520
470P_0603_50V8J
PR513
0_0402_5%
2
1
PR519
3/5V_OK <20,39>
PQ504
AO4468_SO8
+1.2VALWP
3
2
1
PR511
15.4K_0402_1%
1
2
PR516
4.7_1206_5%
PGND1
TRIP1
18
PQ503
FDS6690AS_NL_SO8
+1.2VALWP
PL503
3.3UH 30% MSCDRI-7030AB-3R3N 4.1A
1
2
TPS51124RGER_QFN24_4x4
17
V5IN
16
V5FILT
15
TRIP2
PGND2
14
13
PC507
0.1U_0402_10V7K
5
6
7
8
DR VL1
5
6
7
8
VO1
VFB1
VBST2
DR VL2
4
PR507
2.2_0402_5%
2
1
PC521
@0.1U_0402_25V4K
10
GND
23
PC504
4.7U_0805_25V6-K
2
1
UG_1.1V
PC516
470P_0402_50V7K
2
1
BST_1.1V
TONSEL
6
VO2
24
EN1
PC511
220U_B2_2.5VM
8
7
6
5
1 2
PC519
470P_0603_50V8J
1
2
3
PR515
4.7_1206_5%
PGOOD1
PC509
4.7U_0805_6.3V6K
2
1
PC508
220U_D2_4VY_R25M
EN2
1
PR508
PGOOD2
2
0_0402_5%
+1.1VSP
UG1_1.1V
PL501
2.2UH_PCMC063T-2R2MN_8A_20%
2
1
PC510
4.7U_0805_6.3V6K
1
2
1
2
3
PC506
PR506
0.1U_0402_10V7K
2.2_0402_5%
2
1 2
1
PQ502
AO4466_SO8
P PAD
3
2
1
AO4466_SO8
+1.1VSP
PU501
25
PQ501
VFB2
PC503
@0.022U_0603_25V7K
8
7
6
5
VCCP_POK
PC505
2200P_0402_50V7K
2
1
PC518
@0.1U_0402_25V4K
PC502
2200P_0402_50V7K
2
1
1
2
PC501
4.7U_0805_25V6-K
2
1
PC517
4.7U_0805_25V6-K
B+++
PR518
0_0402_5%
1
2
+1.1VS
B+++
PJP502
2
+1.1VS
+1.2VALWP
PAD-OPEN 4x4m
+1.2VALW
PAD-OPEN 4x4m
PJP503
+1.1VSP
+1.1VS
PAD-OPEN 4x4m
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.1
Sheet
E
41
of
56
+1.8V
+1.8V
PC603
1U_0603_16V6K
G2992F1U_SO8
VCNTL
GND
NC
VREF
NC
VOUT
NC
3
PR606
1K_0402_1%
+5VALW
VIN
8
2
TP
NC
PC613
10U_0805_10V4Z
VOUT
NC
PU603
+5VALW
PC609
@10U_0805_10V4Z
VREF
NC
VCNTL
PR601
1K_0402_1%
GND
VIN
1
2
PC602
@10U_0805_10V4Z
PC601
10U_0805_10V4Z
PU601
TP
PC612
1U_0603_16V6K
G2992F1U_SO8
PR608
0_0402_5%
PC606
@0.1U_0402_16V7K
2
G
+1.5VSP
1
2
PR607
5.1K_0402_1%
2
<36> SUSP
1
PC605
10U_0805_6.3V6M
PQ602
SSM3K7002FU_SC70-3
2
G
+0.9VP
PR604
@0_0402_5%
PR603
1K_0402_1%
D
2
<36> SUSP
2
1
PC604
0.1U_0402_16V7K
PQ601
SSM3K7002FU_SC70-3
2
PR602
0_0402_5%
2
1
PC611
0.1U_0402_16V7K
VREF1.5V
<34,35,36> SYSON#
PC614
10U_0805_6.3V6M
PC610
@0.1U_0402_16V7K
PU602
APL5508-25DC-TRL_SOT89-3
PAD-OPEN 3x3m
PJP603
+1.5VSP
+1.5VS
+2.5VS
IN
OUT
+2.5VSP
GND
1
+3VS
PR605
@150_1206_5%
2
+0.9V
PC607
1U_0603_6.3V6M
+0.9VP
PC608
4.7U_0805_6.3V6K
PJP601
PAD-OPEN 3x3m
PJP602
+2.5VSP
2
PAD-OPEN 3x3m
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
0.1
Sheet
E
42
of
56
8
7
6
5
1
2
PC258
2200P_0402_50V7K
1
2
4.7U_0805_25V6-K
2
UGATE NB1
1
2
1
PR239
0_0402_5%
3
2
1
UGATE0_1
+
2
47P_0402_50V8J
2
1
PC215
1000P_0402_50V7K
PC2532
1
68U_25V_M
47P_0402_50V8J
PC249
3300P_0402_50V7K
2
1
PC250
1800P_0402_50V7K
2
1
PC211
68U_25V_M
PC248
3300P_0402_50V7K
2
1
PC254
1800P_0402_50V7K
2
1
PC255
390P_0402_50V7K
2
1
PC261
2
1
PC213
4.7U_0805_25V6-K
2
1
PC214
2200P_0402_50V7K
2
1
PC212
4.7U_0805_25V6-K
2
1
PC235
4.7U_0805_25V6-K
2
1
PC230
@1000P_0402_50V7K
2
1
PR233
@4.02k_0603_1%
1
2
PC229
0.1U_0603_25V7K
+CPU_CORE_0
PC259
2
1
PQ208
IRFH7932TRPBF_PQFN
PC231
@180P_0402_50V8J
1
PL204
0.36UH_PCMC104T-R36MN1R17_30A_20%
47P_0402_50V8J
PC226
2200P_0603_50V7K
3
2
1
+CPU_CORE_0
PC256
1800P_0402_50V7K
2
1
PC257
390P_0402_50V7K
2
1
PC224
0.22U_0603_10V7K
47P_0402_50V8J
PR221
3.65K_0402_1%
2
1
PQ206
IRF8714TRPBF_SO8
49
TP
1
PR228
2.2_0603_5%
PC260
2
1
BOOT1
UGATE1_1
PC252
47P_0402_50V8J
2
1
25
4
PR226
1
2
0_0603_5%
2
1
2
PR229
4.7_1206_5%
1 2
1
PR244
4.7_1206_5%
2
1
UGATE1
3
2
1
PHASE1
26
27
PC222
2200P_0402_50V7K
2
1
LGATE1
28
CPU_B+
PR231
3.65K_0402_1%
2
1
29
PC240
2200P_0402_50V7K
2
1
30
1
ISP 0
PC221
4.7U_0805_25V6-K
2
1
LGATE0
5
6
7
8
31
PR217
@4.02k_0603_1%
1
2
PC220
4.7U_0805_25V6-K
2
1
32
+CPU_CORE_0
PL203
PC219
0.1U_0603_25V7K
PQ205
IRFH7932TRPBF_PQFN
PC236
4.7U_0805_25V6-K
2
1
PHASE0
PC237
4.7U_0805_25V6-K
2
1
33
3
2
1
UGATE0
PR242
PC218 4.7_1206_5%
2200P_0603_50V7K 2
1
PR220
4.7_1206_5%
34
35
1 2
1
2
0_0603_5%
PR219
BOOT0
36
0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1
ISP 1
PC234
4.7U_0805_25V6-K
2
1
PC239
330P_0402_50V7K
2
1
5
6
7
8
1
2
2.2_0603_5% 0.22U_0603_10V7K
PR214
PC217
1
2 1
2
1
PR241
@0_0402_5%
PQ203
IRF8714TRPBF_SO8
<BOM
Structure>
PC242
2 @1000P_0402_50V7K
PC262
1
BOOT_NB1 2
2
BOOT_NB
UGATE NB
PHASE NB
38
37
UGATE_NB
PHASE_NB
ISP1
ISN1
24
23
VW1
COMP1
BOOT1
22
21
FB1
20
18
VSEN1
+1.8V
PC210
2.2U_0603_6.3V6K
PR236
@6.81K_0402_1%
2
PC241
2 1000P_0402_50V7K
2
<6> CPU_VDD0_FB_L
1
PR237
0_0402_5%
+5VS
PR207
17.4K_0402_1%
39
LGATE NB
PGND_NB
LGATE_NB
OCSET_NB
RTN_NB
VSEN_NB
FSET_NB
17
1
2
PC228
1000P_0402_50V7K
PHASE NB
LGATE NB
1
PR209
0_0402_5%
1
2
PC243
1000P_0402_50V7K
43
44
45
46
16
6.81K_0402_1%
1
PR235
0_0402_5%
COMP_NB
VCC
PR232
1
FB_NB
UGATE1
VW0
RTN1
54.9K_0402_1%
<6> CPU_VDD0_FB_H
47
COMP0
PC225
1
2
1200P_0402_50V7K
1
2
PC227
180P_0402_50V8J
PHASE1
RTN0
ISL6265IRZ-T_QFN48_6X6
FB0
15
PR230
1
PGND1
ISP0
1K_0402_1%
VDIFF0
VDIFF1
12
LGATE1
VSEN1
PVCC
OCSET
VSEN0
RBIAS
14
11
LGATE0
19
4700P_0402_25V7K
PR227
PGND0
ENABLE
RTN1
10
255_0402_1%
PHASE0
13
UGATE0
SVD
VSEN0
PC223
1
2
BOOT_NB
PWROK
SVC
PL202
SMB3025500YA_2P
BOOT0
ISN0
PGOOD
1
@1000P_0402_50V7K
PC244
2
1
@1000P_0402_50V7K
PC245
2
1
@1000P_0402_50V7K
PC246
1
@1000P_0402_50V7K
PC247
10K_0402_1%
OFS/VFIXEN
ISP 0
VR_ON
107K_0402_1%
VIN
1
+CPU_CORE_0
<6> CPU_SVC
48
PR216
10K_0402_1%
2
1
CPU_SVD
PR225
PU201
2
PR246 1100K_0402_5%
2
ISL6265_PWROK 3
1
2
PR234 @100K_0402_5%
SVD
PR218 1
2
4
0_0402_5%
SVC
PR222 1
2
5
0_0402_5%
6
PR223
PR224
1
2
1
2
7
<33>
VGATE
<19> H_PWRGD
<6,20,33> SB_PWRGD
<33>
PR215
@10K_0402_5%
B+
CPU_B+
PR211
1_0603_5%
40
2
PR212
0_0402_5%
1
2
PR213
@0_0402_5%
1
2
PC206
0.1U_0402_16V7K
VSEN_NB
RTN0
+5VS
+3VS
41
PC216
0.1U_0603_25V7K
RTN_NB
CPU_B+
42
PR208
2_0402_5%
1
2
2
1
2
1
PR210
PC208
44.2K_0402_1% 1200P_0402_50V7K
PC207
0.1U_0402_16V7K
PQ209
@SSM3K7002FU_SC70-3
<6>
PR206
0_0402_5%
2
1
PR205
2_0402_5%
1
2
+5VS
33P_0402_50V8K
PC209
2
1
PC205
1000P_0402_50V7K
2
G
VFIX_EN
PR203
0_0402_5%
PC204
ISL6265_PWROK
<33>
4
680P_0603_50V7K
CPU_B+
PC251
1
2
3
PQ202
AO4466_SO8
PQ201
AO4468_SO8
8
7
6
5
1
2
3
PR204
22K_0402_1%
1
2
PC203
2200P_0402_50V7K
PC202
220U_B2_2.5VM
1
2
<6> VDD_NB_FB_L
10U_0805_6.3V6M
PC201
<6> VDD_NB_FB_H
2
1
4.7UH_PCMC063T-4R7MN_5.5A_20%
PC238
470P_0402_50V7K
PL201
+CPU_CORE_NB
PR245
4.7_1206_5%
1 2
1
ISP 1
1
PR238
@54.9K_0402_1%
2
1
PC232
@1200P_0402_50V7K
PR240
@1K_0402_1%
2
1
PR243
@255_0402_1%
2
1
@4700P_0402_25V7K
PC233
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
R ev
0.1
Sheet
43
of
56
T it le
D a t e R e q u e st
O w n er
I s s u e D e sc rip tio n
R ev.
37
DC Connector
/CPU_OTP
9/29
Compal
for Layout
41
1.1VSP/1.2VALWP
9/29
Compal
HW request
41
1.1VSP/1.2VALWP
9/29
Compal
HW request
Add PJP503
43
CPU_CORE
9/29
Compal
HW request
43
CPU_CORE
9/29
Compal
43
CPU_CORE
9/29
Compal
Add PJP201
38
Charger
9/29
Compal
37
10/08
Compal
for Layout
38
Charger
10/08
Compal
10
40
1.8VP
10/08
Compal
PWR request
11
41
1.1VSP/1.2VALWP 10/08
Compal
PWR request
Add PR517
DC Connector
/CPU_OTP
12
37
13
37
14
43
15
37
16
37
17
43
DC Connector
/CPU_OTP
PC12
PWR request
Add PD4
11/01
Compal
for Layout
11/02
Compal
EMI request
3.3VALWP/5VALWP
11/12
Compal
for Layout
3.3VALWP/5VALWP
12/31
Compal
PWR request
12/31
Compal
Vendor request
CPU_CORE
PR518
Compal
CPU_CORE
PJP202
11/01
3.3VALWP/5VALWP
2007/08/02
Issued Date
PR221
PR217
PR223
PR224
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
Security Classification
Title
R ev
1.C
Sheet
E
44
of
56
T it le
D a t e R e q u e st
O w n er
I s s u e D e sc rip tio n
R ev.
18
19
38
37
Charger
DC Connector
/CPU_OTP
Compal
EMI request
01/09
Compal
01/14
Compal
for layout
20
37
21
38
Charger
02/27
Compal
EMI request
22
43
CPU_CORE
02/27
Compal
EMI request
23
37
02/27
Compal
EMI request
24
37
02/27
Compal
25
37
3.3VALWP/5VALWP
01/08
3.3VALWP/5VALWP
DC Connector
/CPU_OTP
3.3VALWP/5VALWP
EMI request
02/27 Compal
26
43
CPU_CORE
03/04
Compal
27
43
CPU_CORE
03/04
Compal
HW request
28
37
DC Connector
/CPU_OTP
04/02
Compal
AC LED issue
29
43
CPU_CORE
04/24
Compal
acoustic noise
Add PC262
30
37
DC Connector
/CPU_OTP
04/24
Compal
+1.2VALW leakage
Add PR519
31
37
1.1VSP/1.2VALWP 05/23
Compal
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
1.C
Sheet
E
45
of
56
25
D ate
T it le
LAN
1 0 /2 9
1 0 /2 9
1 0 /2 9
25
16
LAN
CRT
4
5
29
4
A u d io
FAN
29
R e q u e st
I s s u e D e sc rip tio n
O w n er
HW
C h a n g e L A N C h ip U 2 0 fro m M a rv e ll 8 8 E 8 0 4 2 to
R e a lt e k R T L 8 1 0 2 E L
HPQ
A d d P O E (P o w e r O v e r E th e rn e t) d e sig n
HW
C R T c a n n o t d isp la y
1 0 /3 0
1 1 /0 1
HW
HW
S p e a k e r n o so u n d
F A N C o n n . n o t c o rre c t p a rt
S p ea k er
1 1 /0 1
HW
S p e a k e r C o n n . n o t c o rre c t p a rt
34
MDC
1 1 /0 1
HW
M D C C o n n . n o t c o rre c t p a rt
8
9
11,35
11,21
TV_OUT
1 1 /0 5
N B /S B T h e rm a l 1 1 /0 5
HW
HW
T V -O U T F u n c tio n n o su p p o rt
N B T h e r m a l F u n c tio n n o su p p o rt (lo c a te to o fa r)
10
21,31
SB SATA
1 1 /0 5
HW
11
21
SB SATA
1 1 /0 5
HW
S B S A T A P o rt 5 c h a n g e to P o rt 2 fo r A T I C o m m o n
D e s ig n
S B S A T A _ A C T # P u ll H ig h b e c o m e + 3 V S
12
21
S B G PIO
1 1 /0 5
HW
C h a n g e S B G P I O re fe r to J B K 0 0 fo r c o m m o n
13
14
15
16
17
31
29
25
21,24
36
SB SATA
1 1 /0 5
A u d io H P O U T 1 1 /0 5
L A N T ra n sferm o r 1 1 /0 5
SB SATA
1 1 /0 6
D IM LE D
1 1 /0 6
HW
HW
HW
HW
HW
18
27
C a r d R ea d er
HW
C h a n g e C a rd R e a d e r S o c k e t fo r M / E n e w p a rt a n d
C h ip f o r J M ic ro n n e w v e rsio n
1 1 /0 6
R ev.
U p d a te th e L A N D esig n p a g e a n d su p p o rt circu it
0 .2
0 .2
2007/08/02
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
1 . C o n n e c t U 1 5 .C 6 t o G N D b y 0 _ 0 4 0 2 .
2 . C h a n g e W L O F F # f ro m G P I O 5 0 t o G P I O 6 1 .
3 . C h a n g e B T _ C O M B O _ E N # f ro m G P I O 5 1 to G P IO 6 2 .
4 . C h a n g e W W O F F # f ro m G P I O 5 2 t o G P I O 6 3 .
V e rt ic a l L 5 1 1 < --> 4 , 2 < --> 3 f o r la y o u t ro u tin g
0 .2
2008/08/02
Deciphered Date
Title
0 .2
C h a n g e R 3 4 3 .1 p o w e r ra il f ro m + 5 V S t o + 3 V S . In sta ll R 3 4 3 .
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
0 .2
C h a n g e J P 2 P C B F o o t p rin t f ro m A C E S _ 8 5 2 0 4 -0 2 0 0 1 _ 2 P to
A C E S _ 8 8 2 3 1 -0 2 0 0 1 _ 2 P
C h a n g e J P 2 0 P C B F o o t p rin t f ro m A C E S _ 8 5 2 0 4 -0 4 0 0 1 _ 4 P to
A C E S _ 8 8 2 3 1 -0 4 0 0 1 _ 4 P
C h a n g e J P 2 0 P C B F o o t p rin t f ro m A C E S _ 8 8 0 1 8 -1 2 4 G _ 1 2 P to
A C E S _ 8 8 0 2 0 -1 2 1 0 1 _ 1 2 P
D e l R 5 9 ,R 6 0 ,R 6 1 ,R 1 1 5 ,R 1 1 6 ,R 1 1 7 a n d T V -O U T re la t e d d e s ig n .
C a n c e l N B _ T H E R M A L _ D A / D C c o n n e c t io n b e tw een N B a n d
S B ,d e l C 5 0 0
C h a n g e S B S A T A p o rt 5 to p o rt 2
Security Classification
Issued Date
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
R ev
1.C
Sheet
E
46
of
56
D ate
R e q u e st
O w n er
HW
HW
C IC
HW
HW
N o r m a li z e C R T d e sig n fo r c o m m o n
N o r m a liz e L C D d e sig n fo r c o m m o n
C I C fe e d b a c k R M A c o n c e rn fo r com m on
N o r m a liz e K B 9 2 6 C ry sta l p a rt fo r c o m m o n
C h a n g e U 5 4 W e b C a m p o w e r d e sig n a n d re la te d
I s s u e D e sc rip tio n
19
20
21
22
23
16
17
18
33
17
T it le
CRT
LCD
LCD
KBC
W eb C a m
24
25
18
19,32
HDMI
1 1 /0 9
S B -C L K -D eb u g 1 1 /0 9
HW
HW
R e d u c e H D M I D e sig n
D e b u g C a rd n o fu n c tio n issu e
26
27
28
29
30
31
25
18
6
33
35
26
LAN
HDMI
CPU
KBC
H o les
M in i -C a rd
1 1 /0 9
1 1 /0 9
1 1 /0 9
1 1 /0 9
1 1 /0 9
1 1 /0 9
HW
HW
HW
HW
ME
HW
R J 4 5 L E D P o w e r c o rre c t b a c k
R e d u c e H D M I D e sig n
A d d H _ T H E R M T R I P # o n e m o re w a y
U p d a t e K B C P in D e fin itio n fo r c o m m o n
U p d a t e f o r M / E D ra w in g
R e d u c e M in i-C a rd d e sig n , c h a n g e S I M C a rd d e sign
32
33
33
27
KBC
C a r d R ea d er
1 1 /0 9
1 1 /1 0
HW
HW
R e s e r v e 0 _ 0 6 0 3 fo r K B B a c k L ig h t
C o rre c t C a rd R e a d e r L E D p a rt
34
34
L E D F u n ctio n
1 1 /1 0
HW
C o r r e c t L E D fu n c tio n fo r c o m m o n
1 1 /0 7
1 1 /0 7
1 1 /0 7
1 1 /0 7
1 1 /0 9
C h a n g e L 8 3 ,L 8 4 (1 0 _ 0 4 0 2 ) b e c o m e R 2 4 1 ,R 2 4 0 (0 _ 0 6 0 3 )
C h a n g e R 4 9 1 fro m 2 0 0 _ 0 4 0 2 to 2 0 0 _ 0 8 0 5
C h a n g e Q 4 3 fro m A O S 3 4 1 3 to S I 2 3 0 1
C h a n g e Y 7 f ro m 9 H 0 3 2 0 0 4 1 3 s m a ll t o 1 T J S 1 2 5 D J 4 A 4 2 0 P n o rm a l.
C h a n g e U 5 4 f ro m G 9 1 6 -3 9 0 T 1 U F t o R T 9 1 9 3 -3 9 G B .
R e m o v e R 8 9 1 ,R 8 9 2 if n o u s e G 9 1 6 -3 9 0 T 1 U F .
A d d C 7 1 8 c lo s e t o U 5 4 .4 f o r R T 9 1 9 3 -3 9 G B .
R e m o v e R 1 0 2 7 ~ R 1 0 3 0 f o r J P 7 n o in s ta ll.
C h a n g e J P 7 f ro m 8 p in to 6 p in
C h a n g e J R J 4 5 .1 3 , J R J 4 5 .1 1 f ro m + 3 V _ L A N _ L E D to + 3 V _ L A N
S B -G P I O
K B C-G PIO
1 1 /1 0
1 1 /1 1
HW
HW
37
6,31
C P U ,F P R
1 1 /1 3
HW
A d d o n e m o re w a y fo r G S E N S O R L E D # in fo rm p in
A d d C I R _ I N P H to + 5 V L
A d d E S B _ C L K / D A T P H to + 3 V L
R e d u c e S 3 p o w e r c o n su m p tio n
38
11
NB
1 1 /1 3
HW
R e d u c e th e le v e l sh ift d e sig n fo r C h ip A 1 2 .
39
40
17
6,33
W eb C a m
C P U ,K B C
1 1 /1 3
1 1 /1 3
HW
HW
U p d a te th e W e b C a m + D ig ita l M ic re se rv e r con n .
U p d a te T H E R M T R I P # d e sig n to E C
41
18
1 1 /1 3
HW
R e m o v e E M I so lu tio n b e c o m e re se rv e fo r v e rify
R e m o v e R 4 9 0 (1 0 0 K _ 0 4 0 2 )
A d d R 1 6 clo se to Q 3 .1 fo r H _ T H E R M T R I P #
A d d H _ T H E R M T R I P # to U 3 3 .2 5
D el H 4 9 H 5 0 H 3 8 H 4 5 fo r M /E d ra w in g ch a n ge
R ep lace D 1 7 an d D 47 becom e R 52 and R 53
D e l R 4 0 0 a n d R 4 6 , C h a n g e J P 6 p in d e f in it io n f o r c o m m o n
A d d R 5 1 6 (0 _ 0 6 0 3 ) b e t w e e n J P 4 8 .1 / 4 a n d + 5 V S _ L E D
2007/08/02
Issued Date
C h a n g e R 1 5 .2 ,R 2 1 .2 ,R 3 6 .2 ,R 3 0 .2 c o n n ectio n fro m
+ 1 .8 V t o + 1 .8 V S ; R e m o v e R 6 2 2 , in s ta ll R 5 8 1
0 .2
D e l Q 6 ,R 8 7 ; Q 5 ,R 8 4 a n d re p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 )
c o n n e c t d ire c t ly . I n s t a ll R 3 7 1 (1 0 K o h m )
0 .2
C h a n g e J P 7 f ro m S P 0 2 0 0 0 H C 0 0 (8 p in )--> S P 0 2 0 0 0 I L 0 0 (6 p in )
0 .2
0 .2
C h a n g e R 1 6 .2 c o n n e c t io n f ro m T H E R M T R I P # t o
T H E R M T R I P # _ E C f o r s e p a ra t e
A d d R 1 1 2 ,R 1 1 3 ,R 1 1 5 ~ R 1 2 0 c lo s e t o e a c h L 8 5 ~ L 8 8 f o r c o -la y
2008/08/02
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
0 .2
0 .2
0 .2
Deciphered Date
Title
0 .2
0 .2
A d d H D D _ H A L T L E D # c o n n e c t f ro m U 1 5 .P 8
A d d R 4 6 1 0 K _ 0 4 0 2 P H t o + 5 V L c lo s e t o U 3 3
A d d R 5 1 4 ,R 5 1 5 1 0 K _ 0 4 0 2 P H t o + 3 V L c lo s e t o U 3 3
Security Classification
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
C h a n g e D 5 f ro m S C 5 0 0 0 0 4 E 0 0 (A Q U A _ W H IT E ) to
S C 5 0 0 0 0 4 W 0 0 (W H I T E )
C h a n g e L E D f ro m D 5 0 ,D 3 0 ,D 2 7 S C 5 0 0 0 0 4 E 0 0
(A Q U A _ W H I T E ) t o D 6 ,D 7 ,D 8 S C 5 0 0 0 0 4 W 0 0 (W H I T E )
C h a n g e L E D f ro m D 4 5 ,D 4 6 S C 5 0 0 0 0 4 B 0 0
(A Q U A _ W H I T E / A M B E R ) t o D 1 7 ,D 1 8 S C 5 0 0 0 0 5 M 0 0
(Y E L L O W / W H I T E ); A d d Q 7 ,R 2 0 a n d R 4 2 c lo s e t o D 1 8
21
33
0 .2
0 .2
R e m o v e R 4 9 0 (1 0 0 K _ 0 4 0 2 )
35
36
0 .2
0 .2
0 .2
0 .2
0 .2
D e l R 1 0 3 1 ,a d d R 3 0 3 c lo s e t o R 3 0 1 a n d U 1 5 .P 2
C o n n e c t f o r C L K _ P C I _ S I O 2 t o J P 4 1 .1 5
HDMI
R ev.
0 .2
R ev
1.C
Sheet
E
47
of
56
1 1 /1 3
R e q u e st
I s s u e D e sc rip tio n
O w n er
HW
R e d u c e S B re la te d d e sig n fo r C h ip A 1 2 a n d o th e rs
43
21,32
S B ,B IO S
1 1 /1 3
HW
B I O S D e b u g T o o l re se r v e
44
45
46
47
25
13
18
20
LAN
NB
HDMI
SB
1 1 /1 3
1 1 /1 3
1 1 /1 3
1 1 /1 3
HW
HW
HW
HW
U p d a t e L A N C h ip S y m b o l lin k to C I S se rv e r
A d d 0 o h m _ 0 6 0 3 t o se p a ra te V D D 1 8 _ M E M
R e d u c e H D M I re la te d d e sig n fo r c o m m o n
R e d u c e S B re la te d d e sig n fo r c o m m o n a n d A 1 2 c h ip
48
S B ,C a rd rea d er
1 1 /1 3
HW
49
50
51
2 0 ,2 1 ,
27
21,33
28,33
33
S B ,K B C
C o d ec,K B C
KBC
1 1 /1 3
1 1 /1 3
1 1 /1 3
HW
HPQ
HW
R e se rv e C a rd re a d e r D 3 E fu n c tio n (C R _ W A K E # &
CR_CPPE# )
R e d u c e S B re la te d d e sig n fo r c o m m o n
E C _ B E E P fu n c tio n fo r K B C a d d
R e d u c e S 5 P o w e r C o n su m p tio n
52
33
KBC
1 1 /1 3
HW
R e d u c e K B C D e sig n fo r c o m m o n a n d V e r:C 0 C h ip
C hange from SA 00001J530 to SA 00001J540
53
34
S w i tch D esig n
1 1 /1 3
HW
U p d a t e C S D f u n c tio n b o a rd d e sig n fo r c o m m o n
54
34
LED
1 1 /1 4
HW
Item P a ge#
1
D ate
55
56
57
29
29
4,24
A u d io -D o ck
H o les
M u lti-B a y
1 1 /1 4
1 1 /1 4
1 1 /1 4
HPQ
ME
ME
C o rre c t T / P O n / O ff L E D d e sig n d e f in e
C o r r e c t G -S e n so r L E D d e sig n d e fin e
F o r G S m a rk re q u ire m e n t
U p d a t e H o le s to m e e t M / E D ra w in g
U p d a t e S y m b o l to m e e t M / E D ra w in g
58
59
60
61
62
63
33
20
33
35
33
28,29
H o les
SB
KBC
DOCK
K /B
A U D IO
1 1 /1 4
1 1 /1 6
1 1 /1 6
1 1 /1 6
1 1 /1 6
1 1 /1 8
ME
A TI
EC
EMC
HW
HPQ
U p d a t e H o le s to m e e t M / E D ra w in g
R e se rv e to fix th e O T S 3 2 5 0 5 5 I ssu e
C h a n g e d e sig n fo r E C te a m d e b u g
C o n n e c t D O C K g u id e p in to G N D
F ix K B m a tri x issu e
M a k e s o m e A u d io re la te d d e sig n c h a n g e
29
A U D IO
1 1 /1 9
HPQ
0 .2
0 .2
0 .2
0 .2
A d d R 5 6 3 c lo s e t o C 9 5 5 ; A d d R 5 4 4 c lo s e t o U 3 3 .3 1
C h a n g e R 1 0 4 0 .1 c o n n e c t io n f ro m + 3 V L _ E C to + 3 V A L W
D e l R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 re p la c e b y a d d R 5 4 7 c lo s e to
U 3 3 f o r s h o rt
D e l R 5 3 7 b e c o m e T e s t P o in t , c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6 0 3
R e m o v e R 1 0 4 4 , c h a n g e R 1 0 4 0 f ro m 1 0 K t o 1 0 0 K
C h a n g e R 5 2 8 .2 , R 5 2 9 .2 c o n n e c t io n f ro m + 5 V A L W to + 5 V L
I n s t a ll C 8 1 4 (4 .7 U _ 0 8 0 5 )
C h a n g e J P 3 6 .1 c o n n e c t io n b e c o m e + 3 V L ;C h a n g e R 1 0 4 6 .1
a n d R 1 0 4 7 .1 c o n n e c t io n b e c o m e S M B _ E C _ C K 1 /D A 1
C h a n g e J P 3 6 .7 c o n n e c t io n f ro m G N D to + 5 V A L W _ L E D b y
C h a n g e Q 1 5 3 f ro m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2
C h a n g e R 9 8 8 .1 c o n n e c t io n f ro m + 5 V S _ L E D to + 3 V S
A d d R 9 6 8 ,R 9 6 9 c lo s e t o C 7 7 5 / C 7 7 6 .
2008/08/02
Deciphered Date
Title
0 .2
0 .2
0 .2
0 .2
0 .2
3
0 .2
0 .2
0 .2
C h a n g e R 9 6 8 ,R 9 6 9 f ro m 4 0 .2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3
Compal Secret Data
0 .2
0 .2
C h a n g e C 9 8 3 ,C 9 8 4 f r o m 1 U F t o 0 .0 2 2 U F . C h a n g e C 1 0 4 9 ,C 1 0 5 0 ,C 1 0 4 0 ,C 1 0 4 1
f r o m 0 .4 7 U F t o 0 .0 2 2 U F . C h a n g e R 1 0 0 2 ,R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n g e
C 1 0 4 4 f r o m 1 0 U F t o 4 .7 U F . R e m o v e R 1 0 0 0 ,R 1 0 0 4 ; I n sta ll R 1 0 0 1 ,R 1 0 0 3 .
2007/08/02
0 .2
A d d R 8 1 c lo s e t o U 1 5 ;Q 5 4 ,R 1 2 4 c lo s e t o U 2 3 f o r c o n n e c t U 1 5 .F 8
t o U 2 3 .1 3 ;A d d R 3 6 9 c lo s e t o U 2 3 f o r c o n n e c t U 1 5 .M 5 t o U 2 3 . 1 6
D e l D 5 1 a n d R 1 0 3 4 , C h a n g e t h e n e t A C _ I N b eco m e A C _ IN _ D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
D e l K S I 6 a n d K S O 9 o u t o f p a g e n et co n n ect
Security Classification
0 .2
R e s e rv e R 8 3 P H t o + 3 V S
C h a n g e J P 3 4 .1 f ro m + 5 V A L W to + 5 V L
A d d J D O C K .4 5 / 4 6 to G N D
M a k e s o m e A u d io re la te d d e sig n c h a n g e
Issued Date
D e l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 c lo s e t o U 1 5 .
D el R 1 0 1 1 becom e T 18, C ancel R 1012 and connect to H 31
a n d J P 4 1 d ire c t ly
A d d S B _ I N T _ F L A S H _ S E L a n d re la t e d
(J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 ,C 4 8 9 c lo s e t o U 2 9 )
U p d a t e L A N C h ip U 2 0 S y m b o l lin k t o C I S s e rv e r
A d d R 1 0 5 1 (0 _ 0 6 0 3 ) b e t w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S P
D e l R 4 9 0 (1 0 0 K _ 0 4 0 2 )
R e m o v e R 9 9 4 (0 _ 0 4 0 2 )
C h a n g e U 1 5 .F 1 c o n n e c t io n b e c o m e t e s t p o in t
R em ov e R 1 0 5 3 , change R 1052 becom e 0_0402
A d d back H 52 becom e H _ 1P 5N ; D el C F 4
U p d a t e J P 2 ,J P 9 ,J P 1 0 ,J P 1 1 ,J P 2 0 ,J P 4 0 ,J H D M I ,J E S A T ,J C R T ,
JD O C K Sym bol
A d d back H 52 becom e H _ 1P 5N ; D el C F 4
64
R ev.
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
4
0 .2
Compal Electronics, Inc.
HW Changed-List History-2
R ev
1.C
Sheet
E
48
of
56
T it le
13
NB
22
SB
22
SB
3 3 , 3 4 F u n ctio n B o a rd
69
70
71
72
73
74
75
76
77
23
31
34
33
6
19
26
28
10~13
65
1
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SB
B lu eT o o th
P o w er O n S w i tch
KBC
CPU
SB
E x p ress C a rd
A u d io C o d ec
N B,
19
SB
22
SB
28
C o d ec
34
T/P
14
HDMI
15
C L K G en .
28
C o d ec
2 0 , 2 7 S B ,C a rd R ea d er
32
B IO S
34
LED
19
SB
0 6 ,1 9 ,
SB
23
33
KBC
32
B IO S
34
LED
D ate
1 1 /2 0
1 1 /2 0
1 1 /2 0
1 1 /2 0
1 1 /2 0
1 1 /2 0
1 1 /2 2
1 1 /2 2
1 1 /2 2
1 1 /2 2
1 1 /2 2
1 1 /2 2
1 1 /2 3
1 1 /2 3
1 1 /2 6
1 1 /2 6
1 1 /2 8
1 1 /2 8
1 1 /2 8
1 1 /2 8
1 1 /2 8
1 1 /2 8
1 1 /2 8
1 1 /3 0
1 1 /3 0
1 1 /3 0
1 2 /0 3
1 2 /0 3
R e q u e st
I s s u e D e sc rip tio n
O w n er
A TI
D e s ig n C h a n g e fo r N B A 1 2 V e rsio n c h ip
R ev.
0 .2
I n s t a l l R 5 9 3 , re m o v e R 5 9 2
R e m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 ,C 5 4 7 ,C 5 3 6
0 .2
0 .2
0 .2
A TI
HW
HW
D e s ig n C h a n g e fo r S B A 1 2 V e rsio n c h ip
R e d u c e S B P o w e r D e sig n -N o I D E su p p o rt
R e se rv e fo r R a c h m a n U M A se le c tiv e
HW
HW
HW
HW
HW
HW
HW
HW
HW
M a k e th e S B S tra p S e e tin g fo r c o m m o n
U p d a t e B T d e sig n fo r c o m m o n
C a n c e l o n e re se rv e d p o w e r o n sw itc h
M o d if y S M B _ E C _ D A 1 / C K 1 P H fo r c o m m o n
L in k P R O C H O T # b e tw e e n C P U a n d N B
R e se rv e L P C C L K 1 fo r d e b u g c a rd fu n c tio n
T o a v o id N e w C a rd S w itc h le a k a g e issu e
R e s e r v e S P D I F O U T 1 te st p o in t fo r v e rify
B O M c o rre c t fo r S I -1 S M T b u ild
HW
HW
HW
HW
A TI
HW
HW
HW
HW
HW
HW
A TI
C h a n g e C ry sta l R e s. siz e fo r la y o u t sp a c e
R e d u c e S B S A T A P o w e r C a p s (C o n firm w ith A T I F A E )
S P D I F 0 --> 1 d e sig n c h a n g e to fo llo w V a d e r
C h a n g e T / P P o w e r fo r re d u c e S 4 / S 5 p o w e r c o n su m p tio n
F i x H D M I n o fu n c tio n issu e
C h a n g e d e sig n fo r n e w v e rsio n C L K G e n .
C h a n g e E C _ B E E P fu n c tio n b e c o m e re serv e
D is c o n n e c t D 3 E s u p p o rt fo r A v e rsio n to a v o id risk
U se E x t. B I O S a s d efa u lt
C a n c e l W L A N / W W A N e x t p u ll h ig h
F ix P A M / E I n te rfe re issu e fo r S I-1
A T I re c o m m e n d fo r u p d a te
HW
HW
HW
C h a n g e 3 2 .7 6 8 K H z M a in S o u rc e V e n d o r b e c o m e E P S O N C h a n g e Y 7 f ro m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0
C a n c e l E x t. B I O S re fla sh d e sig n b e c a u se of + 3 V L erroe A d d R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 ,R 2 2 8 ,C 4 8 9
R em ove Q 156
C a n c e l G -S e n so r I N T 2 L E D fu n c tio n
R e s e r v e R 5 5 5 f o r + 5 V A L W _ L E D , a d d R 5 5 4 f o r + 3 V L c lo s e t o J P 3 6 .1
R e s e r v e R 1 0 3 4 c l o s e t o J P 3 6 .4 ,R 1 0 3 5 c lo s e J P 3 6 .5 ,R e m o v e R 1 0 3 6
A d d R 5 1 3 P H t o + 3 V S c lo s e t o U 3 3 .1 9
I n s t a ll R 3 5 6 (1 0 K _ 0 4 0 2 )
C h a n g e R 5 2 0 f ro m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0 4 0 2
D el S W 3
C h a n g e R 5 2 8 ,R 5 2 9 p in 2 c o n n e c t io n f ro m + 5 V L t o + 3 V L
A d d R 5 9 c lo s e t o Q 2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
A d d R 3 0 8 2 2 _ 0 4 0 2 f o r U 1 5 .E 2 2 c lo s e t o R 3 6 2 .1 , re m o v e R 3 0 1
A d d R 5 4 (0 _ 0 4 0 2 ) c lo s e t o U 2 1 .6
A d d T 2 1 c lo s e t o U 2 7 . 4 5
U p d a t e U 3 ( S A 0 0 0 0 1 Z G 0 0 - - > S A 0 0 0 0 1 Z G 2 0 );U 1 0 ( S A 0 0 0 0 1 Z 3 0 0 -->
S A 0 0 0 0 1 Z 3 1 0 );U 1 5 ( S A 0 0 0 0 1 S 5 1 0 - - > S A 0 0 0 0 1 S 5 6 0 )
C h a n g e R 3 8 9 f ro m 0 6 0 3 t o 0 4 0 2
C h a n g e C 5 6 7 ,C 5 6 8 f ro m 1 0 U _ 0 8 0 5 t o 1 U _ 0 8 0 5
C h a n g e U 2 7 .4 8 / 4 5 p in c o n n e c t io n
R em ove R 235; A dd Q 85, R 645, Q 34
R em ove R 102; A dd R 101
R em ove R 1045
R em ove R 563
R e m o v e R 8 1 ,R 3 6 9
R em ove R 221
R em ove R 1041
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
c h a n g e Y 3 f ro m S J 1 0 0 0 0 1 U 0 0 t o S J 1 0 0 0 0 6 6 0 0 w it h 1 0 P P M
C h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a n g e R 3 5 6 fro m 1 0 K _ 0 4 0 2
t o 2 .2 K _ 0 4 0 2 ; I n s t a ll C 2 3 a s 0 .1 U F _ 0 4 0 2
0 .2
0 .2
0 .2
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
1.C
Sheet
E
49
of
56
01
02
03
04
05
06
07
08
09
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
36
19
19
23
29
23
31
32
32
33
34
35
35
34
34
34
33
14
17
22
25
31
19
19
20
21
25
26
33
35
36
34
33
34
34
06
T it le
SB
SB
SB
Amplifier
Speaker
Finger Printer
BIOS ROM
BIOS ROM
EC
T/P ON/OFF LED
Docking
MDC
Switch board
Switch board
Switch board
EC
SB
Webcam and Digital MIC
SB
LAN
USB port
SB
SB
SB
SB
LAN
WWAN
EC
M/B
DC-DC
Switch board
Keyboard connector
Lid switch connector
Switch board
HDT debug port
D ate
12/26
12/26
12/26
12/26
12/26
12/26
12/26
12/26
12/26
12/26
12/26
12/26
01/03
01/03
01/03
01/07
01/08
01/08
01/08
01/08
01/08
01/09
01/09
01/09
01/09
01/09
01/09
01/09
01/09
01/09
01/10
01/10
01/10
01/10
01/14
R e q u e st
O w n er
HW
HW
HW
HW
HW
HW
HW
HW
HW
EC
HW
ME
HW
HW
HW
Power
HW
HW
I s s u e D e sc rip tio n
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
Common design.
Useless
Useless
R1036
HW
Realtek
Layout
EMI
EMI
EMI
DFB
DFB
EMI
HW
ME
HW
HW
DFB
DFB
EMI
AMD
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
R ev.
Title
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
Compal Electronics, Inc.
HW Changed-List History-2
Size Document Number
Custom
LA-4117P
Date:
R ev
1.C
Sheet
E
50
of
56
37
38
39
40
41
42
25
33
11
17
15
15
T it le
LAN
EC
NB
LVDS
Clock GEN.
Clock GEN.
D ate
01/14
01/14
01/15
01/15
01/15
01/15
R e q u e st
O w n er
HW
HW
HW
HW
HW
Vendor
I s s u e D e sc rip tio n
R ev.
Reserve R544
0.3
0.3
0.3
0.3
0.3
0.3
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
R ev
1.C
Sheet
E
51
of
56
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
25
34
06
06
06
06
07
12
12
13
13
24
27
27
31
31
33
33
34
34
11
11
19
21
32
34
33
35
34
34
34
11
16
16
34
T it le
LAN
S/W board connector
CPU
CPU
CPU
CPU
CPU
NB
NB
NB
NB
Multibay connector
Card Reader
Card Reader
BT
BT
EC
EC
Debug SW
TP LED
NB
NB
SB
SB
SPI BIOS
WL/BT LED control
EC
Screw hole
D ate
02/12
02/12
02/12
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/15
02/18
02/18
02/18
02/18
02/18
02/18
02/18
02/19
02/19
02/19
02/22
NB
02/22
CRT connector
02/22
CRT connector
02/22
02/22
R e q u e st
O w n er
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
ME
HW
HW
ME
HW
HW
HW
HW
ME
HW
HW
HW
HW
HW
HW
HW
ME
ENE
ENE
HW
HW
HW
HW
HW
I s s u e D e sc rip tio n
For ESD protect.
Reserve D55.
Reserve R558.
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Reserve R59.
Follow Trinity design.
Add H57.
Add C1098.
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
R ev.
Title
R ev
1.C
Sheet
E
52
of
56
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
67
67
25
35
34
34
33
33
36
31
15
16
17
32
17
34
06
34
11
31
22
13
35
11
11
33
06
19
20
21
21
31
17
15
20
15
15
T it le
LAN
Screw hole
D ate
02/22
02/22
02/22
02/22
EC
02/22
EC
02/22
DC/DC
02/25
USB connector
02/25
Clock GEN.
02/25
CRT Connector
02/25
LCD Connector
02/25
Debug connector
02/26
WEBcam LDO
02/26
02/26
CPU
S/W board connector
NB
USB connector
02/27
03/03
03/03
03/03
SB
03/03
NB
03/03
Docking connector
03/03
NB
03/03
NB
03/03
EC
03/03
CPU
03/04
SB
03/04
SB
03/05
SB
03/06
SB
03/06
eSATA connector
03/06
LCDVCC circuit
03/06
Clock GEN.
SB
WWAN connector
WWAN/WLAN
03/06
03/06
03/06
03/06
R e q u e st
O w n er
DFB
DFB
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
HW
HW
POWER
EMI
EMI
EMI
HW
HW
DFB
AMD
AMD
AMD
AMD
AMD
EMI
AMD
AMD
AMD
HW
HW
HW
HW
HW
I s s u e D e sc rip tio n
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Add C1110~C1117.
Add C1109.
Add C1106.
Add C1107.
Add C1108.
Add C1118.
Add SSC circuit (U66, R1080, R1081, R1082, R1083, C1122) for HDA_BITCLK.
Add C1123.
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
R ev.
Title
R ev
1.C
Sheet
E
53
of
56
68
69
70
71
72
73
T it le
20
11
25
33
18
18
D ate
SB
03/06
NB
03/06
LAN
03/06
LAN
03/06
HDMI
03/07
HDMI
03/07
R e q u e st
O w n er
HW
HW
HW
HW
HW
HW
I s s u e D e sc rip tio n
To solve can not power on if use CPU with single core
0.4
0.4
0.4
Stuff Q144, R1056, R1057, C1077 and reserve R1067.
0.4
Stuff R544.
Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
0.4
Reserve 0 ohm and stuff common choke.
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Compal Secret Data
Compal Electronics, Inc.
Stuff R83.
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
R ev.
Title
HW Changed-List History-2
Size Document Number
Custom
LA-4117P
Date:
R ev
1.C
Sheet
E
54
of
56
68
69
70
71
72
T it le
20
11
25
33
18
D ate
SB
03/06
NB
03/06
LAN
03/06
LAN
03/06
HDMI
03/07
R e q u e st
O w n er
HW
HW
HW
HW
HW
I s s u e D e sc rip tio n
To solve can not power on if use CPU with single core
0.4
0.4
0.4
Stuff Q144, R1056, R1057, C1077 and reserve R1067.
0.4
Stuff R544.
Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Compal Secret Data
Compal Electronics, Inc.
Stuff R83.
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
R ev.
Title
HW Changed-List History-2
Size Document Number
Custom
LA-4117P
Date:
R ev
1.C
Sheet
E
55
of
56
68
69
70
71
72
73
T it le
20
11
25
33
18
33
D ate
SB
03/06
NB
03/06
LAN
03/06
LAN
03/06
HDMI
03/07
EC
09/10
R e q u e st
O w n er
HW
HW
HW
HW
HW
HW
I s s u e D e sc rip tio n
R ev.
Stuff R83.
Stuff R544.
Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
0.4
0.4
0.4
0.4
0.4
1.0
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Compal Electronics, Inc.
HW Changed-List History-2
Size Document Number
Custom
LA-4117P
Date:
R ev
1.C
Sheet
E
56
of
56
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