UNIVERSIDAD PRIVADA DE TACNA

ESCUELA PROFESIONAL DE INGENERIA

ELECTRONICA

FACULTAD DE INGENERIA

PRE-INFORME SUMADOR COMPLETO 2 BITS

DOCENTE
ING. VILDOZO ZAMBRANO MARIA ELENA
ALUMNO
CANDIDO MOLANES MIOVICH
CURSO
CIRCUITOS DIGITALES II
TACNA - PERU
AO
2015

1. MEDIO SUMADOR
A
0
0
1
1

B
0
1
0
1

S
0
1
1
0

Co
0
0
0
1

Tabla 1 Tabla de verdad medio sumador

S = AB+AB
S= A XOR B

Co = AB

Fig. 1 Medio sumador

Fig. 2 Sumador complete de 1 bit

Fig. 3 Sumador complete de 2 bits

2. CODIGO
--Carry1
entity cout is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cout : out STD_LOGIC);
end cout;
architecture Behavioral of cout is
begin
cout <= a and b;
end Behavioral;
--Suma1
entity sum is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC);
end sum;
architecture Behavioral of sum is
begin
s <= a xor b;
end Behavioral;
-- Instanciamos 1 medio sumador llamando las funciones sum y cout
entity medio_sumador1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC;
S : out STD_LOGIC);
end medio_sumador1;
architecture Behavioral of medio_sumador1 is
component sum is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC);
end component;
component cout is
Port (a : in STD_LOGIC;
b : in STD_LOGIC;
cout : out STD_LOGIC);
end component;
begin

carry: cout port map (A,B,C);

suma: sum port map(A,B,S);
end Behavioral;
--Construimos una compuerta or
entity compuertaor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC);
end compuertaor;
architecture Behavioral of compuertaor is
begin
s <= a or b;
end Behavioral;
--Sumador completo de 1 bit
entity medio_sumador1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC;
S : out STD_LOGIC);
end medio_sumador1;
architecture Behavioral of medio_sumador1 is
component sum is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC);
end component;
component cout is
Port (a : in STD_LOGIC;
b : in STD_LOGIC;
cout : out STD_LOGIC);
end component;
begin
carry: cout port map (A,B,C);
suma: sum port map(A,B,S);
end Behavioral;

--Sumador completo de 2 bits

entity sumador_2bits is
Port ( A0 : in STD_LOGIC;
B0 : in STD_LOGIC;
Cin : in STD_LOGIC;
A1 : in STD_LOGIC;
B1 : in STD_LOGIC;
So : out STD_LOGIC;
S1 : out STD_LOGIC;
C1 : out STD_LOGIC);
end sumador_2bits;
architecture Behavioral of sumador_2bits is
component sumador_completo1bit is
Port ( Ao : in STD_LOGIC;
Bo : in STD_LOGIC;
Ci : in STD_LOGIC;
So : out STD_LOGIC;
Co : out STD_LOGIC);
end component;
signal x : STD_LOGIC;
begin
sumador1bit : sumador_completo1bit port map(A0,B0,Cin,So,x);
sumador2bit : sumador_completo1bit port map(A1,B1,x,S1,C1);
end Behavioral;

3. TA BLA DE OPRACION
A0
0
0
0
0
1
1
1

B0
1
0
0
1
0
0
1

Cin
0
0
1
0
1
0
1

A1
0
0
0
0
0
1
1

B1
0
1
1
0
1
1
1

So
1
0
1
0
0
1
1

S1
0
1
1
0
0
0
1

Tabla 2. Tabla de operacin final sumador completo 2 bits

C1
0
0
0
1
1
1
1

4. SIMUACION

Fig. 4 Simulacion sumador completo 2 bits