MOSFET

Lecture 7
MOSFET
Devices and Circuits
Gu-Yeon Wei
Division of Engineering and Applied Sciences
Harvard University
guyeon@eecs.harvard.edu
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Overview
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Reading
Chapter 6
Supplemental Reading
Sedra&Smith: Chapter 5.1~5.4
Background
Now that we have a basic understanding of semiconductors and PN
junctions, we will build on that knowledge to look at a transistor device
called a MOSFET. This is the first of two transistors types that we will be
studying in this course. Most modern ICs are built using these transistors.
While they are commonly used to implement digital circuits, we will look at
their analog characteristics and talk about how to build amplifiers with them.
We begin with the physical structure and a qualitative understanding of how
MOSFETs operate. We will derive some current-voltage equations for the
transistor. We will also use band diagrams to provide some theoretical rigor
to our initial qualitative understanding. Then, we will look at some non-ideal
characteristics of the transistor. Lastly, we will analyze the DC operation of
MOSFETs.
ES154 - Lecture 7 - MOSFETs
Enhancement-Type MOSFET
Most widely used field effect transistor (enhancement type)

Lets look at its structure and physical operation
3 terminal device (gate, source, drain)

Additional body (or bulk) terminal (generally at DC and not used for signals)
Two types:
nMOS and pMOS
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nMOS Transistor
Four terminal device: gate, source, drain (and body)

No connection between the gate and drain/source (separated by oxide)
Voltage on gate controls current flow between source and drain
Gate-oxide-body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a good insulator
Called Metal-Oxide-Semiconductor (MOS) capacitor
Gate no longer made out of metal, but poly
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Basic nMOS Operation
Body is commonly tied to ground (0V)

When the gate is at a low voltage (VG = 0):
P-type body is at low voltage
Source-body and drain-body diodes are OFF (reverse bias)
Depletion region between n+ and p bulk
No current can flow, transistor is OFF
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Basic nMOS Operation Contd
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When the gate is at a high voltage

Positive charge on gate of MOS capacitor
Negative charge attracted to oxide in the body (under the gate)
Inverts channel under the gate to n-type
Now current can flow through this n-type channel between source and drain
Transistor is ON
pMOS Transistor
Similar to nMOS, but doping and voltages reversed

Body tied to high voltage (Vdd)
Gate low: transistor is ON
inverted channel of positively charged holes
Gate high: transistor is OFF

Bubble indicates inverted behavior of the pMOS
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MOSFET in More Detail
An ON transistor passes a finite amount of current

Depends on terminal voltages and mode of operation
We will derive current-voltage (I-V) relationships
To enhance our understanding of MOS devices, lets take quick

aside to look the characteristics of a MOS capacitor and at band
diagrams
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Aside MOS Capacitor
Gate and body form a MOS cap

Operating modes
Accumulation
Depletion
Repels positive charge
Inversion
Inversion layer forms under
the gate
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Aside MOSFET Band Diagrams
A more rigorous look at MOSFETs requires us to again use band diagrams

energy diagram drawn relative to the vacuum level at equilibrium (no voltage applied)
metal work function, M, energy required to completely free an electron from the metal
electron affinity, , is the energy between the conduction band and vacuum level
Vacuum Level
Ef
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metal
semiconductor
oxide
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N-type semiconductor
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Aside Block Charge diagram
Provides information about the charge distribution inside a MOS structure

no charges at equilibrium
when bias is applied, charge appears within the metal and semiconductor at
the interfaces to the oxide
voltage drop across the oxide and there is an electric field due to the +Q and Q
charge separated by the oxide
charge
+Q
position
-Q
M
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We will use band diagrams and block charge diagrams to better understand how
MOS devices work
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Aside Applying Bias
Look at a pMOS (n-type bulk) device and see how applying a bias on the gate
affects the band and block charge diagrams
Accumulation
(VG > 0)
Onset of
Inversion
(VG = Vt)
+Q
+Q
-Q
-Q
M O S
M O
Depletion
(small VG < 0)
+Q
-Q
M O
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Inversion
(VG < Vt)
holes
+Q
-Q
M O S
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Terminal Voltages
The modes of operation depend on terminal

voltages Vg, Vd, and Vs
Vgs = Vg - Vs
Vgd = Vg - Vd
Vds = Vd - Vs = Vgs - Vgd
Source and drain are symmetric diffusion
terminals (transistors are symmetric devices)
By convention, source is the terminal at
the lower (higher) voltage for the nMOS
(pMOS) transistor
Hence, Vds > 0
nMOS body is grounded. First assume that
source is grounded as well
Three regions of operation
Cutoff
Linear
Saturation
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nMOS Cutoff Mode
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Vgs < Vt and so there is no channel

Source tied to body at 0V
Need a channel for current to flow Ids = 0
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nMOS Linear Mode
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Vgs > Vt and so a channel forms underneath the gate

Vt is the threshold voltage that sets when a channel forms
Current flows from d to s
Electrons flow from s to d
Ids increases with Vds
Similar to a linear resistor
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nMOS Saturation Mode
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Vds > Vgs Vt and channel pinches off at the drain side
b/c Vgd < Vt at the drain side (no channel at drain side)
We say current saturates and Ids is independent of Vds
Transistor operates similar to a current source
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I-V Characteristics
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In the Linear region of moderation, Ids depends on

How much charge is in the channel
How fast the charge is moving
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Channel Charge
MOS structure looks like a parallel plate capacitor while operating in

inversion
Gate-oxide-channel
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18
Carrier Velocity
Charge is carried by eCarrier velocity v is proportional to the lateral E-field between source
and drain
Time for carriers to cross the channel is
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19
nMOS Linear I-V
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Combine the channel charge and velocity to find the current flow
Current = amount of charge in the channel / time it takes the
carriers to get across the channel
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nMOS Saturation I-V
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If Vgd < Vt, channel pinches off near the drain

When Vds > Vdsat = Vgs Vt
Now, drain voltage no longer increases current and current saturates
(Idsat)
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Device Operation Review
No gate voltage (vGS = 0)

Two back to back diodes both in reverse bias
no current flow between source and drain when voltage
between source and drain is applied (vDS >0)
There is a depletion region between the p (substrate)
and n+ source and drain regions
Apply a voltage on vGS > 0
Positive potential on gate node pushes free holes away
from the region underneath the gate and leave behind a
negatively charged carrier depletion region
As vGS increases, electrons start to gather at the surface

underneath the gate (onset of inversion)
When vGS is high enough, a n-type channel is induced
underneath the gate oxide where there are more
electrons than holes (strong inversion)
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transistor in depletion mode
This induced region is called an inversion layer (or channel)

and forms when vGS > some threshold voltage Vt and
current can flow between S & D
Transistor is in inversion mode
When vDS = 0, no current flows between source and drain
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Linear Operation
iD
vGS = Vt + 3 V
vGS = Vt + 2 V
vGS = Vt + V
vGS <= Vt
vDS (small)
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With vGS large enough to induce a channel, apply a small potential vDS
Causes current to flow between source and drain (electrons flow from source to drain)
Magnitude of iD depends on density of electrons in channel which depends on vGS
(larger vGS = higher density of electrons)
Conductance of channel is proportional to vGS-Vt (called excess gate voltage or
effective voltage or gate overdrive)
Current is proportional to vGS-Vt and vDS that causes current to flow
i-v curve shows the transistor operates like a voltage-controlled linear resistor
Notice iD = iS and iG = 0 due to the gate oxide
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Triode to Saturation Region
Assume vGS is at a constant value > Vt and increase vDS

vDS appears as a voltage drop across the channel and at different points along the
channel, the voltage is different
Voltages between the gate and points along the channel are also different ranging from
vGS at the source to vGS-vDS at the drain
i-v curve bends over as vDS increases due to the smaller channel depth
At vDS = vGS-Vt channel depth is almost zero at the drain side
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Induced channel is a function of voltage across the oxide at the different points and so channel
depth varies across the length of the transistor
Current stays flat for higher voltages vDS > vGS-Vt

The transistor is said to now operate in the saturation region (not to be confused with the
saturation region in BJTs)
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Saturation Region
vDS >= vGS - Vt
source
channel
drain
vDS
vDS = 0
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As vDS increases, the channel gets smaller and smaller on the drain side until vDS = vGS Vt
at which point the channel is said to be pinched off
Increasing vDS beyond this point as little (ideally no) effect on the channel shape
Current remains constant and said to saturate
Transistor enters saturation at vDSsat = vGS Vt
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Deriving the iD-vDS Relationship
First consider the linear (triode) region of operation vDS < vGS - Vt (vGS > Vt is assumed)
Consider a point along the channel of infinitesimal width dx at x and voltage v(x)
The electron charge at this point is:
where Cox is the parallel-plate cap formed by the gate electrode and the channel
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vDS produces as electric field along the channel (in the negative x direction)
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The electric field causes electron charge dq(x) to drift with a velocity dx/dt
Where n is the electron mobility in the channel

Current is the movement of charge and so
Rearrange the equation and integrate along the length of the channel
Gives the current in the linear (triode) region:
When vDS=vGS-Vt, we get the saturation current equation
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nMOS I-V Summary
Shockley 1st order model of transistors

Cutoff
Linear
Saturation
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+ Ideal Quadratic nMOS i-V

linear
saturation
Vg = 2.5V
ids
saturation starts
Vg = 2.0V
Vg = 1.5V
Vg = 1.0V
Vds
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nMOS and pMOS
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Weve just seen how current flows in nMOS devices. A complementary version
of the nMOS device is a pMOS shown above
pMOS operation and current equations are the same except current is due
to drift of holes
The mobility of holes (p) is lower than the mobility of electrons (n)
Current is lower in pMOS devices given the same dimension and voltages.
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Circuit Symbols
nMOS or nFET
pMOS or pFET
We represent MOSFETs with the following symbols

The book specifies nMOS vs. pMOS with arrows (direction of current flow)
I will use bubbles b/c they are easier to distinguish quickly
a digital circuit designers way of drawing symbols
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These are symmetric devices and so drain and source can be used
interchangeably
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i-v Characteristics
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For small values of vDS, vDS2 is small and so near the origin, we can approximate
the transistor as a linear resistor
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We can get a relationship between iD and vGS

when the transistor is in saturation
Let vGS-Vt = VDS
MOS vs. BJT

Current is quadratic with voltage in MOS vs.
exponential relationship in BJT
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Some Non-Ideal Characteristics
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Channel-length modulation
Body effect
Velocity saturation
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Channel-Length Modulation
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Like the Early effect in BJTs, there is an effect in MOSFETs that causes drain
current to vary with vDS in saturation (finite output resistance)
As vDS increases beyond vDSsat, the pinch off point moves away from the drain
by L and has the effect of changing the effective channel length in the
transistor
Account for this effect with a (1+vDS) term in the saturation current
equation
35
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Channel-length modulation makes the output resistance in saturation finite
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Body Effect
So far, we have been ignoring the substrate (or bulk or body) of the transistor and assumed
that is it tied to the source. However, we cannot always make that assumption.
In integrated circuits, the body is common to many MOS transistors and is connected
to the most negative (positive) supply for nMOS (pMOS) transistors.
The resulting reverse-bias voltage between the source and substrate affects device
operation.
Reverse bias will widen the depletion region and reduces channel depth which can
be modeled as changing the threshold voltage
where Vth0 is the threshold voltage when VSB=0, f is a physical parameter, is a

fabrication-process parameter
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is typically 0.5-V1/2
As VSB increases, Vt increases which affects the transistors i-v characteristics
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Temperature Effects
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Vt and mobility n,p are sensitive to temperature

Vt decreases by 2-mV for every 1C rise in temperature
mobility n,p decreases with temperature
Overall, increase in temperature results in lower drain currents
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Velocity Saturation
So far, the saturation current equation is quadratic with overdrive voltage

(vGS-Vth) and said to obey the square law which is valid for long channel length
(>1-m) devices
As transistor dimensions decrease, gate oxide gets thinner and there is a higher
vertical and horizontal electrical field that the electrons moving through the
channel experience
Causes electrons to bounce up to the oxide (more scattering) and saturates
the velocity at which current flows across the channel
Can approximate the effect of velocity saturation with the following powerlaw equation for saturation current
ranges from 1 to 2 depending on process technology (transistor length)

This approximation is not rigorous, but convenient to use. More accurate
models of the velocity saturation equation can be found in more advanced
courses that cover MOS devices and circuits
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Real nMOS i-V Curve
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i-v curves of nMOS transistor

in 0.5-m CMOS technology
W = 2.5-m, L = 0.6-m
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Depletion-type MOSFETs
Depletion-type MOSFETs have a channel with zero vGS (symbol is drawn with
channel)
must apply negative vGS to turn off device
Can be used as resistor loads (will see later)
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41
MOSFET at DC Example
Current Mirror
What is vGS?
How is ID related to ISRC?
What is ID vs. VD?
ID
ISRC
VD
vGS
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42
MOSFET Amplifier
The MOSFET can be configured to operate as

an amplifier. One of the simplest amplifier
configurations one can build with a MOSFET
is a common-source amplifier.
Requirements for proper operation
MOSFET must operate in saturation
Depends on RD and voltage biasing VGS
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Load Line
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Use a load line to see the operating point of the transistor w.r.t. RD and VGS
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DC Biasing
There are many ways to bias the CS nMOS Amp. Here are two
ways
What is VIN (or VGS) for the circuit on the right?

What is the cap for?
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45
DC Bias
First bias MOSFET in saturation region (equivalent to active region

in BJTs) to operate as an amplifier
set vgs = 0 and find ID (for now, assume =0)
To be in saturation,
Apply a small signal, vgs, to the gate
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Three components of iD
First term = DC current

Second term = current proportional to vgs
Third term = undesired nonlinear distortion
Make vgs small to reduce effect of third term
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This is the small-signal condition and lets us use the

following approximation
and we can relate id to vgs with a transconductance
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Small-Signal Voltage Gain (vd/vgs)
This gain equation hold for small signals

Notice that the output is 180 out of phase w.r.t. the input
Again, we can separate out the DC bias conditions and the

small-signal operation of the circuit
Look at the small-signal equivalent circuit for a MOSFET
biased in the saturation region
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Small-Signal Equivalent Circuit
A MOSFET operates like voltage controlled current source (for small signals)
Like the Early effect in the BJT, channel length modulation results in an
output resistance, ro
where VA = 1/
When using small-signal equivalent circuits, all DC sources are set to 0 since
they do not change
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49
Transconductance
Lets take a closer look at transconductance, gm
Depends on
process technology nCox
physical geometry W/L
make short and wide for high gm
DC bias VGS
making VGS large increases gm, but can limit voltage range on drain
Another way to write gm
gm is proportional to the square root of the DC bias current
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50
T-Model
Sometimes easier to analyze circuits using a different model

T-Model and -Model are equivalent circuits
Resistance looking into the source is 1/gm
Resistance looking into G is still since ig=0
-Model
T-Model
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51
Body Effect
D
B
G
vgs
gmvgs
ro
gmbvbs
vbs
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Body Effect
We saw that the substrate bias VBS affects Vt which has the effect
of influencing current like another gate
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Example 1: CS Amp with Resistor Biasing

VDD
R1
RD
vDS
Rs
vin
Lets look at another CS amplifier

example
What does the mid-band small-signal
equivalent circuit look like?
What is vbs?
What is Rin seen by the source?
What is Rout?
R2
Rs
gmvgs
vin
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R1||R2
vgs
gmbvbs
ro
RD vds
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Example 1 contd
Use the small-signal equivalent circuit to figure out small-signal gain,

Rin and Rout
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In Pursuit of More Gain
How can we make the gain bigger?

Can we arbitrarily increase RD?
Would like to make the load line shallow and shifted up

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55
Example 2:
Common-Source Amplifier w/ Active Load
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Active load uses current source instead of

load resistor
Biasing so that Q2 in saturation and its

output resistance is the effective
resistor load for Q1
Combine the I-V curves
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Look at the Voltage Transfer Characteristics (VTC) of the circuit

Operates like a high-gain amplifier (steep slope) in region III
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CS Amplifier low-frequency small-signal model
vi
What is the voltage gain?
vgs
gmvgs
ro1
ro2
Output Resistance of
Current Source
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vo
What are Rin and Rout?
58
Supplemental Slides on MOS Transistors

from CS148
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59
Fabricating CMOS Transistors
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CMOS transistors are fabricated on a silicon wafer

Lithography process similar to printing press
On each step, different materials are deposited and etched
Multiple steps per layer drawn in layout
Understand by viewing both top and cross section of wafer in a
simplified manufacturing process
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Inverter Cross Section
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Typically use p-type substrate (wafer) where nMOS transistors are

drawn
Need to create n-well for body of pMOS transistors
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Well and Substrate Taps
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Substrate (p-type) must be tied to Gnd and nwell tied to Vdd

Metal to lightly-doped semiconductor forms a poor contact connection
(Shottky Diode)
Use heavily doped well and substrate contacts (taps)
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Inverter Mask Set
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Transistors and wires are defined by masks

Cross section taken along dashed line
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Detailed Mask Views
Six masks
nwell
polysilicon (gate)
n+ diffusion
p+ diffusion
contact
metal
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Fabrication Steps
Start with blank wafer

Build inverter from bottom up
First step will be form the nwell
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where nwell should be
Implant or diffuse n dopants into exposed portion of wafer
Strip off SiO2
Grow SiO2 on top of Si wafer

900-1200 C with H2O or O2 in oxidation furnace
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Photoresist
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Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
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Lithography
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Expose photoresist through nwell mask

Strip off exposed photoresist
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Etch
Etch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone not something you want to
have around in your bathroom
Only attacks oxide where photoresist has been exposed
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68
Strip Photoresist
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Strip off remaining photoresist

Use mixture of acids called piranah etch
Needed so that resist doesnt melt in next step
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nwell
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Nwell is formed with diffusion or ion implantation

Diffusion
Place wafer in a furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion implantation
Blast wafer with beams of As ions
Ions blocked by SiO2, only enter where Si exposed
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Strip Oxide
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Strip off the remaining oxide with HF

Back to bare wafer with nwell
Subsequent steps involve similar series of steps
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Polysilicon
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Depost very thin later of gate oxide

< 20 angstoms (6-7 atomic layers)
Chemical vapor deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small Si crystals called polysilicon
Heavily doped to be a good conductor
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Polysilicon patterning
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Use same lithography process to pattern polysilicon
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Self-Aligned Process
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Use oxide and masking to expose where n+ dopants should be diffused

or implanted
N-diffusion forms nMOS source, drain, and nwell contact
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N-diffusion
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Pattern oxide and form n+ regions

Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates b/c it doesnt melt
during later processing
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N-diffusion contd
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Historically, dopants were diffused

Usually ion implantation is used today
But regions still called diffusion
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N-diffusion contd
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Strip off oxide to complete patterning step
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P-Diffusion
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Similar set of steps to form p+ diffusion regions for pMOS source and
drain and substrate contact
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Contacts
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Now we need to wire the devices together

Cover chip with thick field oxide
Etch oxide where contact cuts are needed
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Metalization
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Sputter on aluminum over entire wafer

Patter to remove excess metal, leaving wires
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Layout
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Chips are specified with set of masks

Minimum dimensions of masks determine transistor size (and
hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon (minimum channel
length)
Feature size improves 30% every three years or so
Normalize for feature size when describing design rules
Express rules in terms of = f/2
We will use \lambda = 0.3m in 0.6 m process (actually a
0.5 m process but drawn as 0.6 m)
Next time: Learn SUE and Magic to draw your own layouts!
81

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Lecture 7

ES154 - Lecture 7 - MOSFETs

Most widely used field effect transistor (enhancement type)

3 terminal device (gate, source, drain)

ES154 - Lecture 7 - MOSFETs

Four terminal device: gate, source, drain (and body)

ES154 - Lecture 7 - MOSFETs

Basic nMOS Operation

Body is commonly tied to ground (0V)

No current can flow, transistor is OFF

ES154 - Lecture 7 - MOSFETs

Basic nMOS Operation Contd

When the gate is at a high voltage

ES154 - Lecture 7 - MOSFETs

Similar to nMOS, but doping and voltages reversed

Gate high: transistor is OFF

ES154 - Lecture 7 - MOSFETs

MOSFET in More Detail

An ON transistor passes a finite amount of current

To enhance our understanding of MOS devices, lets take quick

ES154 - Lecture 7 - MOSFETs

Aside MOS Capacitor

Gate and body form a MOS cap

ES154 - Lecture 7 - MOSFETs

Aside MOSFET Band Diagrams

A more rigorous look at MOSFETs requires us to again use band diagrams

ES154 - Lecture 7 - MOSFETs

Aside Block Charge diagram

Provides information about the charge distribution inside a MOS structure

ES154 - Lecture 7 - MOSFETs

Aside Applying Bias

ES154 - Lecture 7 - MOSFETs

The modes of operation depend on terminal

ES154 - Lecture 7 - MOSFETs

nMOS Cutoff Mode

Vgs < Vt and so there is no channel

ES154 - Lecture 7 - MOSFETs

nMOS Linear Mode

Vgs > Vt and so a channel forms underneath the gate

ES154 - Lecture 7 - MOSFETs

nMOS Saturation Mode

ES154 - Lecture 7 - MOSFETs

In the Linear region of moderation, Ids depends on

ES154 - Lecture 7 - MOSFETs

MOS structure looks like a parallel plate capacitor while operating in

ES154 - Lecture 7 - MOSFETs

Time for carriers to cross the channel is

ES154 - Lecture 7 - MOSFETs

nMOS Linear I-V

ES154 - Lecture 7 - MOSFETs

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near the drain

ES154 - Lecture 7 - MOSFETs

Device Operation Review

No gate voltage (vGS = 0)

As vGS increases, electrons start to gather at the surface

transistor in depletion mode

This induced region is called an inversion layer (or channel)

When vDS = 0, no current flows between source and drain