RossLightfoot

ECEN248504
Lab4
Mehnaz
22615

1. Objectives
Tousewhatwevelearnedsofaranddesignandtest
a4bitArithmeticLogicUnit(ALU)whichwilladd,subtract
orperformbitwiseandoperations.Thisentailslearning
aboutadd/submodulesaswellasmultiplexers.

2. Design

1)
S

Y=SA+SB
2)Schematicsforprelab

3)
C_0

C_1

Op

AND

AND

ADD

SUB

4)
Control(0,1) A

Overflow

0x

1010

0000

0000

0x

1111

1011

1011

0x

1010

0101

0000

0x

0110

1101

0100

0x

1100

1110

1100

0x

0011

0111

0011

0x

1110

1111

1110

0x

0101

0011

0001

10

1110

0110

0100

10

1111

0000

1111

10

1100

1001

0101

10

1011

1100

0111

11

1010

0011

1001

11

0111

0101

1010

11

0110

1010

1100

11

0011

1111

0011

5)

3. Results
Mymodulesallperformedasexpected.Differentcvaluesgave
differentdifferentopperationsontheinputoperands.

4. conclusion
InthislabIdesignedandimplementeda4bitALU.Todothiswelearnedabout
andthendesignedamaddition/subtractmodulealongwitha2:1multiplexer.Thenwe
usedourknowlegeandalreadybuiltcircuitstoforma4bitALUfromthetwo
componentswebuiltearlier.

5. Questions

Maxgatedelay:12
seeDesign4&5

Whatdidyoulikemostabouttheassignmentandwhy?Whatdidyoulike
leastaboutitandwhy?

Ilikedhoweachtaskwasadifferentcomponentuntiltheendwhenwecombined
thethingswehadalreadycompletedtogetthefinalproduct.