DauHoang-KTMT-Chuong 3a - CPU Pipeline

HC VIN CNG NGH BU CHNH VIN THNG
BI GING MN
KIN TRC MY TNH
Ging vin: Ths. Trng Giang

Ngy sinh: 05/01/1987
Chuyn mn: Th.s Cng ngh thng tin
in thoi: 0975.388.005
E-mail: giangdaohanam@gmail.com
BI GING MN KIN TRC MY TNH
CHNG 3a CPU PIPELINE
NI DUNG
1.
2.
3.
4.
5.
6.
7.
8.
www.ptit.edu.vn
Gii thiu v CPU pipeline

Cc vn ca pipeline
Gii quyt vn xung t ti nguyn
Gii quyt vn xung t d liu
Qun l r nhnh trong pipeline
Gii thiu pipeline ca mt s CPU
Siu pipeline
Cu hi n tp
GING VIN: TS. HONG XUN DU

B MN: KHOA HC MY TNH - KHOA CNTT1
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3a.1 Gii thiu CPU pipeline Dy chuyn lp rp t
Mi dy chuyn
lp rp c chia
thnh nhiu cng
on;
Nhiu t cng
c lp rp trn
mt dy chuyn;
Ti mi cng on,
mt phn vic c
hon thnh;
Sau mi nhp thi
gian mt t hon
thin cui dy
chuyn v mt t
bt u hnh thnh
u dy chuyn.
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3a.1 Gii thiu CPU pipeline Nguyn l
Khng pipeline
C pipeline
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Vic thc hin lnh c chia nh thnh cc giai on
5 giai on ca mt h thng load-store n gin:
Instruction Fetch - IF: c lnh t b nh (hoc cache)
Instruction Decode - ID: gii m lnh v c cc ton hng
Execute - EX: thc hin lnh; nu l lnh truy nhp b nh: tnh
ton a ch b nh
Memory Access - MEM: c/ghi b nh; no-op nu khng
truy nhp b nh
Write Back - WB: Ghi kt qu vo cc thanh ghi.
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www.ptit.edu.vn

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3a.1 Gii thiu CPU pipeline c im

L dng x l song song mc lnh (instruction level
parallelism (ILP));
Mt pipeline l y (fully pipelined) khi n lun tip nhn
mt lnh mi ti mi chu k ng h;
Ngc li, mt pipeline l khng y khi c mt s chu
k tr trong tin trnh thc hin;
S lng cc giai on (stages) trong pipeline ph thuc
vo thit k vi x l:
2,3, 5 giai on (pipeline n gin)

14 giai on (PII, PIII)
20-31 giai on (P4)
12-15 giai on (Core)
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3a.1 Gii thiu CPU pipeline P6 (PIII, M)
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3a.1 Gii thiu CPU pipeline S lng stages

Thi gian thc hin mi giai on
Cc stages nn c thi gian thc hin bng nhau
Cc stages chm cn c tch nh
Cc vn lin quan n ti nguyn

iu g xy ra khi hai giai on c lnh v c ton hng u
truy nhp b nh?
iu g xy ra khi hai giai on c lnh v thc hin lnh (tnh
a ch b nh) u truy nhp PC?
Pipeline di bao nhiu l tt?

V nguyn tc: cng nhiu stages, hiu qu cng cao
Pipeline di nu b trng rng v mt l do no s tn nhiu
thi gian in y.
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3a.2 Cc vn ca pipeline Logic gate hazard
Logic Gate Hazard
Gi tr ra mong i (theo thit k) lun l 0 (false)

Tuy nhin, trong mt s thi im gi tr ra l 1 (true)
Hazard (khng theo thit k).
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3a.2 Cc vn ca pipeline
Vn xung t ti nguyn (resource conflicts)
Xung t truy nhp b nh
Xung t truy nhp cc thanh ghi
Tranh chp d liu (Data hazards):

Vn read after write hazard (RAW)
Cc lnh r nhnh (Branch instructions)

Khng iu kin
C iu kin
Gi thc hin v tr v t chng trnh con
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3a.3 Xung t ti nguyn

Khng ti nguyn phc v CPU;
V d: nu b nh ch h tr mt truy nhp ti mi thi im
v nu ti cng mt thi im, pipeline yu cu hai truy
nhp b nh (c lnh ti giai on IF v c d liu ti
giai on ID) ny sinh xung t.
www.ptit.edu.vn

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3a.3 Xung t ti nguyn

Gii php: Thm ti
nguyn hoc nng cao
nng lc phc v ca ti
nguyn:
Memory/Cache: h tr
nhiu truy nhp ti mt
thi im;
Chia cache thnh 2 phn:
I-Cache v D-Cache
ci thin kh nng truy
nhp.
www.ptit.edu.vn

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3a.4 Xung t d liu RAW

Xem xt hai lnh:
ADD R1, R1, R3 ;R1 R1+R3
SUB R4, R1, R2 ;R4 R1-R2
Lnh SUB s dng kt qu ca ADD c s ph thuc d

liu gia hai lnh
SUB c R1 trong giai on 2 (ID), cn ADD ghi kt qu
trong giai on 5 (WB)
SUB c gi tr c ca R1 trc khi ADD lu gi tr mi ca
R1.
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3a.4 Xung t d liu RAW
ADD R1, R1, R3 ;R1 R1+R3

SUB R4, R1, R2 ;R4 R1-R2
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3a.4 Xung t d liu RAW Hng khc phc

Nhn dng RAW hazard khi n din ra
Khi RAW hazard xy ra, tm dng (stall) pipeline cho n
khi lnh pha trc hon tt giai on WB.
C th s dng compiler nhn dng RAW v:
Chn thm cc lnh NO-OP vo gia cc lnh c th gy ra
RAW;
Thay i trt t cc lnh trong chng trnh v chn cc lnh
c lp vo gia cc lnh c th gy ra RAW;
S dng phn cng nhn dng RAW v d on trc

gi tr d liu ph thuc.
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Li thi im thc hin SUB bng cch chn

thm 3 lnh NO-OP
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Chn thm 3 lnh c lp d liu vo

gia 2 lnh ADD v SUB c th sinh ra RAW
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3a.5 Qun l r nhnh trong pipeline

T l cc lnh r nhnh trong chng trnh khong 10-30%.
Lnh r nhnh gy ra:
Ngt qung qu trnh thc hin bnh thng ca chng trnh;
Lm cho pipeline trng rng nu khng c bin php phng
nga/ngn chn.
Vi cc VXL c pipeline di nh P4 (31 stages) v nhiu

pipeline chy song song, vn lnh r nhnh cng tr nn
phc tp:
Phi y ton b cc lnh ang thc hin cc ng khi gp
lnh r nhnh;
Np mi cc lnh t a ch r nhnh vo pipeline. Tiu tn
nhiu thi gian in y pipeline.
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3a.5 Qun l r nhnh trong pipeline
Khi gp lnh r nhnh, cc lnh k tip np b y ra khi

pipeline v sau cc lnh t a ch ch c np vo
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3a.5 Qun l r nhnh Cc gii php

1. Branch Targets (ch r nhnh)
2. Conditional Branches (r nhnh c iu kin)
Delayed Branching (lm chm r nhnh)
Branch Prediction (d on r nhnh)
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3a.5 Qun l r nhnh PIII Branch Targets
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3a.5 Qun l r nhnh Branch Targets

Khi mt lnh r nhnh c thc thi, lnh tip theo c
np l lnh a ch ch (target), khng phi lnh k tip
lnh nhy.
JUMP <Address>
ADD R1, R2
Address: SUB R3, R4
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3a.5 Qun l r nhnh Branch Targets

Lnh r nhnh c nhn bit giai on ID, vy c th
bit trc chng bng cch gii m sm.
S dng Branch Target Buffer (BTB) lu vt ca cc
lnh r nhnh c thc thi:
Cc a ch ch ca cc lnh r nhnh
Lnh ch ca cc lnh r nhnh
Nu cc lnh r nhnh c ti s dng (trong vng lp):

/c ch r nhnh ca chng c th c s dng m khng
cn tnh ton li;
Cc lnh r nhnh c th c s dng ngay m khng cn
phi np li t b nh.
Vic ny thc hin c do a ch v lnh ch r nhnh
thng khng thay i.
www.ptit.edu.vn

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3a.5 Qun l r nhnh R nhnh c iu kin

Vic qun l cc lnh r nhnh c iu kin (conditional
branches) phc tp hn do:
C 2 lnh r nhnh ch phi la chn;
Khng th xc nh chnh xc lnh ch r nhnh cho n khi
lnh r nhnh thc hin.
Branch Target Buffer cng khng th hn ch c tr do ta
vn phi ch cho n khi bit c ch ca lnh r nhnh.
Gii php:
Delayed branching: lm chm r nhnh
Branch prediction: d on r nhnh
www.ptit.edu.vn

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3a.5.1 R nhnh c iu kin - Delayed branching

tng chnh: lnh r nhnh s khng gy ra s r nhnh
tc th m c lm tr mt s chu k, ph thuc vo
chiu di ca pipeline.
c im ca Delayed branching:
Lm vic tt nht trn cc VXL RISC cc lnh c thi gian
thc hin ngang nhau;
Pipeline ngn (thng l 2 stages)
Lnh ngay sau lnh r nhnh lun c thc hin, khng ph
thuc vo kt qu ca lnh r nhnh.
Cch thc hin:

S dng compiler chn thm lnh NO-OP vo sau lnh r
nhnh, hoc;
Chuyn 1 lnh c lp t trc ra ngay sau lnh r nhnh.
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Cho dy lnh:
ADD R2, R3, R4
CMP R1,0
JNE somewhere
Thm NO-OP sau lnh r nhnh

ADD R2, R3, R4
CMP R1,0
JNE somewhere
NO-OP
Chuyn lnh c lp pha trc ra ngay sau lnh r nhnh:

CMP R1,0
JNE somewhere
ADD R2, R3, R4
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D thc hin thng qua ti u trong ho trnh bin dch,
khng i hi phn cng c bit;
Gim hiu nng khi pipeline di nu ch chn thm NO-OP.
V d nu pipeline c 5 stages -> i hi 5 lnh NO-OP.
Thay NO-OP bng lnh c lp c th gim ~70% NO-OP.
Tng phc tp ca m chng trnh.
i hi ngi lp trnh v ngi vit trnh bin dch phi c
hiu bit su v kin trc pipeline ca cc VXL -> y l mt
hn ch ln.
Gim tnh kh chuyn ca m chng trnh, do khi kin trc
VXL thay i -> vit li hoc dch li.
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3a.5.1 R nhnh c iu kin - Branch prediction

tng: c th d on lnh ch ca lnh r nhnh c
iu kin.
on ng: gip tng hiu nng
on sai: y cc lnh np pha sau lnh r nhnh, np
lnh ch r nhnh.
Trng hp xu nht:
50% on ng v 50% on sai
Kt qu khng xu hn khng d on
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3a.5.1 R nhnh c iu kin - Branch prediction

Cc c s d on r nhnh:
Cc lnh nhy ngc:
Thng l mt phn ca mt vng lp;
Cc vng lp thng c thc hin nhiu ln
Ln lp cui c th sai
Cc lnh nhy xui kh d on hn:

C th l lnh kt thc vng lp
C th lnh nhy da trn mt iu kin
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3a.6 AMD K6-2 pipeline
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3a.6 Intel P6 (PIII, M) pipeline
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3a.6 Intel P4 pipeline
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3a.6 Intel Core 2 Duo pipeline
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3a.6 Intel Atom 16-stage pipeline
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3a. 7 Siu pipeline

Siu pipeline (Superpipelining) l k thut cho php:
Tng su ca ng lnh
Tng tc ng h
Gim thi gian tr cho tng giai on thc hin lnh
VD: nu giai on thc hin lnh bi ALU ko di chia

thnh mt s giai on nh gim thi gian ch cho cc
giai on ngn.
Pentium 4 siu ng vi 20 giai on:
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3a. 7 Siu pipeline
Pentium 4
siu ng
vi 20 giai
on
www.ptit.edu.vn

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3a.8 Cu hi n tp
1. CPU pipeline l g v cc c im?
2. Cc vn ca pipeline
3. Vn xung t d liu trong pipeline v gii php khc
phc
4. Vn r nhnh trong pipeline v gii php khc phc
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DauHoang-KTMT-Chuong 3a - CPU Pipeline

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HC VIN CNG NGH BU CHNH VIN THNG

Ging vin: Ths. Trng Giang

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

Gii thiu v CPU pipeline

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline Dy chuyn lp rp t

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline Nguyn l

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline Nguyn l

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline Nguyn l

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline c im

2,3, 5 giai on (pipeline n gin)

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline P6 (PIII, M)

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.1 Gii thiu CPU pipeline S lng stages

Cc vn lin quan n ti nguyn

Pipeline di bao nhiu l tt?

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.2 Cc vn ca pipeline Logic gate hazard

Logic Gate Hazard

Gi tr ra mong i (theo thit k) lun l 0 (false)

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

Tranh chp d liu (Data hazards):

Cc lnh r nhnh (Branch instructions)

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.3 Xung t ti nguyn

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.3 Xung t ti nguyn

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE

3a.4 Xung t d liu RAW

Lnh SUB s dng kt qu ca ADD c s ph thuc d

GING VIN: TS. HONG XUN DU

BI GING MN KIN TRC MY TNH

CHNG 3a CPU PIPELINE