VL7010!2!1 Introduction

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VL7010 Submicron VLSI Design

Presentation by:

C. THIRUVENKATESAN
Associate Professor / ECE

UNIT II
Sources of CMOS power consumption; Technology options for
low power: reduction of Pleak by technological measures reduction of Pdyn by technology measures - reduction of Pdyn by
reduced-voltage processes; Design option for low power;
Computing power vs chip power, a scaling perspective.
Course outcome: CO2

Introduction

Semiconductor Technology Trends

A good VLSI design system should provide for consistent


descriptions in all three description domains (behavioral, structural,
and physical) and at all relevant levels of abstraction (e.g.,
architecture, RTL/block, logic, circuit).
The means by which this is accomplished can be measured in
various terms that differ in importance based on the application.
These parameters can be summarized in terms of:
 Performancespeed, power, function, flexibility
 Size of die (hence, cost of die)
 Time to design (hence, cost of engineering and schedule)
 Ease of verification, test generation, and testability
(hence, cost of engineering and schedule)

Process Technology Trend

Cost-Perf. Designs - notebooks, desktop personal computers, telecom


Data extracted from NTRS97

Design Technology Trend

Example Applications
 Portable Electronics (PC, PDA, Wireless)
 IC Cost (Packaging and Cooling)
 Reliability (Electromigration, Latch-up)
 Signal Integrity (Switching Noise, DC Voltage Drop)
 Thermal Design
Where Does the Power Go?
Varies from one design to next

What Has Worked?


 Voltage and process scaling (3x/Generation)
 Design methodologies
 Power management through HW/SW, trade area for
lower power
 Architecture Design
 Power down techniques
 Clock gating, dynamic power management
 Dynamic voltage scaling based on workload
 Power conscious RT/ logic synthesis
 Better cell library design and resizing methods
 Cap. reduction, threshold control, transistor layout

Ultra Low Power System Design

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