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Datasheet ADC 0804 PDF
Datasheet ADC 0804 PDF
ADC0804
8-Bit, MicroprocessorCompatible, A/D Converters
August 1997
Features
Description
The ADC0802 family are CMOS 8-Bit, successive-approximation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Ordering Information
PART NUMBER
ERROR
ADC0802LCN
1/2 LSB
ADC0802LCD
3/4 LSB
1 LSB
ADC0802LD
ADC0803LCN
1/2 LSB
ADC0803LCD
3/4 LSB
EXTERNAL CONDITIONS
VREF/2 = 2.500VDC (No Adjustments)
0 to 70
PACKAGE
PKG. NO
20 Ld PDIP
E20.3
-40 to 85
20 Ld CERDIP
F20.3
-55 to 125
20 Ld CERDIP
F20.3
20 Ld PDIP
E20.3
-40 to 85
20 Ld CERDIP
F20.3
0 to 70
ADC0803LCWM
1 LSB
-40 to 85
20 Ld SOIC
M20.3
ADC0803LD
1 LSB
-55 to 125
20 Ld CERDIP
F20.3
ADC0804LCN
1 LSB
20 Ld PDIP
E20.3
ADC0804LCD
1 LSB
-40 to 85
20 Ld CERDIP
F20.3
ADC0804LCWM
1 LSB
-40 to 85
20 Ld SOIC
M20.3
Pinout
0 to 70
CS
RD
V+ 20
CLK R 19
WR
CLK IN
INTR
11
DB7
DB4
VIN (+)
DB3
VIN (-)
20 V+ OR VREF
RD
19 CLK R
WR
18 DB0 (LSB)
CLK IN
17 DB1
INTR
16 DB2
15
VIN (+)
15 DB3
16
VIN (-)
14 DB4
17
AGND
13 DB5
18
VREF/2
12 DB6
DGND 10
ANY
PROCESSOR
P BUS
CS
12
13
14
+5V
150pF
10K
DB6
DB5
DB2
DB1
DB0
AGND 8
VREF/2 9
DGND 10
DIFF
INPUTS
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
VREF/2
11 DB7 (MSB)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
6-5
File Number
3094.1
RD
CS
WR
READ
1
3
SET
RESET
INPUT PROTECTION
FOR ALL LOGIC INPUTS
CLK R
19
CLK
INPUT
CLK A
CLK IN
TO INTERNAL
CIRCUITS
G1
RESET
4
CLK OSC
BV = 30V
CLK
GEN CLKS
DFF1
Q
START F/F
10
DGND
START
CONVERSION
CLK B
MSB
V+
(VREF)
VREF/2
20
LADDER
AND
DECODER
SUCCESSIVE
APPROX.
REGISTER
AND LATCH
8-BIT
SHIFT
REGISTER
IF RESET = 0
R
RESET
AGND
DAC
VOUT
LSB
INTR F/F
CLK A
V+
VIN (+)
VIN (-)
DFF2
COMP
Q
XFER
THREE-STATE
OUTPUT LATCHES
G2
SET
5
LSB
MSB
CONV. COMPL.
11 12 13 14 15 16 17 18
8 X 1/f
DIGITAL OUTPUTS
THREE-STATE CONTROL
1 = OUTPUT ENABLE
6-6
INTR
Thermal Information
Operating Conditions
Temperature Range
ADC0802/03LD. . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
ADC0802/03/04LCD . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
ADC0802/03/04LCN . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
ADC0803/04LCWM . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
(Notes 1, 7)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
VREF/2 = 2.500V
1/2
LSB
ADC0803
1/2
LSB
ADC0804
VREF/2 = 2.500V
LSB
1.0
1.3
(Note 2)
GND-0.05
(V+) + 0.05
DC Common-Mode Rejection
1/16
1/8
LSB
1/16
1/8
LSB
1/2
LSB
LSB
CONVERTER SPECIFICATIONS V+ = 5V, 0oC to 70oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
VREF/2 = 2.500V
ADC0803
1/
ADC0804
VREF/2 = 2.500V
LSB
(Note 2)
1.0
1.3
GND-0.05
(V+) + 0.05
1/8
1/16
1/4
1/8
LSB
3/4
LSB
3/
LSB
LSB
1.0
1.3
DC Common-Mode Rejection
LSB
CONVERTER SPECIFICATIONS V+ = 5V, -25oC to 85oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
VREF/2 = 2.500V
ADC0803
ADC0804
VREF/2 = 2.500V
(Note 2)
GND-0.05
(V+) + 0.05
DC Common-Mode Rejection
1/8
1/4
LSB
1/16
1/8
LSB
6-7
(Notes 1, 7) (Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CONVERTER SPECIFICATIONS V+ = 5V, -55oC to 125oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
VREF/2 = 2.500V
LSB
ADC0803
LSB
(Note 2)
1.0
1.3
GND-0.05
(V+) + 0.05
1/8
1/8
1/4
1/4
LSB
kHz
DC Common-Mode Rejection
LSB
100
640
1280
V+ = 5V
100
640
800
kHz
62
73
Clocks/Conv
8888
Conv/s
100
ns
Access Time (Delay from Falling CL = 100pF (Use Bus Driver IC for
Edge of RD to Output Data Valid), Larger CL)
tACC
135
200
ns
125
250
ns
300
450
ns
pF
pF
CS = 0V (Note 5)
DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX , Unless Otherwise Specified
CONTROL INPUTS (Note 6)
Logic 1 Input Voltage (Except
Pin 4 CLK IN), VINH
V+ = 5.25V
2.0
V+
V+ = 4.75V
0.8
2.7
3.1
3.5
1.5
1.8
2.1
0.6
1.3
2.0
VlN = 5V
0.005
VlN = 0V
-1
-0.005
1.3
2.5
mA
lO = 1.6mA, V+ = 4.75V
0.4
6-8
(Notes 1, 7) (Continued)
MIN
TYP
MAX
UNITS
PARAMETER
lO = -360A, V+ = 4.75V
TEST CONDITIONS
2.4
VOUT = 0V
-3
4.5
mA
9.0
16
mA
VOUT = 5V
NOTES:
1. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the
DGND, being careful to avoid ground loops.
2. For VIN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which
will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful,
during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature variations, initial tolerance and loading.
3. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
4. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion
process.
5. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse
width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see
Timing Diagrams).
6. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
7. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span
exists (for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet.
Timing Waveforms
2.4V
V+
tr = 20ns
tr
90%
50%
RD
RD
0.8V
DATA
OUTPUT
CS
CL
10%
t1H
VOH
10K
90%
DATA
OUTPUTS
GND
tr = 20ns
V+
V+
tr
2.4V
RD
10K
0.8V
RD
DATA
OUTPUT
CS
V+
CL
DATA
OUTPUTS
VOI
90%
50%
10%
t0H
10%
6-9
1.8
1.6
1.5
300
200
1.4
100
1.3
4.50
4.75
5.00
5.25
5.50
200
1000
R = 10K
3.1
VT(+)
R = 50K
fCLK (kHz)
2.7
-55oC TO 125oC
2.3
1.9
VT(-)
1.5
4.50
4.75
5.00
R = 20K
5.25
100
5.50
10
100
CLOCK CAPACITOR (pF)
16
VIN(+) = VIN(-) = 0V
14
12
V+ = 4.5V
5
4
3
V+ = 5V
1000
7
FULL SCALE ERROR (LSBs)
1000
3.5
CLK IN THRESHOLD VOLTAGE (V)
400
600
800
LOAD CAPACITANCE (pF)
10
8
6
4
1
2
V+ = 6V
0
0
400
800
1200
fCLK (kHz)
1600
0
0.01
2000
0.1
1.0
VREF/2 (V)
6-10
(Continued)
1.6
V+ = 5V
POWER SUPPLY CURRENT (mA)
fCLK = 640kHz
7
DATA OUTPUT
BUFFERS
6
ISOURCE
VOUT = 2.4V
-ISINK
VOUT = 0.4V
2
-50
-25
25
50
75
100
1.5
V+ = 5.5V
1.4
1.3
V+ = 5.0V
1.2
V+ = 4.5V
1.1
1.0
125
-50
-25
0
25
50
75
100
TA AMBIENT TEMPERATURE (oC)
Timing Diagrams
CS
WR
tWI
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
BUSY
tW(WR)I
DATA IS VALID IN
OUTPUT LATCHES
NOT BUSY
1 TO 8 x 1/fCLK
INTERNAL TC
INTR
ASSERTED
INTR
CS
INTR RESET
tRI
RD
VALID
DATA
DATA
OUTPUTS
tACC
125
THREE-STATE
(HI-Z)
VALID
DATA
t1H , t0H
6-11
1/ f
2 CLK
+1 LSB
D+1
5 6
ERROR
3 4
D-1
+1/2 LSB
* QUANTIZATION ERROR
0
-1/2 LSB
1 2
-1 LSB
A-1
A-1
A+1
A+1
TRANSFER FUNCTION
ERROR PLOT
+1 LSB
1
5
D+1
ERROR
3
D
QUANTIZATION
ERROR
1
D-1
4
2
-1 LSB
A-1
A+1
A-1
A+1
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11B. ACCURACY = 1/2 LSB
constant negative slope and the abrupt upside steps are always
1 LSB in magnitude, unless the device has missing codes.
Detailed Description
The functional diagram of the ADC0802 series of A/D
converters operates on the successive approximation principle (see Application Notes AN016 and AN020 for a more
detailed description of this principle). Analog switches are
closed sequentially by successive-approximation logic until
the analog differential input voltage [VlN(+) - VlN(-)] matches
a voltage derived from a tapped resistor string across the
reference voltage. The most significant bit is tested first and
after 8 comparisons (64 clock cycles), an 8-bit binary code
(1111 1111 = full scale) is transferred to an output latch.
The normal operation proceeds as follows. On the high-to-low
transition of the WR input, the internal SAR latches and the
shift-register stages are reset, and the INTR output will be set
high. As long as the CS input and WR input remain low, the
A/D will remain in a reset state. Conversion will start from 1 to
8 clock periods after at least one of these inputs makes a lowto-high transition. After the requisite number of clock pulses to
complete the conversion, the INTR pin will make a high-to-low
transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion. A RD
operation (with CS low) will clear the INTR line high again.
6-12
where:
VE is the error voltage due to sampling delay,
VPEAK is the peak value of the common-mode voltage,
fCM is the common-mode frequency.
For example, with a 60Hz common-mode frequency, fCM ,
and a 640kHz A/D clock, fCLK , keeping this error to 1/4 LSB
(~5mV) would allow a common-mode voltage, VPEAK , given
by:
V E ( MAX ) ( f
CLK )
V PEAK = -------------------------------------------------- ,
( 2f CM ) ( 4.5 )
or
3
( 5 10 ) ( 640 10 )
V PEAK = ---------------------------------------------------------- 1.9V .
( 6.28 ) ( 60 ) ( 4.5 )
6-13
V+
(VREF)
20
R
VREF/2
9
DIGITAL
CIRCUITS
Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize stray signal pickup (EMI).
Both EMI and undesired digital-clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 5k. Larger values of
source resistance can cause undesired signal pickup. Input
bypass capacitors, placed from the analog inputs to ground,
will eliminate this pickup but can create analog scale errors as
these capacitors will average the transient input switching currents of the A/D (see Analog Input Current). This scale error
depends on both a large source resistance and the use of an
input bypass capacitor. This error can be compensated by a
full scale adjustment of the A/D (see Full Scale Adjustment)
with the source resistance and input bypass capacitor in
place, and the desired conversion rate.
AGND
10
DGND
VREF
(5V)
ICL7611
Notice that the reference voltage for the IC is either 1/2 of the
FS
ADJ.
ANALOG
CIRCUITS
DECODE
SPAN/2
5V
300
TO VREF/2
+
0.1F
TO VIN(-)
VIN 10V
2R
VIN(+)
V+
ADC0802ADC0804
2R
7
20
+
10F
VIN(-)
6-14
5V
(VREF)
VIN 5V
VIN(+)
V+
ADC0802ADC0804
7
20
+
10F
VIN(-)
( V MAX V MIN )
V IN ( + ) f SADJ = V MAX 1.5 ----------------------------------------- ,
256
where:
and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)
Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, VlN(MlN) , is not ground, a
zero offset can be done. The converter can be made to output
0000 0000 digital code for this minimum input voltage by biasing the A/D VIN(-) input at this VlN(MlN) value (see Applications
section). This utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the VIN(-) input and applying a small magnitude
positive voltage to the VIN(+) input. Zero error is the difference
between the actual DC input voltage which is necessary to
just cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for
VREF/2 = 2.500V).
Clocking Option
The clock for the A/D can be derived from an external source
such as the CPU clock or an external RC network can be
added to provIde self-clocking. The CLK IN (pin 4) makes
use of a Schmitt trigger as shown in Figure 16.
CLK R
19
ADC0802ADC0804
R
CLK IN
C
fCLK
1
1.1 RC
R 10k
CLK
6-15
5V (VREF)
ADC0802 - ADC0804
150pF
1 CS
N.O.
START
ANALOG
INPUTS
V+ 20
2 RD
CLK R 19
3 WR
DB0 18
4 CLK IN
DB1 17
5 INTR
DB2 16
6 VIN (+)
DB3 15
7 VIN (-)
DB4 14
8 AGND
DB5 13
9 VREF/2
DB6 12
10 DGND
DB7 11
+
10F
LSB
DATA
OUTPUTS
MSB
N.O.
START
VIN (+)
19
18
17
Power Supplies
0.1F
AGND
2.560V
VREF/2
0.1F
20
ADC0802ADC0804
5.120V
10F
TANTALUM
LSB
16
15
14
13
12
10
11
DGND
5V
MSB
1.3k LEDs
(8)
(8)
6-16
VANALOG OUTPUT
10-BIT
DAC
R
R
B
ANALOG
INPUTS
A1
R
100R
R
A2
100X ANALOG
ERROR VOLTAGE
DIGITAL
OUTPUTS
VANALOG
The Z-80 and 8085 control buses are slightly different from
that of the 8080. General RD and WR strobes are provided
and separate memory request, MREQ, and I/O request,
IORQ, signals have to be combined with the generalized
strobes to provide the appropriate signals. An advantage of
operating the A/D in I/O space with the Z-80 is that the CPU
will automatically insert one wait state (the RD and WR
strobes are extended one clock period) to allow more time
for the I/O devices to respond. Logic to map the A/D in I/O
space is shown in Figure 22. By using MREQ in place of
IORQ, a memory-mapped configuration results.
A/D UNDER
TEST
Typical Applications
Interfacing 8080/85 or Z-80 Microprocessors
This converter has been designed to directly interface with
8080/85 or Z-80 Microprocessors. The three-state output
capability of the A/D eliminates the need for a peripheral
interface device, although address decoding is still required
to generate the appropriate CS for the converter. The A/D
can be mapped into memory space (using standard memory-address decoding for CS and the MEMR and MEMW
strobes) or it can be controlled as an I/O device by using the
I/OR and I/OW strobes and decoding the address bits A0
A7 (or address bits A8 A15, since they will contain the
same 8-bit address information) to obtain the CS input.
Using the I/O space provides 256 additional addresses and
may allow a simpler 8-bit address decoder, but the data can
only be input to the accumulator. To make use of the additional memory reference instructions, the A/D should be
mapped into memory space. See AN020 for more discussion of memory-mapped vs I/O-mapped interfaces. An
example of an A/D in I/O space is shown in Figure 21.
Application Notes
6-17
NOTE #
DESCRIPTION
AnswerFAX
DOC. #
AN016
9016
AN018
9018
AN020
9020
AN030
9030
INT (14)
I/O WR (27) (NOTE)
I/O RD (25) (NOTE)
10K
ADC0802 - ADC0804
ANALOG
INPUTS
150pF
1 CS
V+ 20
2 RD
CLK R 19
5V
+
10F
3 WR
DB0 18 LSB
4 CLK IN
DB1 17
5 INTR
DB2 16
6 VIN (+)
DB3 15
7 VIN (-)
DB4 14
8 AGND
DB5 13
9 VREF/2
DB6 12
10 DGND
DB7 11
5V
OUT
V+
B5
AD15 (36)
B4
AD14 (39)
B3
AD13 (38)
B2
AD12 (37)
T1
B1
AD11 (40)
T0
B0
AD10 (1)
T5
T4
T3
T2
8131
BUS
COMPARATOR
NOTE: Pin numbers for 8228 System Controller: Others are 8080A.
FIGURE 21. ADC0802 TO 8080A CPU INTERFACE
6-18
ADC0802 - ADC0804
RD
RD
ANALOG
INPUTS
IORQ
ADC0802ADC0804
150pF
V+ 20
2 RD
CLK R 19
10F
ABC
5V (8) 1 2 3
3 WR
DB0 18 LSB
D0 (33) [31]
4 CLK IN
DB1 17
D1 (32) [29]
5 INTR
DB2 16
D2 (31) [K]
6 VIN (+)
DB3 15
D3 (30) [H]
7 VIN (-)
DB4 14
D4 (29) [32]
8 AGND
DB5 13
D5 (28) [30]
9 VREF/2
DB6 12
10 DGND
WR
WR
1 CS
DB7 11
D6 (27) [L]
MSB
D7 (26) [J]
3
1
74C32
2
6
1/ DM8092
2
18
19
CB1
CB2
10K
ADC0802 - ADC0804
ANALOG
INPUTS
150pF
1 CS
V+ 20
2 RD
CLK R 19
MC6820
(MCS6520)
5V
PIA
3 WR
DB0 18 LSB
10
PB0
4 CLK IN
DB1 17
11
PB1
5 INTR
DB2 16
12
PB2
6 VIN (+)
DB3 15
13
PB3
7 VIN (-)
DB4 14
14
PB4
8 AGND
DB5 13
15
PB5
9 VREF/2
DB6 12
16
PB6
17
PB7
10 DGND
DB7 11
MSB
6-19
PASSIVATION:
METALLIZATION:
Type: Al
Thickness: 10k 1k
VIN (-)
VIN (+)
INTR
CLK IN
WR
VREF/2
RD
DGND
CS
DB7 (MSB)
DB6
V+ OR VREF
V+ OR VREF
DB5
CLK R
DB4
DB3
DB2
DB1
DB0
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6-20