FPGA/ CPLD LAB

EXPERIMENT 11
AIM : To design and simulate Universal Shift Register using Verilog HDL.
EDA TOOL USED : Xilinx ISE 8.1i
METHODOLOGY : A register is composed of a group of FFs to store a group of bits. A universal shift
register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it
can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions,
through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both
parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. In
order for the universal shift register to operate in a specific mode, it must first select the mode. To
accomplish mode selection the universal register uses a set of two selector switches, S[1] and S[0] as shown
in table. Its parallel outputs are A[0], A[1], A[2], A[3] and parallel inputs are I[0], I[1], I[2], I[3]. The control
of right and left shift is governed by rtin and lfin respectively. Universal shift registers, as all other types of
registers, are used in computers as memory elements. In fact, all the operations in a digital system are
performed on registers. Examples of such operations include multiplication, division, and data transfer.
Operating mode
Hold
Shift right
Shift left
Parallel load

S[1]
0
0
1
1

S[0]
0
1
0
1

Fig. 11.1 Block diagram of Universal Shift register

52

FPGA/ CPLD LAB

VERILOG CODE :
module muxd2(I0, I1, I2, I3, S0, S1, Y);
input I0, I1, I2, I3, S0, S1;

output Y;

assign {Y}=S0?(S1?I3:I1):(S1?I2:I0);
endmodule
module dff(d,clk,res, q);
input d,clk,res;
initial

begin

output reg q;
q<=0;

end

always@(posedge clk or posedge res)

begin

if (res)

begin q<=0; end

else

begin q<=d; end

end

endmodule
module universal(clk,s1,s0,dinl,dinr, q, i, doutl,doutr);
input clk,s1,s0,dinl,dinr;

input [3:0]i;

wire [3:0] d; output [3:0]q; output doutl,doutr;

muxd2 m1(q[3],dinr,q[2],i[3],s0,s1,d[3]);
muxd2 m2(q[2],q[3],q[1],i[2],s0,s1,d[2]);
muxd2 m3(q[1],q[2],q[0],i[1],s0,s1,d[1]);
muxd2 m4(q[0],q[1],dinl,i[0],s0,s1,d[0]);
dff d1(d[3],clk,res,q[3]); dff d2(d[2],clk,res,q[2]); dff d3(d[1],clk,res,q[1]);
dff d4(d[0],clk,res,q[0]); and(doutl,s1,~s0,q[3]); and(doutr,~s1,s0,q[0]);
endmodule

RTL SCHEMATIC VIEW :

(a)
53

FPGA/ CPLD LAB

(b)

(c)

(d)
Fig. 11.2 RTL schematic of Universal Shift register

OUTPUT WAVEFORM :

Fig. 11.3 Output waveform of Universal Shift register

54

FPGA/ CPLD LAB

RESULT : Universal Shift Register is successfully implemented and its operation is verified by
simulation.

55