Cascaded Counters

ECEn 224

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Mod-N Counters
Generally we are interested in counters that
count up to specific count values
Not just powers of 2

A mod-N counter has N states

Counts from 0 to N-1 then rolls over
Requires log 2 N flip flops

For example
A 4-bit binary counter is a mod-16 counter
A counter that counts from 0-9 is a mod-10
counter
ECEn 224

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A Mod-4 Counter
A.K.A. 2-bit counter

CLR INC Q1 Q0 N1 N0
0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
-

0
0
1
1
0
0
1
1
-

0
1
0
1
0
1
0
1
-

0
0
1
1
0
1
1
0
0

0
1
0
1
1
0
1
0
0

CLRINC
CLR

00
CLRINC

CLRINC
CLRINC

CLRINC

11

01
CLRINC

CLRINC

10
CLRINC
ECEn 224

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A Mod-4 Counter With Rollover Signal

CLR INC Q1 Q0 N1 N0 RO
0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
-

0
0
1
1
0
0
1
1
-

0
1
0
1
0
1
0
1
-

0
0
1
1
0
1
1
0
0

0
1
0
1
1
0
1
0
0

0
0
0
0
0
0
0
1
0

Mealy output

CLRINC
CLR

00
CLRINC / RO

CLRINC
CLRINC

CLRINC

The ROLL signal is used to tell

other circuitry that the counter
is rolling over to all 0s.

11

01
CLRINC

CLRINC

10
CLRINC
ECEn 224

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Cascaded Counters
Larger counters can be built by combining
smaller counters together
The rollover signal is used to communicate
when the upper counters should roll over
Two types of counters
Asynchronous
Synchronous

ECEn 224

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Cascaded Asynchronous Counter

digit0

digit1
2

Sequence should be:

00-01-02-03-10-11-12-

clr

But we get:
00-01-02-13-10-11-12-

As a general rule.
DO NOT tie the clock
inputs on modules to
anything but the clock!

clk

clk1

roll1

Mod-4
Counter

clr

Mod-4
Counter

inc

roll0

clk
digit1
digit0

0
2

1
3

roll0 / clk1

ECEn 224

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Cascaded Asynchronous Counter

digit0

digit1
clk1

clk

clr

roll1

Mod-4
Counter

clr

Mod-4
Counter

inc

roll0

digit1 increments
too early
clk
clr
digit0
roll0 / clk1
digit1

ECEn 224

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Cascaded Asynchronous Counter

The more stages we add to the counter, the
bigger the discrepancy between asynchronous
counters and what we expect

Stage 1
Stage 2
Stage 3

Expected

Async
Expected

Async

ECEn 224

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digit0

digit1
2

clk

clk1

clr

It is possible to modify
the circuit to get the
correct count sequence,
but the roll signal must
be glitch free!
The transition from the
value 1 to 2 (012 to 102)
makes it difficult, if not
impossible to eliminate
glitches.

Mod4
Counter

roll1

clr

Mod4
Counter

inc

roll0

clk
digit1
digit0

0
2

1
3

Possible hazard

roll0 / clk1

ECEn 224

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2003-2008
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Ripple Counters
When you tie a rollover-like signal to a clock
on the next higher digit
ripple counter
A ripple counter is an asynchronous counter
Transitions are not all synchronized to the clock
Different flip flops change at different times
Similar to gated clocks (seen earlier)

Asynchronous circuits are an advanced topic

ECEn 224

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Another Common Ripple Counter

Q3

Counts in normal binary:

0000
0001
0010
0011
0100
0101
0110
0111
1000

T Q
Q

Q2

T Q
Q

Q1

T Q
Q

Q0

T Q
Q
CLK

Whats wrong with this design?

ECEn 224

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Timing Diagram
clk

Q0 changes in response to clock edge

Q0

Only after Q0 changes does Q1s FF get a

clock
Only after that does Q2s FF get a clock

Q1
Q2

Q3

Logic depending on Q3 has very little time

to react before next clock edge

Net effect is that all the FFs change at

different times!

ECEn 224

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Asynchronous and Ripple Counters

Because asynchronous and ripple counters are
difficult to use correctly, they are avoided
Do not use them in your designs!
Violates globally synchronous design principle

Always use synchronous counters

ECEn 224

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Synchronous Counters
In a synchronous counter, all flip flops are
clocked by the same clock signal
They all change at the same time

Synchronous counters can be cascaded to

create larger counters that are also globally
synchronous

ECEn 224

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A Mod-4 Counter
CLR INC Q1 Q0 N1 N0 RO
0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
-

0
0
1
1
0
0
1
1
-

0
1
0
1
0
1
0
1
-

0
0
1
1
0
1
1
0
0

0
1
0
1
1
0
1
0
0

0
0
0
0
0
0
0
1
0

Count
Value
D Q

clr
IFL

Terminal
Count

clk
D Q
clk

inc

Roll
Over

ECEn 224

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A Mod-4 Counter
CLR INC Q1 Q0 N1 N0 RO
0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
-

0
0
1
1
0
0
1
1
-

0
1
0
1
0
1
0
1
-

0
0
1
1
0
1
1
0
0

0
1
0
1
1
0
1
0
0

0
0
0
0
0
0
0
1
0

Count
Value
D Q

clr
IFL

Terminal
Count

clk
D Q
clk

inc

We could make a mod-4 counter

from the block shown in red.

ECEn 224

21 CASCNT
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Roll
Over

2003-2008
BYU

Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

clr

CV

MOD4
inc

TC

Count
Value

CV

MOD4

Terminal
Count

inc

TC

clr

CV

MOD4

TC

inc

inc
Rollover

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

Assume that the second timer is already at the terminal count.

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

ECEn 224

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Cascaded Counters
digit0[1:0]

digit2[1:0]

digit1[1:0]

clk
clr

clr

CV

MOD4
inc

TC

clr

CV

MOD4
inc

TC

clr

CV

MOD4

TC

inc

inc

It looks like the inc signal ripples from counter to counter.

How is this different from the ripple counter examples?

ECEn 224

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Cascaded Synchronous Counter

clk
digit0

10

11

00

roll
digit1

00

01

ECEn 224

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Cascaded Synchronous Counter

Notice that all signals are synchronized with
the system clock

roll0
roll1

Signals:

clk
digit0
digit1
digit2
ECEn 224

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A Mod-4 Counter
With consolidated rollover logic
Count
Value
D Q

clr

IFL

Terminal
Count

clk
D Q

inc

Roll
Over

clk
A good mod-4 counter includes
the logic within the red block.
ECEn 224

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A Mod-4 Counter

inc

dout

MOD4
roll

clk
clr

ECEn 224

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Cascading two Mod-4 Counters

Count Sequence:
digit1 digit0

00
01
02
03
10
11
12
13
20
21
22
23
30
31
32
33
00

Increment higher digits

counter when lower digits
counter is rolling over
digit1
clk

digit0
clk

2
dout
clr

roll1 roll

MOD4
inc

2
dout

clr
roll0

ECEn 224

MOD4
roll

clr
inc

clr
inc

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Three-digit Mod-4 Counter

Can combine any counters that have a rollover signal
to make larger counters
Combine two 16-bit counters to make a 32-bit counter
Combine three mod-4 counters to make a three-digit
mod-4 counter
digit2
clk

clk

2
dout
clr

roll1 roll

digit0

digit1

MOD4
inc

clk

2
dout

clr

clr

roll1

MOD4
roll

ECEn 224

inc

2
dout

clr
roll0

MOD4
roll

clr
inc

21 CASCNT
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clr
inc

2003-2008
BYU

BCD Counter
Combine to create non-binary counters
BCD counter
digit2
clk

clk

4
dout
clr

roll1 roll

digit0

digit1

MOD10
inc

clk

4
dout

clr

clr

roll1

MOD10
roll

ECEn 224

inc

4
dout

clr
roll0

MOD10
roll

clr
inc

21 CASCNT
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clr
inc

2003-2008
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Hybrid Counters
Can combine different kinds of mod counters
Combine an 8-bit counter with a 16-bit counter
to create a 24-bit counter
Combine mod-24 and mod-60 counters to
create a digital H:M:S clock
Hours
clk

clk

5
dout
clr

day

MOD24
roll

Seconds

Minutes

inc

clk

6
dout

clr

clr

hour

MOD60
roll

ECEn 224

inc

6
dout

clr
min

MOD60
roll

clr
inc

21 CASCNT
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clr
sec

2003-2008
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D Flip Flop with Asynchronous Clear

and Clock Enable

Clock Enable
(a.k.a. Load)

Clear
(a.k.a. Reset)

ECEn 224

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Mod-4 Counter

D0
CLK

CEO
CE
CE

D1

ECEn 224

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Cascaded Synchronous Counter

Digit0

Digit1

CEO

CLK
Reset
Digit0
CEO
Digit1

ECEn 224

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Library Counters
Component libraries often have several
cascadable counters available
Can be cascaded to form desired width

Xilinx Library Counters

ECEn 224

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Summary
Mod-N counters are counters that count from
0 to N-1 then roll over
Adding rollover logic to counters allows us to
cascade counters
We can build large counters from smaller ones
We can easily build non-binary counters
BCD counter
HMS clock counter

Always use synchronous counters instead of

asynchronous counters
ECEn 224

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