EE 668: Systems Design

Spring Semester 2014

Assignment 1
Q1 A system receives byte wide data asynchronously using a 2 wire handshake (request/acknowledge).
It maintains a byte wide sum of all received bytes, ignoring any carry which results
from adding each received byte. It should output a bit which is 1 if the current sum
is divisible by 4 and 0 otherwise.
Draw a state diagram for the system.
2 Wire Handshake
Req
Ack

In a pull system, Receiver asserts Req to request data.

When the data source has data available, it places it
on the data lines and asserts Ack. The receiver uses
Ack to latch data and negates Req. Negation of Req
causes the data source to negate Ack.

Q2 A system receives bit serial data using a clock. (New bits arrive at every positive edge
of the clock, LSB first). 8 bits constitute a byte. Successive bytes are accumulated in
a sum The output should indicate if the current value of sum is divisible by 3.
This problem turned out to be a little more complex!
Checking for divisibility by 3 in binary values can be tricky!
Each arriving bit carries a place value. The value of a byte B is
B=

7
X

2i bi

Each arriving bit contributes a value which is 0, 1 or -1 modulo 3.

If the bit is 0, it always contributes 0 and can be ignored for generation of the output.
If the bit is 1, it contributes a +1 or -1 depending on place value.
As the place value increases, the sign of contribution alternates.
Thus, 1 contributes +1 modulo 3, 2 contributes -1 modulo 3, 4 contributes +1, 8 contributes -1 and so on.
So the arrival of a 1 in the bit stream should cause the state machine to add a value
which alternates between +1 and -1 every clock. (This value is to be added only if the
incoming bit is a 1). This sum should be maintained modulo 3.