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Synopsys 2010
Today
IC Compiler 32/28nm Webinar Series
Done
Done
Done
Done
Done
Manufacturing-Aware
Routing
Done
Extraction For
32/28nm
Todays Topic
Synopsys 2010
Welcome!
JC Lin
Vice President, R&D
IC Compiler
Synopsys
Synopsys 2010
Synopsys 2010
Enhanced Manufacturing
Compliance
Routing, Physical
Verification & Test
PrimeTime/StarRC
IC Validator
Galaxy
Design
Compiler
Low Power
Comprehensive flow
Major advances in
2010.03 and 2010.12
Design Complexity
IC
Compiler
Runtime speedup
40M+ design handling
100
90
80
70
60
50
40
30
20
10
Q2'10
Q1'10
Q4'09
Q3'09
Q2'09
Q1'09
Q4'08
Q3'08
Q2'08
Q1'08
Q4'07
Q3'07
Q2'07
Q1'07
Q4'06
Q3'06
Q2'06
Q1'06
Q4'05
Driver
Model
Reduced Order
Network Model
Advanced OCV
Receiver
Model
U
2
Current vectors
0.7
0.5
0.2
0.1
U3
U1
U4
output
cap
Synopsys 2010
NLDM
CCS
Elmore
Arnoldi
NLDM
CCS
Depth
Derate
1.2
1.2
1.15
1.15
1.08
1.08
1-core
4-core
Design
Compiler
Design
Planning
Placement
3
2
CTS
FCLK
TCLK
MCMM
New: MCMM
CTS/CTO
RTL to Layout
Multi-Voltage
Multicore Support
Routing
0
2009.06
2010.03
2010.12
Comprehensive MCMM support - faster TAT, best QoR and easy to use
Synopsys 2010
In-Design PrimeRail
IC Compiler Integration
User provided
X-Y padding
Manufacturing
Error Browser
identified missing via
Y
Before EM-Aware CTS
Based on guidance
IC Compiler adds in the
missing via
Clock cell
Logic cell
Logic cell
Clock cell
Improved
Productivity - UPF
Multi-voltage
Aware Opt.
Top
RTL
Mid
UPF
Bot
Design Compiler
Gate
Logic View
UPF
AO (VA)
IC Compiler
AO (VA)
Gate
Gate (PG)
UPF
Physical View
Synopsys 2010
10
SD PD
data[0:7]
0
clock
dly[0:7]
I
C
G
Datapath ICG
placement & routing
~30% less power
Synopsys 2010
11
Power (mW)
120
In-Design STA
20%
ICC Only MCMM
140
Physical Flow
DCG+ICC
MCMM
%Improvement
18%
16%
Place Opt
14%
12%
100
10%
80
8%
60
Clock Opt
6%
40
4%
20
2%
Route Opt
0%
Final-stage
Leakage Recovery
Customer Designs
Delivers Maximum
Leakage Savings
Synopsys 2010
12
Faster
Global Route
Virtual IPO
fanout
43
32
VIPO
43
32
plangroup
1
plangroup 2
47
Coarser placement no legalization
25M instances in 1 hour
budgeted
output delay
Synopsys 2010
13
Feasibility Flow
Faster & Easy To Debug
Categorized
Reports
Feasibility
Optimization
Timing Histogram
(baseline, feasibility)
Infeasible
paths
Optimization on
feasible paths
masked
User customizable
What Next recommendations
14
Top-level
Designers View
Original
netlist
1.8M Cells
On-demand
netlist
50K Cells
Synopsys 2010
15
Routing Rules
2x
Soft Rules
Yield
1x
Standard Cell
Filler Cell
Yield vs.
spacing plot
Synopsys 2010
16
H S Spacing
Manufacturing
Compliant
Multicore Delivers
3X Speed-up
Dynamic Maze
Grid
Multi-threaded
Dynamic
Grid
Virtual
Wire
Redundant Vias
Advanced Design
Rules
0.6S
Polygon Manager
X Y
0.6S
S
Z
S
# of Cores
Synopsys 2010
17
Auto-Repair
Timing-Aware
Signoff Quality
10x Faster
Incremental
Highest Density
Synopsys 2010
18
In-Design LCC
Automatic
litho-repair using
pattern matching
Synopsys 2010
19
20
OUT
A1
A1
OUT
A1
A2
A2
A2
A3
A3
A3
21
OUT
Before
After
300
62%
Less
200
48%
Less
100
0
40nm
864K cells
4 Vth
BC/WC
32nm
2M cells
7 Vth
4 scenarios
22
Synopsys 2010
23
Wavelength
Size (um)
3.0
0.436
0.1
2000
10
Complex Feature
Dependencies
DRC-clean
1500
2.0
Number of Rules
0.6
0.365
0.35
1000
0.193
0.18
65nm
0.01
500
Litho
Hotspot
32nm
0
350 250 180 150 130 90 65 45 32
24
Prevent
Match
IC Compiler (ICC)
IC Validator (ICV)
Repair
ICC+ICV
Automatic repair and
revalidation of
matched layout
patterns
25
In-Design PV Pattern-Matching
Match
Database-Driven
Pattern Matching
100K
10K
1K
100
30
25
20
15
10
5
0
10
Intelligent
Layout Filtering
Runtime (min)
Automated
Pattern Capture
Num Patterns
Fast Identification of
Match Candidates
26
Repair
Highly Localized
Router-Driven
Incremental Validation
27
1214
1200
800
90%
600
400
200
457
85%
187
54
13
80%
617k
966k
2.4M
Design Instances
1000
25
20
100
15
10
10
5
0
1
617K
966K
28
2.4M
Design Instances
Patterns in DB
# Patterns
95%
1000
Repair
30
100%
Repair Rate
# Litho Hotspots
1400
Detection
Repair Rate
Runtime (min)
Before
Fast Runtime
Manufacturing Compliance
Routing, Physical
Verification & Test
In-Design PV: Litho
Hotspot Prevention using
Pattern Matching
PrimeTime/StarRC
IC Validator
Galaxy
Design
Compiler
Low Power
Comprehensive flow
Low Power CTS
In-Design STA : Finalstage Leakage
Recovery
Design Complexity
IC
Compiler
Runtime speedup
40M+ design handling
29
Thank You!
IC Compiler 32/28nm Webinar Series
Synopsys 2010
Done
Done
Done
Done
Done
Manufacturing-Aware
Routing
Done
Extraction For
32/28nm
Done
30
Predictable Success
Synopsys 2010
31