Design-for-Test For Digital IC's and Embedded Core Systems: Figures To Accompany

Figures to Accompany
Design-for-Test
for Digital ICs and
Embedded Core Systems
Alfred L. Crouch
1999 Prentice Hall, All Rights Reserved
Contents
ii
Chapter 1 Test and Design-for-Test Fundamentals

Figure 1-1
Cost of Product
Figure 1-2
Concurrent Test Engineering
Figure 1-3
Why Test?
Figure 1-4
Definition of Testing
Figure 1-5
Measurement Criteria
Figure 1-6
Fault Modeling
Figure 1-7
Types of Testing
Figure 1-8
Manufacturing Test Load Board
Figure 1-9
Using ATE
Figure 1-10 Pin Timing
Figure 1-11 Test Program Components
Chapter 2 Automatic Test Pattern Generation Fundamentals
Figure 2-1
The Overall Pattern Generation Process
Figure 2-2
Why ATPG?
Figure 2-3
The ATPG Process
Figure 2-4
Combinational Stuck-At Fault
Figure 2-5
The Delay Fault
Figure 2-6
The Current Fault
Figure 2-7
Stuck-At Fault Effective Circuit
Figure 2-8
Fault Masking
Figure 2-9
Fault Equivalence Example
Figure 2-10 Stuck-At Fault ATPG
Figure 2-11 Transition Delay Fault ATPG
Figure 2-12 Path Delay Fault ATPG
Figure 2-13 Current Fault ATPG
Figure 2-14 Two-Time-Frame ATPG
Figure 2-15 Fault Simulation example
Figure 2-16 Vector Compression and Compaction
Figure 2-17 Some Example Design Rules for ATPG Support
Figure 2-18 ATPG Measurables
Chapter 3 Scan Architectures and Techniques
Figure 3-1
Introduction to Scan-based Testing
Figure 3-2
An Example Non-Scan Circuit
Design-for-Test for Digital ICs and Embedded Core Systems

Alfred L. Crouch
Contents
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 3-18
Figure 3-19
Figure 3-20
Figure 3-21
Figure 3-22
Figure 3-23
Figure 3-24
Figure 3-25
Figure 3-26
Figure 3-27
Figure 3-28
iii
Scan Effective Circuit

Flip-Flop versus Scan Flip-Flop
Example Set-Scan Flip-Flops
An Example Scan Circuit with a Scan Chain
Scan Element Operations
Example Scan Test Sequencing
Example Scan Testing Timing
Safe Scan Shifting
Safe Scan Vectors
Partial Scan
Multiple Scan Chains
The Borrowed Scan Interface
Clocking and Scan
Scan-Based Design Rules
DC Scan Insertion
Stuck-At Scan Diagnostics
At-Speed Scan Goals
At-Speed Scan Testing
At-Speed Scan Architecture
At-Speed Scan Interface
Multiple Scan and Timing Domains
Clock Skew and Scan Insertion
Scan Insertion for At-Speed Scan
Critical Paths for At-Speed Testing
Logic BIST
Scan Test Fundamentals Summary
Chapter 4 Memory Test Architectures and Techniques

Figure 4-1
Introduction to Memory Testing
Figure 4-2
Memory Types
Figure 4-3
Simple Memory Organization
Figure 4-4
Memory Design Concerns
Figure 4-5
Memory Integration Concerns
Figure 4-6
Embedded Memory Test Methods
Figure 4-7
Simple Memory Model
Figure 4-8
Bit-Cell and Array Stuck-At Faults

Alfred L. Crouch
Contents
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 4-17
Figure 4-18
Figure 4-19
Figure 4-20
Figure 4-21
Figure 4-22
Figure 4-23
Figure 4-24
Figure 4-25
Figure 4-26
Figure 4-27
Figure 4-28
iv
Array Bridging Faults

Decode Faults
Data Retention Faults
Memory Bit Mapping
Algorithmic Test Generation
Scan Boundaries
Memory Modeling
Black Box Boundaries
Memory Transparency
The Fake Word Technique
Memory Test Needs
Memory BIST Requirements
An Example Memory BIST
MBIST Integration Issues
MBIST Default Values
Banked Operation
LFSR-Based Memory BIST
Shift-Based Memory BIST
ROM BIST
Memory Test Summary
Chapter 5 Embedded Core Test Fundamentals

Figure 5-1
Introduction to Embedded Core Test and Test Integration
Figure 5-2
What is a CORE?
Figure 5-3
Chip Designed with Core
Figure 5-4
Reuse Core Deliverables
Figure 5-5
Core DFT Issues
Figure 5-6
Core Development DFT Considerations
Figure 5-7
DFT Core Interface Considerations
Figure 5-8
DFT Core Interface Concerns
Figure 5-9
DFT Core Interface Considerations
Figure 5-10 Registered Isolation Test Wrapper
Figure 5-11 Slice Isolation Test Wrapper
Figure 5-12 Slice Isolation Test Wrapper Cell
Figure 5-13 Core DFT Connections through the Test Wrapper
Figure 5-14 Core DFT Connections with Test Mode Gating

Alfred L. Crouch
Contents
Figure 5-15
Figure 5-16
Figure 5-17
Figure 5-18
Figure 5-19
Figure 5-20
Figure 5-21
Figure 5-22
Figure 5-23
Figure 5-24
Figure 5-25
Figure 5-26
Figure 5-27
Other Core Interface Signal Concerns

DFT Core Interface Frequency Considerations
A Reuse Embedded Cores DFT Features
Core Test Economics
Chip with Core Test Architecture
Isolated Scan-Based Core-Testing
Scan Testing the Non-Core Logic
Scan Testing the Non-Core Logic
Memory Testing the Device
DFT Integration Architecture
Test Program Components
Selecting or Receiving a Core
Embedded Core DFT Summary

Alfred L. Crouch
Total
Cost
Testing
Cost
Packaging
Cost
Silicon
Cost
Initial
Product
Increasing
Time
Final
Product
The goal over time is to reduce the cost of manufacturing

the product by reducing the per-part recurring costs:
- reduction of silicon cost by increasing volume and yield,
and by die size reduction (process shrinks or more
efficient layout)
- reduction of packaging cost by increasing volume,
shifting to lower cost packages if possible (e.g., from
ceramic to plastic), or reduction in package pin count
- reduction in cost of test by:
- reducing the vector data size
- reducing the tester sequencing complexity
- reducing the cost of the tester
- reducing test time
- simplifying the test program
Figure 1-1 Cost of Product

Alfred L. Crouch
Behavioral Specification and Model

Functional Architecture
Development
Test Architecture
Development
Test Control
Test Interface
BIST HDL
JTAG HDL
Hardware Description Language

Register Transfer Level
Timing Constraints
Gate-Level Library Mapping

Scan Insertion
Gate-Level Synthesis
Insert
Scan Cells
Scan Signals
Scan Ports
Test Timing
Gate-Level Netlist
Static Timing Assessment
Physical Process Mapping

Scan Optimization
Algorithmic
Scan Signal
ReOrdering
FloorPlanning and
Place&Route
Macrocell FloorPlanning
Timing Driven Cell Placement
Timing Driven Routing
Clock Tree Synthesis
Figure 1-2 Concurrent Test Engineering

Alfred L. Crouch
WHY TEST?
Reasons
Measurement
of Defects &
Quality Level
Incoming
Inspection
Contractual
Perceived
Product Quality
by Customer
Reliability
Requirement
Contractual
Pro & Con Perceptions of DFT

Eases
Generation of
Vectors
Adds Complexity
to Design
Methodology
Eases
Diagnosis
& Debugging
Impacts
Design Power
& Package Pins
Provides a
Deterministic
Quality Metric
Impacts
Design Speed or
Performance
Reduces
the Cost
of Test
Adds to
Silicon
Area
Figure 1-3 Why Test?

Alfred L. Crouch
DEFINITION of TESTING
Device or Circuit
under test
DEVICE
IN A
KNOWN
STATE
A KNOWN
STIMULUS
A KNOWN
EXPECTED
RESPONSE
EXAMPLE
IN_A
IN_B
IN_C
D Q
CLK
1
S
D Q
OUT_1
IN_D
OUT_2
b
Broadside
Parallel
Vector
1
1
^
1
CLK
with an unknown state
1
^
X
^
1
X
1
X
1
?
?
Figure 1-4 Definition of Testing

Alfred L. Crouch
Vdd
S
physical defects
opens
shorts
metal bridges
process errors
source-to-drain
short
G
D is always
at a logic 1
D
S
G
transistor faults
S2 D
G2 D
S2 G
G2 SB
S 2 SB D2 SB
D
Vss
gate faults
a@ 0 a@ 1
b@ 0 b@ 1
c@ 0 c@ 1
C
observed truth table
A
B
C
failures
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
0
Transistor and Gate Representation of Defects, Faults, and Failures

Figure 1-5 Measurement Criteria

Alfred L. Crouch
defects
open/short
bridge
mask
process
transistor faults
s2 d
g2 d
s2 g
g 2 sb
s 2 sb d 2 sb
stuck faults
a@ 0 a@ 1
b@ 0 b@ 1
c@ 0 c@ 1
6 gate faults
transition
delay faults
a 1- 0 a 0- 1
b1- 0 b0- 1
c 1- 0 c 0- 1
+
g
s
d
Truth Table
with fail modes
nand ab a b c
ab c 0 1 1 0
00 1 1 1 1 0
01 1 1 0 1 0
10 1 1 1 0 0
11 0 1 0 0 0
6 transitions
a
e
b
c
1 BIT ADDER with CARRY
Figure 1-6 Fault Modeling

path
delay faults
A2SR A2SF
A2CR A2CF
B2SR B2SF
B2CR B2CF
path
R=Slow-to-Rise
F=Slow-to-Fall
Alfred L. Crouch
Functional
3 a
A
D
D
E
R
3+5=8
Structural
A
a
e
f
r
s
b
c
faultlist
a@ 0 a@
b@ 0 b@
e@ 0 e@
f@ 0 f@
r@ 0 r@
t@ 0 t@
s@ 0 s@
c@ 0 c@
1
1
1
1
1
1
1
1
16 faults
Figure 1-7 Types of Testing

Alfred L. Crouch
Chip
under
Test
The chip will be accessed by the tester at its pins only

A custom (load) board will be made for this purpose
Each pin has a limited number of bits available (e.g., 2 MB)
The test program (set of vectors and tester control) will be
applied at tester speed (may be less than actual chip speed)
The primary goal of manufacturing test is structural verification
Figure 1-8 Manufacturing Test Load Board

Alfred L. Crouch
2 Meg
Memory
Depth
Clock Gen 1
Clock Gen 2
Clock Gen 3
hi
pS
o
ck
et
192
Channels
Loadboard
Power Supply 1
Power Supply 2
Power Supply 3
Figure 1-9 Using ATE

Alfred L. Crouch
10
Chip Point of View
1 2
DV 4
1. Input Setup Time:
time the signal must arrive

and be stable before the clock
edge to ensure capture
2. Input Hold Time:
time the signal must remain

stable after the clock edge
to ensure that capture is stable
3. Output Valid Time:
time the signal takes to be

valid (or tristated) and stable on
the output after the clock edge
4. Output Hold Time:
time that the signal remains

available after output valid
so that it can be used
Tester Point of View

CLK
NRZ
RZ
SBC
Figure 1-10 Pin Timing

Alfred L. Crouch
11
DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-At
DC Logic Retention
AC Logic Delay
AC Frequency Assessment
AC Pin Specification
Memory Testing
Memory Retention
Idd and Iddq
Specialty Vectors
Analog Functions
Test Escapes
The Venn circles are

examples of DC fault
coverages of some of the
vector classifications
in the test program
Some of the fault
coverages overlap
Vector reduction can
be accomplished by
removing overlap or
by combining vector
sets
Scan
Path Delay
Scan
Transition
Delay
Scan
Stuck-At
Scan
Sequential
Parametric
Functional
Test Escapes

Alfred L. Crouch
Library Support
Netlist Conditioning
Observe Point Assessment
Vector Generation/Simulation
Vector Compression
Vector Writing
Figure 2-1 The Overall Pattern Generation Process

Alfred L. Crouch
WHY ATPG?
Reasons
Greater
Measurement
Ability
Reduction
in Cycle
Time
Perceived
Competitive
Methodology
More
Efficient
Vectors
Pro & Con Perceptions of ATPG

Good
Bad
Eases
Generation of
Vectors
Adds Complexity
to Design
Methodology
Eases
Diagnosis
& Debugging
Requires
Design-for-Test
Analysis
Provides a
Deterministic
Quality Metric
Requires
Library
Support
Reduces
the Cost
of Test
Requires
Tool
Support
Figure 2-2 Why ATPG?

Alfred L. Crouch
Fault Selection
Fault Observe Point Assessment
Fault Excitation
Vector Generation
Fault Simulation
Fault Dropping
Figure 2-3 The ATPG Process

Alfred L. Crouch
a
X
b
e
stuck-at-0
force to a 1
detected
good = faulty
d
1
GOOD CIRCUIT
1
D
I
F
F
E
R
E
N
T
FAULTY CIRCUIT
Figure 2-4 Combinational Stuck-At Fault

Alfred L. Crouch
Delay from Strong Driver

Insufficient Transistor Doping
Delay Model Element
B
Resistive Bridge
C
Delay from Extra Load
Slow Gate Output

Slow Gate Input
E
F
Capacitive or Resistive
Wire Delay from Opens
and Metal Defects
The Delay Fault Model
is an added delay
to net, nodes, wires, gates
and other circuit elements
Effect of Delay Fault
Delay of Transition Occurrence
Changing of Edge-Rate
Edge-Rate Layover
Ideal Signal
1
0
Added Rise Delay
Added Fall Delay
Figure 2-5 The Delay Fault

Alfred L. Crouch
Leakage from Bridge

Leakage from Metastability
Leakage Fault Model
B
Resistive Bridge
C
Leakage from Bridge
Internal Gate Leakage
E
F
Capacitive or Resistive
Delay Extends Current
Flow Time
The Current Fault Model

is an added Leakage
to net, nodes, wires, gates
and other circuit elements
Effect of a Current Fault

is to add extra current
flow or to extend flow time
I(t)
t
Figure 2-6 The Current Fault

Alfred L. Crouch
a
b
nand
ab z
00 1
01 1
10 1
11 0
X
stuck-at-0
force to a 1
c
d
evaluate fault against

the gates truth table
R
E
M
A
P
nor
ab z
00 1
01 0
10 0
11 0
c
e
d
evaluate change against

the gates truth table
R
E
M
A
P
Detectable
evaluate final result against

the circuits whole truth table
Figure 2-7 Stuck-At Fault Effective Circuit

Alfred L. Crouch
stuck-at-0
force to a 1
b
e
not detected
good = faulty
c
1
GOOD CIRCUIT
S
A
M
E
FAULTY CIRCUIT
Figure 2-8 Fault Masking

Alfred L. Crouch
faultlist
a@ 0 a@
b@ 0 b@
e@ 0 e@
f@ 0 f@
r@ 0 r@
t@ 0 t@
s@ 0 s@
c@ 0 c@
a
e
f
b
a
r
r
t
t
GOOD - 1 BIT ADDER with CARRY
a
b
a
a
z
z
z
b
Fault Equivalence Table
AND
a@0 = b@0 = z@0
INV
a@1 = z@0 : a@0 = z@1
OR
a@1 = b@1 = z@1
1
1
1
1
1
1
1
1
16 faults
1. Any fault that

requires a logic 1 on
the output of an
AND-gate will also
place 1s on inputs
2. Similar analysis
exists for all other
gate-level elements
3. If one fault is
detected, all
equivalent faults are
detected
4. Fault selection only
needs to target one
of the equivalent
faults
Figure 2-9 Fault Equivalence Example

Alfred L. Crouch
A 1
eX
f
B
r
1
0
b
c

Set Up the Detect and Propagation Path
10
faultlist
a@ 0
a@
b@ 0
b@
e@ 0
e@
f@ 0
f@
r@ 0
r@
t@ 0
t@
s@ 0
s@
c@ 0
c@
1
1
1
1
1
1
1
1
16 faults
1. Set up the path to

pass the opposite of
e S @ 0, which is e = 1
2. Exercise by setting
e equal to1
a
e
f
B 0
r
s
3. Detect by observing
S for wrong value
during fault
simulation
b
c

Exercise the Fault
Figure 2-10 Stuck-At Fault ATPG

Alfred L. Crouch
A 1
a 1
eX
f 0
r
t
1
1
0
faultlist
a@ 0
a@
b@ 0
b@
e@ 0
e@
f@ 0
f@
r@ 0
r@
t@ 0
t@
s@ 0
s@
c@ 0
c@
b
c
a
e 0
f
B 1
r
t
1. Set up the path to

pass the opposite of e
S=0 S @ 0, which is e = 1
S@Time 1
2. Pre-fail by setting
e equal to 0
b
c

Pre-Fail the Fault by Passing a 0
f
B 0
r
1
3. Exercise by setting
e equal to 1 some
time period later
4. Detect by observing
S for wrong value
during timing
simulation
a
e 1
1
1
1
1
1
1
1
1
16 faults
Set Up the Detect Path to Pass a 1
11
S@Time 2
b
c
S=1
The Transition Delay
Faultlist is identical to
the Stuck-At Faultlist but
the goal is to detect a
Logic Transition within
C a given time period

Exercise the Fault to Pass a 1
Figure 2-11 Transition Delay Fault

Alfred L. Crouch
1->1
eX
f
1->1
x->x b
X
0->0
16.0 pt
0->1
r
0->1
s
0->1
16 faults
S@Time1 -> S@Time2
1
1
1
1
1
1
1
1
2. Exercise by first setting

B equal to 1 and then
to 0. This is known as a
vector-pair
a
1->0
faultlist
a@ 0
a@
b@ 0
b@
e@ 0
e@
f@ 0
f@
r@ 0
r@
t@ 0
t@
s@ 0
s@
c@ 0
c@
1. Set up the path to pass

a transition on B-to-S
through e, r, and s by
setting the off-path
values to be stable for
2 time periods

Set Up the Off-Path
12
1->0
1. Detect by observing S
for wrong value during
fault simulation with
respect to a time
C standard

Exercise the Fault (Path)
Figure 2-12 Path Delay Fault

Alfred L. Crouch
faultlist
a@ 0
a@
b@ 0
b@
e@ 0
e@
f@ 0
f@
r@ 0
r@
t@ 0
t@
s@ 0
s@
c@ 0
c@
13
1
1
1
1
1
1
1
1
16 faults
a
e
f
B 0
1. Exercise by first
setting e equal to1
1
r
s
t
S
2. Detect by measuring
current and accept
vector by quietness
b
c

Exercise the Fault
Figure 2-13 Current Fault

Alfred L. Crouch
14
Transition
bit
End of Path
bit
1->0
1
second-order
cone of logic
0
0
establishes
transition and
off-path values
establishes
the legal
next-state
Defined
Critical
Path
1->1
Solve This Combinational

Cone of Logic As Second Step
after Middle Register Values
Are Established by First Cone
D Expect
Value
0->0
first-order
combinational
cone of logic
1->1
contains path
and off-path
logic
establish
first state
preset
next-state
Gate
Elements
legal
next-next-state
legal
next-state
Solve This Combinational

Cone of Logic As the First Step
to Combinational Multiple
Time Frame Analysis
Slack Time
Propagation Delay Time
Register Setup Time
1. Launch 1st Value:
establish path fail value at clock edge
2. Launch Transition:
provide pass value at next clock edge
3. Capture Transition:
observe transition value at this clock edge
Figure 2-14 Two-Time-Frame ATPG

Alfred L. Crouch
15
faultlist
a@ 0 a@
b@ 0 b@
e@ 0 e@
f@ 0 f@
r@ 0 r@
t@ 0 t@
s@ 0 s@
c@ 0 c@
a
e
b
c
GOOD - 1 BIT ADDER with CARRY
16 faults
a
e
GND
t S@0 - 1 BIT ADDER with CARRY
a
e
b
+
1. Create multiple
copies of the netlist
for each fault.
2. Apply same
vectors to each
copy.
1
1
1
1
1
1
1
1
VDD
t S@1 - 1 BIT ADDER with CARRY
3. Compare each
copy to good
simulation
(expected
response).
4. Fault is detected if
bad circuit and
good circuit differ
at a detect point.
5. Measurement is
faults detected
divided by total
number of faults
(8/16 = 50%).
Figure 2-15 Fault Simulation example

Alfred L. Crouch
16
Simulation Post Processing Compression

Pattern Set
Fault Re-Simulation
with Redundant
Vector Dropping
01101110001010
01101110101110
00101110111010
11111110001010
01100000001011
01001011001010
01010101010101
11101100101010
11001110001010
01111000001010
00000000001010
This Usually Drops

Early Vectors That
Are Fully Covered
by Later Vectors
and Eliminates Less
Efficient Vectors
Dynamic ATPG Compression
X
X
1
0
1
0
X
X
X
X
X
one targeted
fault
During ATPG a Vector Is Not

Submitted to Fault Simulation
until Multiple Faults have
been Targeted Xs Mapped
This can Greatly Increase
Vector Generation Time
But Usually Results in
the Most Efficient Vectors
Figure 2-16 Vector Compression and Compaction

Alfred L. Crouch
17
Transistor
Structure
Equivalent
Gate
Structure
ATPG May Only Operate

on Gate-level Elements
Combinational Feedback Results in

Latches, Oscillators, or Endless Loops
Propagation Timing Distance Must Be Less

Than One Test Clock Cycle
SET
D Q
General
Combinational
Logic
CLK
CLR
D Q
CLK
Figure 2-17 Some Example Design Rules for ATPG

Alfred L. Crouch
Sizing
Design
Description
Complexity
ATPG
Library
Faultlist
Management
Support
Files
18
ATPG
TOOL
Runscripts
Runtime
algorithms
rule checks
Vectors
Vector Features
Compression
Detected
Faults
Vector
Translation
Figure 2-18 ATPG Measurables

Alfred L. Crouch
- >1,000,000 gates
- >5,000,000 faults
- >10,000 flip-flops
- > 1,000 sequential depth
- < 500 chip pins
* > 2,000 gates/pin
* > 2M = 21000
A deep sequential circuit
Chip under Test without Scan
- >1,000,000 gates
- >5,000,000 faults
- > no effective flip-flops
- > no sequential depth
- < 500 + 10,000 chip pins
* > 95.23 gates/pin
* > 2M = 20 = 1
A combinational circuit
Chip under Test with Full-Scan
Figure 3-1 Introduction to Scan-based Testing

Alfred L. Crouch
Combinational &
Sequential Logic
input1
input2
input3
input4
output1
Q
QN
clk
input5
input6
output2
34
Sequential Depth of 4
Combinational Width of 6
26+4 = 1024 Vectors
Figure 3-2 An Example Non-Scan Circuit

Alfred L. Crouch
Combinational-Only Logic
input1
input2
input3
input4
output1
D
Q
QN
D
input5
input6
output2
TPI1
TPI2
TPI3
TPI4
TPI5
A no-clock, combinational-only circuit with:

6 inputs plus 5 pseudo-inputs and
TPO1
TPO2
TPO3
TPO4
2 outputs plus 4 pseudo-outputs
Figure 3-3 Scan Effective Circuit

Alfred L. Crouch
QN
CLK
clk
Regular D Flip-Flop
SDO
D
D
SDI
SE
Q
SDO
clk
QN
CLK
Scannable D Flip-Flop
Figure 3-4 Flip-Flop versus Scan Flip-Flop

Alfred L. Crouch
SET
D
SDO
D
SDI
QN
SE
clk
CLK
Set-Scan D Flip-Flop
with Set at Higher Priority
D
SET
SDI
SE
SDO
Q
QN
clk
CLK
Set-Scan D Flip-Flop
with Scan-Shift at Higher Priority
Figure 3-5 Example Set-Scan Flip-Flops

Alfred L. Crouch
Combinational and
Sequential Logic
input1
input2
output1
input3
input4
SE
SE
scanin
SDI
clk
QN
D
SDO
SE
input5
SDI
input6
SE
SE
SDI
SDI
scanout
output2
SDO
SDO
SDO
4-Bit Scan Vector
Figure 3-6 An Example Scan Circuit with a Scan Chain

Alfred L. Crouch
a
D
SDI
QN
SE
clk
SDO
CLK
Scannable D Flip-Flop
The scan cell provides observability and controllability of the signal

path by conducting the four transfer functions of a scan element.
Operate: D to Q through port a of the input multiplexer:
allows normal transparent operation of the element.
Scan Sample: D to SDO through port a of the input multiplexer:
gives observability of logic that fans into the scan element.
Scan Load/Shift: SDI to SDO through the b port of the multiplexer:
used to serially load/shift data into the scan chain while simultaneously
unloading the last sample.
Scan Data Apply: SDI to Q through the b port of the multiplexer:
allows the scan element to control the value of the output, thereby
controlling the logic driven by Q.
Figure 3-7 Scan Element Operations

Alfred L. Crouch
From normal operation:

D
SDI
SE=0
Q
QN
clk
SDO
CLK
Apply clocks for scan length

D
SDI
SE=1
Q
QN
SDO
clk
Scan Shift Load/Unload Mode
SDI
Q
QN
SE=1
clk
SDO
Scan Apply Mode (Last Shift)
The next rising edge of the clock

will sample D
NOTE: unloading is simultaneous

with loading the next test
D
SDI
SE=0
Normal circuit response will be

applied to D
Return to Load/Shift mode to

unload circuit response sample
CLK
When chain is loaded, the last

shift clock will apply scan data
While the clock is low,
place SE = 0
CLK
While the clock is low,

apply test data to SDI
and Place SE = 1
At the rising edge of the clock,
test data will be loaded
Functional Operation Mode
Q
QN
clk
SDO
CLK
Scan Sample Mode
Repeat operations until all vectors

have been applied
NOTE: the chips primary inputs
must be applied during the scan
apply mode (after the last shift)
Figure 3-8 Example Scan Test Sequencing

Alfred L. Crouch
The Scan Sample

The Last Shift In
The First Shift Out
CLK
SE
Scan Enable Assert
Scan Enable De-assert
The Output Pin Strobe

SHIFT
DATA
SHIFT
DATA
FAULT
EXERCISE
SAMPLE
DATA
SHIFT
DATA
SHIFT
DATA
Faults Exercised Interval
Figure 3-9 Example Scan Testing Timing

Alfred L. Crouch
Gated Clock Nets
10
clock tree
distribution
Provide an Enable Signal

f_seB
force the clock on
Asynchronous or Synchronous
Signals with Higher Priority
than Scanor Non-Scan Elements
D
Q
HOLD
SET
CLR
f_seB
CLK
Provide a Blocking Signal
D
Q
HOLD
SET
CLR
CLK
Driven Contention
During Scan Shifting
D Q
Q D
CLK
CLK
D Q
Q D
CLK
t_seB
Provide a Forced Mutual Exclusivity
CLK
Figure 3-10 Safe Scan Shifting

Alfred L. Crouch
11
The Scan Sample

The Last Shift In
The First Shift Out
CLK

SE
t_seB
a tristate scan enable may be

a separate signal that has
slightly different timing than
the flip-flop SE
Driven Contention
during the Capture Cycle
D Q
Q D
CLK
CLK
D Q
Q D
CLK
t_seB
de-asserted
CLK
Figure 3-11 Safe Scan Vectors

Alfred L. Crouch
12
Combinational-Only Logic
input1
input2
input3
input4
output1
D
Q
QN
D
input5
input6
output2
TPI1
TPI2
TPO1
TPI3
TPI5
A clocked, sequential circuit with depth=1:

6 inputs plus 4 pseudo-inputs and
2 outputs plus 3 pseudo-outputs
TPO3
TPO4
Figure 3-12 Partial Scan

Alfred L. Crouch
13
An Example Using a Chip with 1000 Scan Bits and 5 Scan Vectors
Red Space Is Wasted Tester Memory
1000
1000
One Long
Scan Chain
1000
Vector Data
One Channel
1000
Xs on all Other Channels

not actively used for parallel pin data
Each Vector is 1000 Bits Long

So 5 Vectors Are 5000 Bits of Tester Memory
Many
Variable Length
Scan Chains
120
X
80 XXX
100 XX
110 XX
90 XXX
180
X20 XXXX
100 XX
100 XX
100 XX
120
X
80 XXX
100 XX
110 XX
90 XXX
180
X20 XXXX
100 XX
100 XX
100 XX
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
120
X
80 XXX
100 XX
110 XX
90 XXX
180
X 20 XXXX
100 XX
100 XX
100 XX
120
X
80 XXX
100 XX
110 XX
90 XXX
180
X 20 XXXX
100 XX
100 XX
100 XX
10 Non-Balanced
Channels
Each Vector Is 180 Bits LongSo 900 Bits of Tester Memory

Differences from Longest Chain (180) Are Full of XsWasted Memory
Many
Balanced
Scan Chains
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
Vector Data
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
10 Balanced
Channels
Each Vector Is 100 Bits LongSo 500 Bits of Tester Memory

No Wasted Memory Space
Figure 3-13 Multiple Scan Chains

Alfred L. Crouch
14
Borrowed DC Scan Input on Bidirectional Pin

Combinational
Logic
Scan
Data
Input
Output Data Path

Blocked during Scan Shift
Output Enable
with bus_se
Captures through the
or scan_mode
Combinational Logic
during the Sample Operation
Combinational
Logic
Any
Bidir
Functional
Pin
D
S
SE
Pad
Captures Directly from

the Input Pin During
the Shift Operation
Q
Input
Parallel Scan
Input to Chip
Normal Input
to Logic
SE
Input Scan InterfaceMay Resolve to Functional during Sample Interval
Borrowed DC Scan Output on Bidirectional Pin

Last Scan Shift Bit
from Scan Chain
D
Q
Input
Normal Output
from Logic
D
S
SE
S
SE
Input Data Path Is a

Dont Care
during Scan Shift
SE on Input
Combinational
Blocks Data
Logic
Combinational
Logic
Output
a
b
s
Added Scan Output Mux with bus_se or scan_mode
Scan
Data
Output
Any
Bidir
Pin
Pad
Functional Output Enable with bus_se or scan_mode added
Output Scan InterfaceMay Resolve to Functional during Sample Interval

Figure 3-14 The Borrowed Scan Interface

Alfred L. Crouch
15
Scan Bypass Clocks

Scan Testing an On-Chip Clock Source
Bypass Clocks
Analog
Digital 1
Digital 2
VCO
Raw VCO
Clock
Counters &
Dividers
On-Chip Clock Generation Logic
Figure 3-15 Clocking and Scan

Alfred L. Crouch
16
Driven Contention
during Scan Shifting
D Q
Q D
CLK
CLK
D Q
Q D
CLK
CLK
t_seB
Provide a Forced Mutual Exclusivity
Asynchronous or Synchronous
Signals with Higher Priority
than Scanor Non-Scan Elements
D
Q
HOLD
SET
CLR
f_seB
CLK
D
Q
HOLD
SET
CLR
CLK
Gated Clock Nets

f_seB
Figure 3-16 Scan-Based Design Rules

Alfred L. Crouch
17
Basic Netlist Scan Insertion

Element Substitution
Ports, Routing & Connection of SE
Ports, Routing & Connection of SDI-SDO
Extras
Tristate Safe Shift Logic
Asynchronous Safe Shift Logic
Gated-Clock Safe Shift Logic
Multiple Scan Chains
Scan-Bit Re-Ordering
Clock Considerations
All Non-Sampling
Clock Domains
Inhibit Sample
Clock Pulse
Last Shift
All Scan Chains (Clocks) Shift
Only One Clock Domain

Conducts a Sample Clock
Figure 3-17 DC Scan Insertion

Alfred L. Crouch
18
Scan Fail Data Presented at

Chip Interface Automatically
Implicates the Cone of Logic
at One Flip-Flop
1
0
Multiple Fails under the

Single Fault Assumption
Implicate Gates
Common to Both
Cones of Logic
0
1
0
Figure 3-18 Stuck-At Scan Diagnostics

Alfred L. Crouch
19
Basic Purpose
Frequency Assessment
Pin Specifications
Delay Fault Content
Cost Drivers
No Functional Vectors
Fewer Overall Vectors
Deterministic Grade
Figure 3-19 At-Speed Scan Goals

Alfred L. Crouch
20
The Transition Launch

The First Shift Out
The Last Shift In
The Transition Capture
CLK
Transition Generation Interval
SE
T_SE
F_SE
Bus_SE
Separate Scan Enables for Tristate Drivers,

Clock Forcing Functions, Logic Forcing
Functions, Scan Interface Forcing Functions,
and the Scan Multiplexor Control
Because the Different Elements Have
Different Timing Requirements
Figure 3-20 At-Speed Scan Testing

Alfred L. Crouch
21
Borrowed Scan Input with Scan Head Register

Output Data Path Blocked during Scan Shift
Output Enable with bus_se
Combinational
Logic
Any
Bidir
Pin
D
Q
Input
Pad
Parallel Scan
Input to Chip
Normal Input
to Logic
D
S
SE
Q
Input
At-Speed Scan InterfaceResolves to Functional During Sample Interval
Driven Contention
During Scan Shifting
CLK
CLK
D
CLK
CLK
t_seB
At-Speed Assert and De-Assert
Asynchronous or Synchronous Signals

with Higher Priority than Scan
or Non-Scan Sequential Elements
D
HOLD
SET
CLR
CLK
HOLD
SET
CLR
f_seB
CLK
At-Speed Assert and De-Assert

Figure 3-21 At-Speed Scan Architecture

Alfred L. Crouch
22
Borrowed AC Scan Input on Bidirectional Pin

Combinational
Logic
Output Data Path

Blocked during Scan Shift
Output Enable
with at-speed bus_se
Scan
Data
Input
Captures through the

Combinational Logic
during the Sample Operation
Combinational
Logic
Any
Bidir
Functional
Pin
S
SE
Pad
Parallel Scan
Input to Chip
Normal Input
to Logic
D
Q
Input
Captures Directly from

the Input Pin During
the Shift Operation
D
Q
Input
Head
Input Scan InterfaceResolves to Functional during Sample Interval
Borrowed AC Scan Output on Bidirectional Pin

Last Scan Shift Bit
from Scan Chain
D
Q
Input
Normal Output
from Logic
D
S
SE
Q
Output
S
SE
Input Data Path Is a

Dont Care
during Scan Shift
SE on Input
Combinational
Blocks Data
Logic
Combinational
Logic
D
Q b
Output s
Tail
Added Scan Output Mux with bus_se
Scan
Data
Output
Any
Bidir
Pin
Pad
Functional Output Enable with bus_se Added
Output Scan InterfaceResolves to Functional During Sample Interval

Figure 3-22 At-Speed Scan Interface

Alfred L. Crouch
23
Fast to Slow
Transfers
Slow to Fast
Transfers
Fast
Logic
Slow
Logic
Fast to Slow
Transfers
Fast Scannable
System Registers
Slow Scannable
System Registers
Clock A
Scan Enable A
Clock B
Scan Enable B
The Clock Domains and Logic Timing

should be crafted so that the very next
rising edge after the launch or last shift
is the legal capture edge
Last Scan
Shift Edge
Legal ATPG
Transfer
Illegal ATPG
Transfer
Applied
Fast Clock
Applied
Slow Clock
Only Fast-to-Slow
Legal ATPG Transfer
Figure 3-23 Multiple Scan and Timing Domains

Alfred L. Crouch
24
Combinational
Logic
Combinational
Logic
Combinational
Logic
scanned
flip-flop
D
SDI
SDI
SDI
165 ps
CLK
120 ps
SE
150 ps
First Clock Domain All Elements on Same Clock Tree

300ps+
Cross Domain
Clock Skew
Combinational
Logic
Combinational
Logic
Combinational
Logic
scanned
flip-flop
SDI
SDI
SDI
165 ps
CLK
SE
120 ps
150 ps
Second Clock DomainAll Elements on Same Clock Tree

Cross Domain Clock Skew must be managed to less than the fastest
flip-flop update time in the launching clock domain
If it is not, then the receiving flip-flop may receive new-new
scan data before the capture clock arrives
To prevent this outcome, constrain the ATPG tool to only
sample one clock domain at a time during the sample interval
Figure 3-24 Clock Skew and Scan Insertion

Alfred L. Crouch
25
Specification
Development
Scan Mode
Bus_SE
Tristate_SE
Logic Force_SE
Architecture
Development
Simulation
Verification
Model
Behavior
Synthesis
Scan Shift SE
Clock Force_SE
Scan Data
Connection
Insertion
Timing
Analysis
Place
and
Route
Scan Chain Bit

Re-Ordering
Specification
Determination
Gates
Mask
Mask
and
Fab
Silicon
Test
Silicon
Design Flow Chart
Scan Mode: Fixed Safe Logic
Scan Enable (SE): Scan Shift
Force_SE:
Force_SE: Clock Force States
Logic Forced States
Tristate_SE: Internal Tristates
Bus_SE: Scan Interface Control
Figure 3-25 Scan Insertion for At-Speed Scan

Alfred L. Crouch
D Q
R1
D Q
R2
In1
0>1
A
U35
B
0
X
In2
0
In3
In4
0
A
U36
B
A
U39
B
26
Static Timing Analysis Provides Path Description

of Identified Critical Path from the Q-Output of R1
to the Device Output PinOut1
0>1
A
U37
B
1>0
A
U38
B
1>0
Out1
1
Isolated Combinational Logic
All Fan-in to Endpoint Is
Accounted at this Endpoint
Fanout to other Endpoints is
Evaluated atThose Endpoints
Period = 20ns : Output Strobe @ 15ns

Path Element
Incremental
Cumulative
Description
Delay
Delay
Clk
R1.Q
U35.A
U35.Z
U37.A
U37.Z
U38.A
U38.Z
Out1
2.2ns
0.0ns
2.1ns
0.1ns
3.2ns
0.2ns
2.2ns
0.1ns
Dly=10.1
Skew Amb.
0.0ns
2.1ns
2.2ns
5.4ns
5.6ns
7.8ns
7.9ns
Slk=4.9ns
Timing Analysis Report

Figure 3-26 Critical Paths for At-Speed Testing

Alfred L. Crouch
27
Polynomial: X3 + X +1 = X3 + X1 + X0 = 23 + 21 + 20 = 11
LFSR - PRPG: pseudo-random pattern generation
X3
Seed
DQ
1
X2
DQ
1
X1
DQ
1
CLK
X0
111
011
001
100
010
101
110
111
Chip with Full-Scan

and X-Management
DQ
DQ
DQ
CLK
LFSR - MISR: multiple input signature register
Figure 3-27 Logic BIST

Alfred L. Crouch
28
Scan Testing Methodology

Advantages
Direct Observability of Internal Nodes
Direct Controllability of Internal Nodes
Enables Combinational ATPG
More Efficient Vectors
Higher Potential Fault Coverage
Deterministic Quality Metric
Efficient Diagnostic Capability
AC and DC Compliance
Concerns
Safe Shifting
Safe Sampling
Power Consumption
Clock Skew
Design Rule Impact on Budgets
Figure 3-28 Scan Test Fundamentals Summary

Alfred L. Crouch
Chip-Level
Embedded
Memory
Logic
Memory Access
PLL
TAP
JTAG Boundary Scan
Figure 4-1 Introduction to Memory Testing

Alfred L. Crouch
Row/Word-Address
Select
Select
Column/Bit-Data
Column/Bit-Data
Storage
6 Transistor SRAM Cell

Row/Word-Address
Storage
Select
Column/Bit-Data
1 Transistor DRAM Cell

Row/Word-Address
Storage
Select
Column/Bit-Data
2 Transistor EEPROM Cell
Figure 4-2 Memory Types

Alfred L. Crouch
Data Bus: To Multiple Memory Arrays
Address Bus: To Multiple Memory Arrays
Bus
Enable
Data In
Data Out
Memory: Data Width by Address Depth
32 x 512
Address In
Read/WriteBar
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Output Enable
Control Circuitry to Read, Write,

and Data Output Enable
Control Signals: Individual Signals to This Memory Array
Figure 4-3 Simple Memory Organization

Alfred L. Crouch
Chip FloorPlan
Memory 1
M
e
m
o
r
y
3
Memory
2
- Aspect Ratio
- Access Time
- Power Dissipation
Memory 4
Figure 4-4 Memory Design Concerns

Alfred L. Crouch
Chip FloorPlan
Memory 1
M
e
m
o
r
y
Memory
2
- Routing
- Placement & Distribution

- Overall Power Dissipation
Processor
Local
Logic
Memory 4
Figure 4-5 Memory Integration Concerns

Alfred L. Crouch
32
Embedded
Microprocessor
Core
Data
24
Embedded
Memory
Array
Address
3
Control
Functional Memory Test
Data
Address
Control
32
Embedded
Memory
Array
24
3
Direct Access Memory Test
Invoke
BIST Controller
Done
Reset
Embedded
Memory
Array
Hold
Fail
BIST Memory Test
Figure 4-6 Embedded Memory Test Methods

Alfred L. Crouch
column # >
row # > 0
row # > 1
data bit cell
row # > 2
Figure 4-7 Simple Memory Model

Alfred L. Crouch
Data in Bit Cells

May Be Stuck-At
Logic 1 or Logic 0
word stuck-at
data value 1110
address A031>
address A032>
address A033>
single bit stuck-at 1
single bit stuck-at 0
Figure 4-8 Bit-Cell and Array Stuck-At Faults

Alfred L. Crouch
Data in Bit Cells

May Be Bridged
to Other Bit Cells
horizontal (row)
bit bridging
vertical (column)
bit bridging
word bridging
unidirectional
one-way short
random
bit bridging
word bridging
bidirectional
two-way short
Figure 4-9 Array Bridging Faults

Alfred L. Crouch
10
Column Decode
X
C
O
Select Lines
R
O
0
Row Decode
stuck-at faults result
in always choosing
wrong address
Row Decode
bridging faults result
in always selecting
multiple addresses
o
d
e
Column Decode
bridging faults result
in always selecting
multiple data bits
Column Decode
Select Line
stuck-at faults result
faults result in
in always choosing
similar array
wrong data bit
fault effects
Figure 4-10 Decode Faults

Alfred L. Crouch
11
Data around target

cell is written with
complement data
Complementary
Data around
Target Cell
Address 21 = A
Address 22 = 5
Address 23 = A
Address 24 = 5
alternating 5s and As make for a natural checkerboard pattern

Figure 4-11 Data Retention Faults

Alfred L. Crouch
Blue: Pass
Red: Fail
12
Column
Data Fault
Physical Memory Organization

Row Address
Fault
Logical Memory Organization

Stuck-At
Bit Faults

Bridged
Cell Faults

Figure 4-12 Memory Bit Mapping

Alfred L. Crouch
13
Address 00 >
Address 01 >
Address 02 >
Address 03 >
Addr(00) to Addr(Max)
Read(5)-Write(A)-Read(A) Address 04 >
Increment Address
Address 05 >
Address 06 >
Read(A)-Write(5)-Read(5) Address 07 >
Increment Address
Address 08 >
Address 09 >
Addr(Max) to Addr(00)
Read(5)-Write(A)-Read(A) Address 10 >
Decrement Address
Address 11 >
Address 12 >
Read(A)-Write(5)-Read(5) Address 13 >
Decrement Address
Address 14 >
Address 15 >
Address 16 >
Address 17 >
Address 18 >
Address 19 >
Address 20 >
Address 21 >
Address 22 >
Address 23 >
Write(5)-Initialize
Increment Address
Read(5)
Decrement Address
Read (A)------->
Write (5)
Read (5)
Increment Address
March C+ Algorithm
Memory Array with 24 Addresses

with Algorithm at Read (A) Stage
Figure 4-13 Algorithmic Test Generation

Alfred L. Crouch
14
Boundary at some level

of scanned registration
or pipelining away
from the memory
array
Data
Data
Memory
Detection of
incoming
signals
Control of
outgoing
signals
Array
Address
Control
scan-memory
boundary
Minimum Requirement
Detection up to Memory Input
and Control of Memory Output
Concern: the Logic between

the Scan Test Area and the
Memory Test Area Is not
Adequately Covered
Non-Scanned Registration inside the Boundary

but Before the Memory Test Area Results in
a Non-Overlap Zone
Figure 4-14 Scan Boundaries

Alfred L. Crouch
15
The Memory Array is modeled

for the ATPG Engine so the
ATPG Tool can use the memory
to observe the inputs
and control the outputs
Data In
Din
Dout
Data Out
Memory
Array
Address
Ain
ATPG
Model
Control
Read/Write
Scan
Architecture
Figure 4-15 Memory Modeling

Alfred L. Crouch
16

is blocked off
as if the memory was
cut out of the circuit
Scan Mode
Control of
outgoing
signals
Data In
Gated Data Out
Detection of
incoming
signals
Memory
Array
can be
Address
Multiplexed Data Out
removed
from
All Registers
are in the
scan chain
architecture
netlist for
ATPG purposes
Control
scan black-box
boundary
Observe-only registers
used for detection of memory
input signals
Gate or Multiplexor is used

to Blockfix to a known
valuethe Memory
Output Signals
Figure 4-16 Black Box Boundaries

Alfred L. Crouch
17

is blocked off
Input is passed
to output as the
form of output
control
Data In
Bypass Data Out
Detection of
incoming
signals
Memory
array
can be
Address
removed
from
netlist for
ATPG purposes
Control
scan black-box
boundary
used for detection of memory
input signals
Multiplexor is used to
pass the input directly
to the output
Figure 4-17 Memory Transparency

Alfred L. Crouch
18
Detection of incoming
data signals done here
is blocked off
Input is passed
to output with
registration
Data In
Bypass Data Out

Memory
In ideal sense,
timing should
also be matched
array
can be
Address
removed
from
netlist for
ATPG purposes
Control
scan black-box
boundary
not needed on data since
register emulates memory
Register and multiplexor

is used to emulate memory
timing and output
Figure 4-18 The Fake Word Technique

Alfred L. Crouch
19
Data Bus: Possibly to Multiple Memory Arrays
Address Bus: Possibly to Multiple Memory Arrays
Data In
Data Out
Memory: data width by address depth
32 x 512
Address
Read/WriteB
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Output Enable
Control Circuitry to Read, Write,

and Data Output Enable
Control Signals: Individual Signals to This Memory Array

Test Must Access the Data, Address, and Control Signals
in order to Test This Memory
Figure 4-19 Memory Test Needs

Alfred L. Crouch
20
Chip Level
Invoke
Retention
Debug
Algorithm Controller
Address Generator
Data Generator
Done
Fail
Debug_data
Memory Array(s)
Comparator
INPUTS
Invoke: Start BIST
Retention: Pause BIST and Memory Clocking
Debug: Enable BIST Bitmap Output
OUTPUTS
Fail: A Memory Has Failed a BIST Test
Done: Operation of BIST Is Complete
Debug_data: Debug Data Output
OPERATIONS
Address: Ability to Apply Address Sequences
Data: Ability to Apply Different Data Sequences
Algorithm: Ability to Apply Algorithmic Control Sequences
Comparator: Ability to Verify Memory Data
Figure 4-20 Memory BIST Requirements

Alfred L. Crouch
Retention
Release
Bitmap
Algorithm Controller
Address Generator
Data Generator
Comparator
Invoke
21
Din
Memory
DI Array Do
Ain
Write_en
WRB
Read_en
CEB
done
Fail
Hold_out
Bitmap_out
Dout
Clk
INPUTS
Invoke: invoke the BIST (apply muxes and release reset)
Retention: enable retention algorithm and pause
Release: discontinue and release pause
Bitmap: enable bitmap output on fail occurrence
OUTPUTS
Fail: sticky fail flagdynamic under bitmap
Done: operation of BIST is complete
Bitmap_out: fail data under bitmap
Hold_out: indication of pause
Figure 4-21 An Example Memory BIST

Alfred L. Crouch
22
Chip Level
bitmap_out1
Memory Array
with BIST
Invoke
done1 fail1
bitmap_out2
Memory Array
with BIST
Reset
Bitmap
done2 fail2
bitmap_out3
Memory Array
with BIST
Hold_1
Hold_2
Hold_3
Hold_4
done3 fail3
bitmap_out4
Memory Array
with BIST
so
s1
done4 fail4
fail 1-4
done 1-4
Invoke: a global signal to invoke all BIST units
Reset: a global signal to hold all BIST units in reset done fail diag_out
Bitmap: a global signal to put all BIST units in debug mode
Hold_#: individual hold signals to place memories in retention
or to select which memory is displayed during debug
done: all memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold mode will present debug data
Figure 4-22 MBIST Integration Issues

Alfred L. Crouch
23
bitmap_out1
Memory Array
with BIST
Invoke
done1
Reset
fail1
bitmap_out2
Memory Array
with BIST
Bitmap
done2
fail2
Hold_1
Memory Array
with BIST
bitmap_out3
Hold_2
done3
fail3
Hold_3
Hold_4
Memory Array
with BIST
done4
bitmap_out4
so
s1
fail4
fail 1-4
done 1-4
Invoke: must be a logic 0 when BIST is not enabled

Reset: should be a logic 0 when BIST is not enabled
done
fail diag_out
Bitmap: should be a logic 0 when BIST is not enabled

Hold_#: should be a logic 0 when BIST is not enabled
done: should not be connected to package output pin when BIST is not enabled
fail: should not be connected to package output pin when BIST is not enabled
diag_out: should not be connected to package output pin when BIST is not enabled
Figure 4-23 MBIST Default Values

Alfred L. Crouch
n
Invoke
n
Reset
n
Bitmap
Hold_1
Hold_2
Hold_n
M
e
m
o
r
y
invoke
1-m
done
A 1-n
r
r
a
y
s
M
e
m m
o
r
y
with fail
1-n
I M
n B debug
d I
e S hold_l1
p T
e s hold_l2
n
d
hold_1m
e
n
t
Bank 1
scan_out
1-n
24
done
A 1-m
r
r
a
y
s
with
fail
1-m
m I M
n B
d I
e S
p T
e s
n
d
e
n
t
Bank 2
m
diag_out
1-m
so
s1
Invoke: global signal invokes bank 1 BIST
Reset: global signal holds bank 1 BIST in reset
diag_out
Bitmap: global signal that enables BIST debug
fail
done
Hold_#: paired hold signals to place memories in retention

or to select which memory is displayed during debug
done: bank n memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold will present debug data
Figure 4-24 Banked Operation

Alfred L. Crouch
25
LFSR - PRPG
DQ
DQ
DQ
CLK
MBIST
Address
Functional
5
A
0
F
Memory Array
MBIST Data In
Data
Functional Data In
Algorithm
Sequencer
MBIST
Control
Functional
Functional & MBIST Data Out
DQ
DQ
Data Out
DQ
CLK
LFSR - MISR
Figure 4-25 LFSR-Based Memory BIST

Alfred L. Crouch
26
The Address sequence can be shifted

both forward and backward to provide
all addresses
The Data sequence can be shifted
across the data lines, and can also
provide data for a comparator
0
0
1
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
Address
Memory Array
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Data
0
1
0
0
1
0
Read/Write
The Control sequence can be

shifted across the read-write
or output enable or other
control signals
Figure 4-26 Shift-Based Memory BIST

Alfred L. Crouch
27
MBIST
Address
Functional
Read-Only Memory Array

MBIST
Functional
Read Control
Functional Data Out
Data Out
MBIST
DQ
DQ
DQ
CLK
LFSR - MISR
Figure 4-27 ROM BIST

Alfred L. Crouch
28
Memory Testing Fundamentals Summary

Memory Testing Is Defect-Based
Memory Testing Is Algorithmic
Different Types of MemoriesDifferent Algorithms
A Memory Fault Model Is Wrong Data on Read
Memory Testing Relies on Multiple-Clue Analysis
A Memory Test Architecture May CoExist with Scan
A Memory Can Block Scan Test Goals
Modern Embedded Memory Test Is BIST-Based
BIST Is the Moving of the Tester into the Chip
BIST-Based Testing Allows Parallelism
Parallel Testing Impacts Retention Testing
Parallel Testing Impacts Power Requirements
Parallel Testing Requires Chip-Level Integration
Figure 4-28 Memory Test Summary

Alfred L. Crouch
Chip-Level
TCU
Core 4
Core 5
Core 1
Core 2
General
Logic
Core 3
Memory Access
Embedded
Memory
PLL
Embedded
Memory
TAP
JTAG Boundary Scan
Figure 5-1 Introduction to Embedded Core Test and Test Integration

Alfred L. Crouch
WHAT IS A CORE?
SOFT
HDL
Model with
No Test
HDL
Model with
Modeled Test
RTL
Model with
No Test
RTL
Model with
Modeled Test
Gate-Level
Netlist with
No Test
Gate-Level
Netlist with
Synthesized Test
Gate-Level
Netlist with
Inserted Test
Gate-Level
Netlist with
Mixed Test
FIRM
HARD
Layout
GDSII with
No Test
Layout
with Test from
Synthesis
Layout
with Test from
Gate-Level
Layout
with Test
Optimization
Figure 5-2 What is a CORE?

Alfred L. Crouch
TMode[3:0]
4
Chip-Level
CTCU
3
Core
UDL
Embedded
Memories
Embedded
Memories
Wrapper
PLL
TAP
JTAG Boundary Scan
- A Core-Based Device May Include 1. Core(s) with Test Wrapper + Embedded Memory Arrays
2. Chip-Level User Defined Logic + Embedded Memory Arrays
3. Chip-Level Test Selection and Control Logic
4. Dedicated Chip-Level Test Pins
5. Chip-Level Clock Generation and Clock Control Logic
6. IEEE 1149.1 Controller and Boundary Scan Logic
Figure 5-3 Chip Designed with Core

Alfred L. Crouch
A Reuse
Embeddable
Core
Business Deliverables
1. The Core
2. The Specification or Data Sheet
3. The Various Models
4. The Integration Guide
5. The Reuse Vectors
Figure 5-4 Reuse Core Deliverables

Alfred L. Crouch
CORE-BASED DESIGN DFT ISSUES

Chip-Level
Device
A KNOWN
STIMULUS
ACCESS
TO THE
EMBEDDED
CORE
A KNOWN
EXPECTED
RESPONSE
Other
Chip-Level Logic
If the Core is HARD DFT must exist before
delivery how is access provided at the chip level?
If the Core is HARD and delivered with pre-generated
vectors how are vectors merged in the whole test program?
If the Core is HARD and part of the overall chip test
environment how is the core test scheduled?
If the Core is HARD and part of the overall chip test
environment what defaults are applied when not active?
If the Core is HARD what is the most economical and
effective test mix Scan? LBIST? MBIST? Functional?
If the Core is SOFT is the overall chip test environment
developed as a Core and UDL or as a unified design?
If the Core operates at a different frequency from the pin
I/O or other chip logic how does this affect DFT and Test?
Figure 5-5 Core DFT Issues

Alfred L. Crouch
A Reuse
Embeddable
Core
DFT Drivers During Core Development

Target Market/business Turnkey versus Customer Design
Target Cost-Performance Profile Low to High
Potential Packages Plastic versus Ceramic
Potential Pin Counts
Core Test Architectures and Interfaces
Direct Access Mux Out Core Terminals
Add-On Test Wrapper Virtual Test Socket
Interface Share-Wrapper Scanned Registered Core I/O
At-Speed Scan Or Logic Built-in Self-test (LBIST)
Design For Reuse Considerations
Dedicated Core Test Ports Access Via IC Pins
Reference Clocks Test and Functional
Test Wrapper Signal Reduction/No JTAG/No Bidis
Virtual Test Socket Vector Reuse
Figure 5-6 Core Development DFT Considerations

Alfred L. Crouch
A Chip Package with

44 Functional Signals
A ReUse
Embeddable
Core with
60 Functional
Signals
Core DFT Interface Considerations

Note none of this is known a priori
Access to core test ports via IC pins (integration)
I/O port count less restrictive than IC pin count
Impact of routing core signals to the chip edge
- Dedicated test signals to place in test mode
- Number of test signals needed to test core
- Frequency requirements of test signals
Figure 5-7 DFT Core Interface Considerations

Alfred L. Crouch
UDL Logic
At the time of Core Development,

the UDL logic is not available
and is configuration is not known
Embedded
Core
DQ
DQ
For example:
- registered inputs or outputs
- combinational logic
- bidirectional signals or tristate busses
QD
QD
How are vectors generated for a Hard
Core before integration?
How are vectors delivered that can
assess the signal timing or frequency?
UDL
Domain
How is test access planned to be

provided through the UDL or directly
from the package pins?
CORE
Domain
Figure 5-8 DFT Core Interface Concerns

Alfred L. Crouch
A Chip Package with

44 Functional Signals
Test Wrapper with 10 Test Signals
A Reuse
Embeddable
Core with
60 Functional
Signals
Core DFT Interface Considerations

Wrapper for interface signal reduction
Wrapper for frequency assessment
Wrapper as frequency boundary
Wrapper as a virtual test socket (for ATPG)
Note: bidirectional functional signals cant
cross the boundary if wrapper or scan
Figure 5-9 DFT Core Interface Considerations

Alfred L. Crouch
UDL Logic
Land between the Lakes

The Isolation Test Wrapper
D Q
DQ
DQ
10
Embedded
Hard Core
DQ
D Q
QD
QD
QD
D Q
UDL Scan
Domain
CORE Scan
Domain
Core-Wrapper Scan
Domain
where the wrapper is the registered
core functional I/F that is
scan-inserted separately
Note: Wrapper and core are on same clock
and path delay is used to generate vectors
Figure 5-10 Registered Isolation Test Wrapper

Alfred L. Crouch
UDL Logic
11

DQ
Embedded
Hard Core
DQ
DQ
D Q
QD
QD
Q D
QD
UDL Scan
Domain
CORE Scan
Domain
Wrapper Scan
Domain
where the wrapper is an added slice
between the core functional I/F
and the UDL functional I/F
Wrapper and core are on different clocks
Figure 5-11 Slice Isolation Test Wrapper

Alfred L. Crouch
UDL Logic
12

Core_Test
TR_SDO
DQ
DQ
DQ
D Q
QD
QD
UDL Scan
Domain
Embedded
Hard Core
TR_SE
TR_SDI
TR_CLK
Wrapper Scan
Domain
TR_Mode
CORE Scan
Domain
System Clock
the wrapper is an added slice
between the core functional I/F
and the UDL functional I/F
Wrapper and core are on different clocks
Figure 5-12 Slice Isolation Test Wrapper Cell

Alfred L. Crouch
Internal BIST In
Direct Test
Signals go
to Package
Pins
Internal BIST Out
Internal Scan In
Internal Scan Out
QD
QD
13
D Q
Q D
D Q
Q D
QD
Wrapper Scan In
D Q
UDL Scan
Domain
UDL Logic
CORE Scan
Domain
Core-Wrapper Scan
Domain
Embedded
Hard Core

All Core Test Interface Signals pass through the

Test Wrapper without being acted upon
All Core I/O are part of the Wrapper Scan Chain
So Total Core Test I/F is:
Internal Scan
Internal MBIST
Wrapper Scan
Figure 5-13 Core DFT Connections through the Test Wrapper

Alfred L. Crouch
14
Internal BIST In
Direct Test
Signals Go
to Package
Pins
Internal Scan In
Test Mode Control
QD
QD
D Q
D Q
Core Test
Controller
QD
Wrapper Scan In
D Q
UDL Scan
Domain
UDL Logic
CORE Scan
Domain
Core-Wrapper Scan
Domain
Embedded
Hard Core

All Core Test Interface Signals pass through the

Test Wrapper and may be acted upon by a Test Mode
All Core I/O are part of the Wrapper Scan Chain
So Total Core Test I/F is:
Gated Internal Scan
Gated Internal MBIST
Gated Wrapper Scan
Figure 5-14 Core DFT Connections with Test Mode Gating

Alfred L. Crouch
15
Cant Use
the
Wrapper
Cell
Wrapper Cell
UDL
Test Wrapper
PLL
Bypass
Test Clock
Mul/Div
Clocks
A Reuse
Embeddable
Hard Core
with Pre-Existing
Clock Trees
Core
Clock Out
Signal(s)
DFT Considerations
Cant Support Bidirectional Core Ports
Input and Reference Clocks
Figure 5-15 Other Core Interface Signal Concerns

Alfred L. Crouch
16
A Chip Package with

a 25 MHz Interface
Test Wrapper with 10 Test Signals
A Reuse
Embeddable
Core with
Fmax = 100MHz
Logic
Core DFT Frequency Considerations

Wrapper for frequency boundary
Test signals designed for low frequency
Package interface designed for high frequency
Wrapper as a multi-frequency ATPG test socket
Note: functional high/low frequency signals can
cross the wrapperthe test I/F is the concern
Figure 5-16 DFT Core Interface Frequency Considerations

Alfred L. Crouch
The Cores Test Port

Internal Scan Data In
Internal Scan Enable
Wrapper Scan Data In
Wrapper Scan Enable
Wrapper Test Enable
MemBIST Invoke
MemBIST Retention
MemBIST Bitmap
Internal Scan Data Out
Wrapper Scan Data Out
MemBIST Fail
MemBIST Done
MemBIST Bitmap Out
17
A Test Wrapper
A Reuse
Embeddable
Core with
Existing DFT
and Test Features
Core DFT Goals and Features

Embedded Memory Test by MBIST
- Few Signals High Coverage Less Test Time
- Bitmap Characterization Support
Structure by Stuck-At Scan
- High Coverage Fewer Vectors Ease of Application
Frequency by At-Speed Scan (Path & Transition Delay)
- Deterministic Fewer Vectors Ease of Application
Reuse of Core Patterns Independent of Integration
Test Insulation from Customer Logic
Embedded Core I/O Timing Specifications with Wrapper
Minimize Test Logic Area Impact
Minimize Test Logic Performance Penalty
DFT Scannability Logic
Full-Scan Single-Edge Triggered MUX DFF
Tristate Busses - Contention/Float Prevention
Negedge Inputs and Outputs
IddqNo Active Logic and Clock Stop Support
Figure 5-17 A Reuse Embedded Cores DFT Features

Alfred L. Crouch
18
A Test Wrapper
The Cores Test Port

Internal Scan Data In
Internal Scan Enable
Wrapper Scan Data In
Wrapper Scan Enable
Wrapper Test Enable
MemBIST Invoke
MemBIST Retention
MemBIST Bitmap
Internal Scan Data Out
Wrapper Scan Data Out
MemBIST Fail
MemBIST Done
MemBIST Bitmap Out
A Reuse
Embeddable
Core with
Existing DFT
and Test Features
Core Economic Considerations

Test Integration (Time-to-Market)
Core Area and Routing Impact (Silicon/Package Cost)
Core Power and Frequency Impact (Package/Pin Cost)
Core Test Program Time/Size/Complexity (Tester Cost)
Time
and/or
Tester
Memory
Retention Testing
Chip Logic Testing
Total
Chip
Test
Program
Budget(s)
Memory Testing
Embedded Core Testing
Chip Parametrics
Figure 5-18 Core Test Economics

Alfred L. Crouch
19
TMode[3:0]
Chip-Level
CTCU
Core
UDL
Embedded
Memories
Embedded
Memories
Wrapper
PLL
TAP
JTAG Boundary Scan
- A Core-Base Device May Include Core(s) with Test Wrapper and Embedded Memory Arrays
Chip-Level Non-Core Logic with Embedded Memory Arrays
Chip-Level Test Selection and Control Logic
Dedicated Chip-Level Test Pins
Chip-Level Clock Generation and Control Logic
IEEE 1149.1 Controller and Boundary Scan Logic
Figure 5-19 Chip with Core Test Architecture

Alfred L. Crouch
20
Pre-Existing
Vectors
Chip-Level
CTCU
Test Selection
Wrapper and
Core Scan
Package Pin
Connections
Core
UDL
PLL
Clock Bypass
TAP
JTAG Boundary Scan
Figure 5-20 Isolated Scan-Based Core-Testing

Alfred L. Crouch
21
Development
Generated Vectors
Chip-Level
CTCU
Wrapper and
UDL Scan
Package Pin
Connections
Test Selection
UDL
Clock Bypass
PLL
TAP
JTAG Boundary Scan
Figure 5-21 Scan Testing the Non-Core Logic

Alfred L. Crouch
22
Development
Generated Vectors
Chip-Level
CTCU
Wrapper and
UDL Scan
Package Pin
Connections
Test Selection
UDL
Clock Bypass
PLL
TAP
JTAG Boundary Scan
I/O specification testingbus_SE

Tristate busses - contention/float prevention
IddqHighZ pin
Pin requirements(open drains)
Figure 5-22 Scan Testing the Non-Core Logic

Alfred L. Crouch
23
Development
Generated Vectors
Chip-Level
CTCU
Test Selection
Core
UDL
Embedded
Memories
Embedded
Memories
Wrapper
PLL
Clock Bypass
TAP
JTAG Boundary Scan
Figure 5-23 Memory Testing the Device

Alfred L. Crouch
24
Chip-Level
CTCU
Core 4
Core 5
Core 1
Core 2
General
Logic
Core 3
Memory Access
Embedded
Memory
PLL
Embedded
Memory
TAP
JTAG Boundary Scan
Chip-level DFT integration considerations

each core/vector set must have:
1. Power Rating during Test
2. Frequency/Data Rate of Test Vectors
3. Fault Coverage of the Test Vectors
4. Required Test Architecture to Reuse Vectors
5. ATPG Test Wrapper or Encrypted Sim Model
6. The Vector Sets Format
7. The Vector Set Sizing
Figure 5-24 DFT Integration Architecture

Alfred L. Crouch
25
Chip Parametrics
Chip Iddq (Merged)
Core 1 Test Components
Chip-Level Memory
Chip-Level Analog
Core 1 Components
Core 1 Iddq
Core 1 Scan
Core 1 Memory Test
Core 1 Analog
Test
Time
in (s)
3
4
# of Cores

Alfred L. Crouch
26
Receiving Core DFT Specification

Driven by Fab and Integration Requirements
Core DFT Specification Items
- Test Mix
- Style of Test
- Maximum Number of Integration Signals
- Minimum-Maximum Test Frequency
- Maximum Vector Sizing
- Minimum Fault Coverage
- Clock Source
Figure 5-26 Selecting or Receiving a Core

Alfred L. Crouch
27
Core Test Driven by Cost-of-Test and TTM

Two Concerns: Reuse and Integration
Reuse: Interface, Clocks, Test Features
- number of dedicated test signal
- size of test integration interface
- ability to test interface timing
- no functional bidirectional ports
- specifications and vectors based on clock-in
- specifications and vectors based on clock-out
- ability to stop clock for retention or Iddq
- number of clock domains
- at-speed full scan
- at-speed memory BIST
- use of a scan test wrapper
- self-defaulting safety logic
Integration: Core Connections, Chip Test Modes
- simple core integration
- reuse of pre-existing vectors
- application of test signal defaults
- shared resources (pins and control logic)
- shared testing (parallel scheduling)
- chip level test controller
Figure 5-27 Embedded Core DFT Summary

Alfred L. Crouch

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Chapter 1 Test and Design-for-Test Fundamentals