Introduction to Sequential Logic Design

Flip-flops

Prev
Latches
S-R
S-bar-R-bar
S-R

with enable signal

FF vs. Latch

Latches and flip-flops (FFs) are the basic building

blocks of sequential circuits.

latch: bistable memory device with level sensitive triggering

(no clock), watches all of its inputs continuously and changes
its outputs, independent of a clocking signal.
flip-flop: bistable memory device with edge-triggering (with
clock), samples its inputs, and changes its output only at
times determined by a clocking signal.

Edge triggered D Flip-Flop

A D

FF combines a pair of D latches.

Master/slave
D FF
Positive-edge-triggered

D FF
Negative-edge-triggered D FF
Edge-Triggered D FF with Enable
Scan FF
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Positive-Edge-triggered D flip-flop

Positive-Edge-triggered D flip-flop

Dynamic-input
indicator

Edge-triggered D flip-flop behavior

Edge-triggered D flip-flop behavior

Edge-triggered D flip-flop behavior

D flip-flop timing parameters

Propagation delay (from CLK)

Setup time (D before CLK)
Hold time (D after CLK)

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D FF with asynchronous inputs

Force the D FF to a particular state
independent of the CLK and D inputs. PR
(Preset) and CLR (Clear)

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Negative-edge triggered D FF
Simply

inverts the clock input. Active low.

12

Negative-edge triggered D FF
Simply

inverts the clock input. Active low.

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J-K flip-flops

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T (toggle) flip-flops
AT

FF changes state on every tick of the clock. (be toggled on every tick)
has precisely half the frequency of the T.
Important for counters
Positive-edge-triggered T FF
Q

How

to build T FF using J-K FF and D FF?

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T (toggle) flip-flops with enable

How

to build a T FF with enable using?

D FF
J-K FF

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T (toggle) flip-flops with enable

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Next
FSM

analysis
Read Ch-7.3

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