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  • 8x8 FIFO Buffer VHDL Design

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    IgnacioMartí
    255 views2 pages
    This VHDL code defines a FIFO8x8 entity that implements a first-in first-out buffer with 8-bit data width and depth of 8. It contains ports for reset, clock, read, write, empty, full and data input/output. The architecture contains signals to track the read and write counters, empty and full status. On each clock edge, it checks the read and write conditions and increments/decrements the counters accordingly while shifting data in and out of the internal register array.

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    8x8 FIFO Buffer

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    This VHDL code defines a FIFO8x8 entity that implements a first-in first-out buffer with 8-bit data width and depth of 8. It contains ports for reset, clock, read, write, empty, full and data input/output. The architecture contains signals to track the read and write counters, empty and full status. On each clock edge, it checks the read and write conditions and increments/decrements the counters accordingly while shifting data in and out of the internal register array.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    255 views2 pages

    8x8 FIFO Buffer VHDL Design

    Uploaded by

    IgnacioMartí
    This VHDL code defines a FIFO8x8 entity that implements a first-in first-out buffer with 8-bit data width and depth of 8. It contains ports for reset, clock, read, write, empty, full and data input/output. The architecture contains signals to track the read and write counters, empty and full status. On each clock edge, it checks the read and write conditions and increments/decrements the counters accordingly while shifting data in and out of the internal register array.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    of 2

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity FIFO8x8 is
    port (
    reset, clk, r, w : in std_logic;
    empty, full
    : out std_logic;
    d
    : in std_logic_vector(7 downto 0);
    q
    : out std_logic_vector(7 downto 0));
    end FIFO8x8;
    architecture Behavioral of FIFO8x8 is
    constant m
    constant
    signal
    subtype
    type
    signal
    signal
    signal

    : integer := 8;
    n
    : integer := 8;
    rcntr, wcntr
    : std_logic_vector(2 downto 0);
    wrdtype is std_logic_vector(n - 1 downto 0);
    regtype is array(0 to m - 1) of wrdtype;
    reg
    : regtype;
    rw
    : std_logic_vector(1 downto 0);
    full_buf, empty_buf : std_logic;

    begin
    rw <= r & w;
    seq : process(reset, clk)
    begin
    if reset = '1' then
    rcntr
    <= (others => '0');
    wcntr
    <= (others => '0');
    empty_buf <= '1';
    full_buf <= '0';
    for j in 0 to m - 1 loop
    reg(j) <= (others => '0');
    end loop;
    elsif falling_edge(clk) then
    case rw is
    when "11" =>
    -- read and write at the same time
    rcntr
    <= rcntr + 1;
    wcntr
    <= wcntr + 1;
    reg(conv_integer(wcntr)) <= d;
    when "10" =>
    -- only read
    if empty_buf = '0' then
    -- not empty
    if (rcntr + 1) = wcntr then
    empty_buf <= '1';
    end if;
    rcntr <= rcntr + 1;
    end if;
    full_buf <= '0';
    when "01" =>
    -- only write
    empty_buf <= '0';

    if full_buf = '0' then


    -- not full
    reg(conv_integer(wcntr)) <= d;
    if (wcntr + 1) = rcntr then
    full_buf <= '1';
    end if;
    wcntr <= wcntr + 1;
    end if;
    when others =>
    null;
    end case;
    end if;
    end process;
    q
    <= reg(conv_integer(rcntr));
    full <= full_buf;
    empty <= empty_buf;

    end Behavioral;

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