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Sequential Circuits For Registers and Counters
Sequential Circuits For Registers and Counters
Sequential Circuits For Registers and Counters
Lesson 2
Shift Registers
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Outline
Shift Register
Serial-In Serial-Out Register
Serial-In Parallel-Out Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift
Register
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Clock Edges
Shift register looks upon the data bits
at DD DC DB DA inputs (= Qs of
previous state only) at the instant of a
falling edge (-ve edge) in case of -ve
edge D-FFs are used and at rising edge
in case +ve edge D-FFs are used.
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Outline
Shift Register
Serial-In Serial-Out Register
Serial-In Parallel-Out Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift
Register
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
QA
D-FF D
QB
D-FF D
QC
D-FF
QD
D-FF SerialOut
CLK (shift)
10
QA
D-FF
D
QB
D-FF
D
QC
D-FF
QD
D-FF
SerialIn
CLK (shift)
11
CLK
(shift)
1 or 0
Serial in
QA
QB
QC
QD Serial out
t
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
12
CLK
(shift)
1 or 0
Serial-in
QA Serial out
QB
QC
QD
t
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
13
Shift Register
A shift register shifts the transfers the
input D bits to next Qs such that Qi
(n+1) = Di after an interval from nth
clock edge instance plus propagation
delay
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
14
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
15
Outline
Shift Register
Serial-In Serial-Out Register
Serial-In Parallel-Out Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift
Register
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
16
QA
QA
D-FF D
QB
QB
D-FF D
QC
D-FF
QC
QD
QD
D-FF SerialOut
CLK (shift)
17
QA
D-FF
QB
QB
D-FF
QC
QC
D-FF
QD
D
QD
D-FF
SerialIn
CLK (shift)
18
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
19
Outline
Shift Register
Serial-In Serial-Out Register
Serial-In Parallel-Out Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift Register
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
20
XB
XA
XC
XD
L/S
D
PR QA
D-FF D
PR QB
D-FF D
S
R
PR QD QD
PR QC
D-FF
S
R
D-FF
SerialOut
R
CLR
CLK (shift)
4- bit Right Shift Register PISO using D-FFs; L/S
means load when 1 and shift when 0.
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
21
XB
XA
XC
XD
L/S
QA
PR
QB
D-FF D
PR
D-FF D
S
R
QC
PR
D-FF
S
R
QD
PR
D D-FF
S
R
CLR
CLK (shift)
Serial- Out at QA
22
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
23
24
Outline
Shift Register
Serial-In Serial-Out Register
Serial-In Parallel-Out Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift
Register
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
25
XB
XA
XC
XD
L/S
D
PR QB
PR QA
D-FF D
D-FF D
D-FF
YA
QB
YB
QC
SerialOut
R
CLR
CLK (shift)
OE
QA
D-FF
PR QD QD
PR QC
YD
YC
QD
26
XB
XA
XC
XD
L/S
QA
PR
QB
D-FF D
PR
D-FF D
PR
D-FF
R
CLK (shift)
OE
Serial- Out at QA
YA
QA
QC
YB
QB
QC
QD
PR
D D-FF
S
R
CLR
Left Shift PIPO
YD
YC
QD
27
28
29
30
Summary
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
31
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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33
End of Lesson 2 on
Shift Registers
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
34
Thank You
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
35