And now, I am presenting to everyone about FSK demodulation.

This is block
diagram of FSK demodulation
FSK DEMODULATOR

Almost all FSK modulator use PLL.

Do you remember anything about PLL?
PLL consisting of a Phase detector, LPF, and VCO. PLL is a locked loop. A phase detector
compares two input signals and produces an error signal which is proportional to their phase
difference. The error signal is then low-pass filtered and used to drive a VCO VCO keep the input
and output phase in lock step also implies keeping the input and output frequencies the same.
This circuit is based on PLL made of IC 4046. The free running frequency of PLL is
set at 320 kHz value. Hence when FSK signal having two frequency 320 kHz and
640 kHz is given to it input, it produced demodulated signal locked to 320 kHz.
Hence output is raw data signal. This signal is then given to squarer circuit.
DATA SQUARER (COMPARATOR) SECTION:

This section converts raw data output of FSK demodulator into pure recovered data
using comparator IC311
Variable resistor is used to vary voltage comparator.
This is experiment results group 6 implement and measure.