EE 739 Processor Design

Assignment 1
Vikas Jha
11D070024

Single cycle implementation

of
LC-3 ISA.

REGWR

JMP,BRZ

MEMADR

N,Z,P

ALUSRC

EXTCTRL

REGCTRL

REGSRC

TRAPCTRL

Control

+2

R,WR

MUX

ALU
9-15, 4,5

0-2
9-11

SR2

Mux

DST

Write

MUX

Instruction
Memory

SR1

ALU

SR2 data
MUX

6-8

Sign Extension
5 to 16 bit

Zero Extension
4-16

Shift Left
by 1
ALU
Control

0
1
2

MUX

Zero Extension
8 to 16

MUX

Sign Extension
11 to 16 bit

Data
Mem.

The i/p of mux are in

ascending order of (select)
from top to bottom

Sign Extension
6 to 16 bit
Sign Extension
9 to 16 bit

MUX

REG
File

111

PC

SR1 data

Control Logic : Truth Table

Instruction

Instruction bits

N,Z,P

REGCTRL

15-12

11

10

ADD reg

0001

111

00

00

00

10

ADD immediate

0001

101

000

10

00

00

10

AND reg

0101

111

00

00

00

10

AND immediate

0101

101

000

10

00

00

10

0000

1xx

000

010

00

10

x1x

000

010

00

10

xx1

000

010

00

10

000

000

00

00

BR

REGSRC TRAPCTRL SR1,SR2,Dest EXTCTRL ALUSRC MEMADR R,WR JMP,BRZ REGWR

JMP

1100

100

00

01

JSR

0100

000

011

00

10

JSRR

0100

100

00

01

LDB

0010

101

001

10

10

00

10

LDW

0110

101

001

01

10

00

10

LEA

1110

001

010

01

00

00

10

RTI

1000

100

01

10

00

10

LSHF

1101

101

101

10

00

00

10

RSHFL

1101

101

101

10

00

00

10

RSHFA

1101

101

101

10

00

00

10

STB

0011

110

001

10

01

00

STW

0111

110

001

10

01

00

TRAP

1111

001

100

01

10

11

01

XOR reg

1001

111

00

00

00

10

XOR immediate

1001

101

10

00

00

10

The bits of REGCTRL denote whether SR1 register is read, SR2 register is read and data is written to Dest. register respectively.

Multi-cycle implementation
of
LC-3 ISA

Cycle ->
Instruction

1st

IR
Memory[PC];
AND,ADD,XOR
PC PC+2
reg
IR
AND,ADD,XOR, Memory[PC];
NOT
PC PC+2
immediate

BR

JMP/RET/JSRR

IR
Memory[PC];
PC PC+2

IR
Memory[PC];
PC PC+2

IR
Memory[PC];
PC PC+2
JSR

LDB

2nd
A Reg(SR1);

3rd

4th

ALUOut A op B

Reg(DST)ALUO
ut

ALUOut A op
sext(IR(4:0))

Reg(DST)ALUO
ut

5th

B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1
A Reg(SR1);
B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1
A Reg(SR1);

If(N|P|Z)PC
ALUOut

B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1
A Reg(SR1);

ALUOut SrcA

PC ALUOut

B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1
A Reg(SR1);

PC ALUOut

B Reg(SR2)
ALUOut PC +
ALUOut PC +
(sext IR[10:0]) <<
(sext IR[8:0]) << 1
1

IR
Memory[PC];
PC PC+2

A Reg(SR1);

B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1

ALUOut A +
sext(IR(5:0))

MDR
mem(ALUOut)

Reg(DST)MDR

6th

7th

8th

LEA

IR
Memory[PC];

A Reg(SR1);

PC PC+2

B Reg(SR2)

ALUOut A +
sext(IR(9:0))<<1

MDR
mem(ALUOut)

Reg(DST)MDR

A R6

ALUOut A

MDR
PC MDR
mem(ALUOut)

ALUOut PC +
(sext IR[8:0]) << 1

RTI

IR
Memory[PC];

A Reg(SR1);

PC PC+2

B Reg(SR2)

ALUOUT A+2 R6 ALUOut

ALUOut PC +
(sext IR[8:0]) << 1

SHF

IR
Memory[PC];

A Reg(SR1);

PC PC+2

B Reg(SR2)

ALUOut A
shift(zext(3:0))

Reg(dest)<ALUOut

ALUOut A +
sext(5:0)

Mem(ALUOut) =
B

ALUOut A +
sext(5:0)<<1

Mem(ALUOut) =
B

ALUOut PC +
(sext IR[8:0]) << 1

STB

IR
Memory[PC];
PC PC+2

A Reg(SR1);
B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1

STB

IR
Memory[PC];
PC PC+2

A Reg(SR1);
B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1

TRAP

IR
Memory[PC];

A Reg(SR1);

PC PC+2

B Reg(SR2)
ALUOut PC +
(sext IR[8:0]) << 1

ALUOut ALU
MDR
R7 = ALUOut
PC MDR
PC
mem(ALUOut)
ALUOut ALU
zext(8:0)

MDR
mem(ALUOut PSR MDR
)
ALUOut
R6 ALUOut
A+2

MUX
RegCtrl
PCsrc

DataWr

Register File

110

SR2

Sign Extension
5 to 16 bit

2
ALUsrcB

RegWr
ALU
Control

Sign Extension
6 to 16 bit

Sign Extension
11 to 16 bit

Shift
Left
by
1

MUX

Sign Extension
9 to 16 bit

111

MUX

Memory Data
Register (MDR)

DST

Zero Extension
8 to 16

0
Extsrc

The i/p of mux are in

ascending order of (select)
from top to bottom

MUX

Zero Extension
4-16

ALU out
Register

9-11

ALUsrcA

ALU

SR2

MUX

Instruction
Register (IR)

RegDst
MUX

Memory

SR1
SR1

Mux

PC

6-8
0-2
Mux

MUX
MemAddr

RegSrc2

Mux

Mem R,Wr