Tanta University

Faculty of Engineering
2nd Computer and Control Engineering

Computer Architecture

Report
Name : Saber
Mahmoud Attia

Section : 2
Dr. Mahmoud
Alshewimy
Branch if equal
When 10110 =>
regSel <= instrReg (5 down to 3);
regRD <= 1;
next-state <= beqI2;
when beqI2 =>
regSel <= instrReg (5 down to 3);
regRD <= 1;
OPRegWR <= 1;
Next-state <= beqI3 ;
When beqI3 =>
OPReg <= 1;
regSel <= instrReg (2 down to 0);
regRD <= 1;

CompSel <= eq;

Next-state <= beqI4 ;
When beqI4 =>
OPReg <= 1 after 1 nsec;
regSel <= instrReg (2 down to 0);
regRD <= 1;
compSel <= eq;
if compout = 1 then
next-state <= beqI5;
else
next-state <= incPC;
endif;
when beqI5 =>
regSel <= instrReg (2 down to 0);
regRD <= 1;
OPRegWR <= 1;
Next-state <= beqI6 ;
When beqI6 =>
OutReg <= 1;
AluSel <= alupass;
Shiftsel <= shiftpass;
OutRegWR <= 1;
Next-state <= beqI7 ;

When bltI7 =>

outRegRD <= 1;
ProgcntWR <= 1 ;
next-state <= loadPC;

Branch if not equal

When 10010 =>
regSel <= instrReg (5 down to 3);
regRD <= 1;
next-state <= bNeqI2;
when bNeqI2 =>
regSel <= instrReg (5 down to 3);
regRD <= 1;
OPRegWR <= 1;
Next-state <= bNeqI3 ;
When bNeqI3 =>
OPReg <= 1;
regSel <= instrReg (2 down to 0);
regRD <= 1;
CompSel <= Neq;

Next-state <= bNeqI4 ;

When bNeqI4 =>
OPReg <= 1 after 1 nsec;
regSel <= instrReg (2 down to 0);
regRD <= 1;
compSel <= Neq;
if compout = 1 then
next-state <= bNeqI5;
else
next-state <= incPC;
endif;
when bNeqI5 =>
regSel <= instrReg (2 down to 0);
regRD <= 1;
OPRegWR <= 1;
Next-state <= bNeqI6 ;
When bNeqI6 =>
OutReg <= 1;
AluSel <= alupass;
Shiftsel <= shiftpass;
OutRegWR <= 1;
Next-state <= bNeqI7 ;
When bNeqI7 =>

outRegRD <= 1;
ProgcntWR <= 1 ;
next-state <= loadPC;

Branch if greader
than
When 10100 =>
RegSel <= instrReg (5 down to 3);
regRD <= 1;
next-state <= bgtI2;
when bgtI2 =>
regSel <= instrReg (5 down to 3);
regRD <= 1;
OPRegWR <= 1;
Next-state <= bgtI3 ;
When bgtI3 =>
OPReg <= 1;
regSel <= instrReg (2 down to 0);
regRD <= 1;
CompSel <= gt;

Next-state <= bgtI4 ;

When bgtI4 =>
OPReg <= 1 after 1 nsec;
regSel <= instrReg (2 down to 0);
regRD <= 1;
compSel <= gt;
if compout = 1 then
next-state <= bgtI5;
else
next-state <= incPC;
endif;
when bgtI5 =>
regSel <= instrReg (2 down to 0);
regRD <= 1;
OPRegWR <= 1;
Next-state <= bgtI6 ;
When bgtI6 =>
OutReg <= 1;
AluSel <= alupass;
Shiftsel <= shiftpass;
OutRegWR <= 1;
Next-state <= bgtI7 ;
When bgtI7 =>

outRegRD <= 1;
ProgcntWR <= 1 ;
next-state <= loadPC;

Branch if less than

When 10001 =>
RegSel <= instrReg (5 down to 3);
regRD <= 1;
next-state <= bltI2;
when bltI2 =>
regSel <= instrReg (5 down to 3);
regRD <= 1;
OPRegWR <= 1;
Next-state <= bltI3 ;
When bltI3 =>
OPReg <= 1;
regSel <= instrReg (2 down to 0);
regRD <= 1;
CompSel <= lt;
Next-state <= bltI4 ;

When bltI4 =>

OPReg <= 1 after 1 nsec;
regSel <= instrReg (2 down to 0);
regRD <= 1;
compSel <= lt;
if compout = 1 then
next-state <= bltI5;
else
next-state <= incPC;
endif;
when bltI5 =>
regSel <= instrReg (2 down to 0);
regRD <= 1;
OPRegWR <= 1;
Next-state <= bltI6 ;
When bltI6 =>
OutReg <= 1;
AluSel <= alupass;
Shiftsel <= shiftpass;
OutRegWR <= 1;
Next-state <= bltI7 ;
When bltI7 =>
outRegRD <= 1;

ProgcntWR <= 1 ;
next-state <= loadPC;